Gerald Pfeifer [Sun, 28 Mar 2021 21:34:35 +0000 (23:34 +0200)]
doc: Update link to "Memory Model" paper
gcc/ChangeLog:
* doc/analyzer.texi (Analyzer Internals): Update link to
"A Memory Model for Static Analysis of C Programs".
François Dumont [Fri, 26 Mar 2021 20:22:52 +0000 (21:22 +0100)]
libstdc++: _GLIBCXX_DEBUG Fix allocator-extended move constructor
libstdc++-v3/ChangeLog:
* include/debug/forward_list
(forward_list(forward_list&&, const allocator_type&)): Add noexcept qualification.
* include/debug/list (list(list&&, const allocator_type&)): Likewise and add
call to safe container allocator aware move constructor.
* include/debug/vector (vector(vector&&, const allocator_type&)):
Fix noexcept qualification.
* testsuite/23_containers/forward_list/cons/noexcept_move_construct.cc:
Add allocator-extended move constructor noexceot qualification check.
* testsuite/23_containers/list/cons/noexcept_move_construct.cc: Likewise.
Christophe Lyon [Sun, 28 Mar 2021 18:59:06 +0000 (18:59 +0000)]
testsuite/arm: Improve scan-assembler in pr96770.c
I'm seeing random scan-assembler-times failures in pr96770.c when LTO is used.
I suspect this is because the \\+4 string matches the LTO sections, sometimes.
This small patch avoids the issue, by matching arr\\+4 instead of \\+4.
2021-03-28 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
PR target/96770
* gcc.target/arm/pure-code/pr96770.c: Improve scan-assembler-times.
Paul Thomas [Sun, 28 Mar 2021 15:48:27 +0000 (16:48 +0100)]
Fortran: Fix problem with runtime pointer check [PR99602].
2021-03-28 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran/ChangeLog
PR fortran/99602
* trans-expr.c (gfc_conv_procedure_call): Use the _data attrs
for class expressions and detect proc pointer evaluations by
the non-null actual argument list.
gcc/testsuite/ChangeLog
PR fortran/99602
* gfortran.dg/pr99602.f90: New test.
* gfortran.dg/pr99602a.f90: New test.
* gfortran.dg/pr99602b.f90: New test.
* gfortran.dg/pr99602c.f90: New test.
* gfortran.dg/pr99602d.f90: New test.
Iain Buclaw [Sun, 28 Mar 2021 14:40:23 +0000 (16:40 +0200)]
d: Predefine the D_PIE version condition when flag_pie is set.
Same as the D_PIC version condition, which is set by flag_pic.
gcc/d/ChangeLog:
* d-builtins.cc (d_init_versions): Predefine D_PIE if flag_pie is set.
Iain Buclaw [Thu, 25 Mar 2021 23:57:54 +0000 (00:57 +0100)]
d: Don't create gdc.test symlink in the gdc testsuite directory
Instead, tests are copied from the source tree (i.e: $srcdir/compilable)
into the test base directory ($base_dir/compilable). A dejagnu test
file with all translated test directives is created in a path that
follows DejaGnu naming conventions ($base_dir/gdc.test/compilable),
which is then passed to `dg-test'.
Before invoking the compiler, the gdc.test prefixed is trimmed from the
test program in `gdc-dg-test' so that all copied test files are picked
up with the correct path names.
gcc/testsuite/ChangeLog:
* lib/gdc-utils.exp (gdc-copy-extra): Rename to...
(gdc-copy-file): ... this. Use file copy instead of open/close.
(gdc-convert-test): Save translated dejagnu test to gdc.test
directory, only write dejagnu directives to the test file.
(gdc-do-test): Don't create gdc.test symlink.
Iain Buclaw [Sat, 27 Mar 2021 01:31:45 +0000 (02:31 +0100)]
d: Define language hook for LANG_HOOKS_ENUM_UNDERLYING_BASE_TYPE
The underlying base type for enumerals are always present in TREE_TYPE.
gcc/d/ChangeLog:
* d-lang.cc (d_enum_underlying_base_type): New function.
(LANG_HOOKS_ENUM_UNDERLYING_BASE_TYPE): Set as
d_enum_underlying_base_type.
Iain Buclaw [Sun, 16 Jun 2019 16:12:47 +0000 (18:12 +0200)]
d: Use COMPILER_FOR_BUILD to build all D front-end generator programs
This means the correct config headers are included when building the
D front-end in a Canadian cross configuration.
gcc/d/ChangeLog:
* Make-lang.in (DMDGEN_COMPILE): Remove.
(d/%.dmdgen.o): Use COMPILER_FOR_BUILD and BUILD_COMPILERFLAGS to
build all D generator programs.
(D_SYSTEM_H): New macro.
(d/idgen.dmdgen.o): Add dependencies to build.
(d/impcnvgen.dmdgen.o): Likewise.
* d-system.h: Include bconfig.h if GENERATOR_FILE is defined.
Iain Buclaw [Sun, 14 Mar 2021 17:11:14 +0000 (18:11 +0100)]
d: Don't generate per-module wrapper for calling DSO constructor/destructor.
The static constructor/destructor list only ever has one function to
call in it, so mark the gdc.dso_ctor and gdc.dso_dtor functions as
static ctor/dtor directly instead.
gcc/d/ChangeLog:
* config-lang.in (gtfiles): Remove modules.cc.
* modules.cc (struct module_info): Remove GTY marker.
(static_ctor_list): Remove variable.
(static_dtor_list): Remove variable.
(register_moduleinfo): Directly set DECL_STATIC_CONSTRUCTOR on
dso_ctor, and DECL_STATIC_DESTRUCTOR on dso_dtor.
(d_finish_compilation): Remove static ctor/dtor handling.
gcc/testsuite/ChangeLog:
* gdc.dg/gdc270a.d: Removed.
* gdc.dg/gdc270b.d: Removed.
GCC Administrator [Sun, 28 Mar 2021 00:16:17 +0000 (00:16 +0000)]
Daily bump.
Steve Kargl [Sat, 27 Mar 2021 22:02:16 +0000 (15:02 -0700)]
fortran: Fix off-by-one in buffer sizes.
gcc/fortran/ChangeLog:
* misc.c (gfc_typename): Fix off-by-one in buffer sizes.
GCC Administrator [Sat, 27 Mar 2021 00:16:27 +0000 (00:16 +0000)]
Daily bump.
David Edelsohn [Sun, 14 Mar 2021 19:09:21 +0000 (15:09 -0400)]
aix: ABI struct alignment (PR99557)
The AIX power alignment rules apply the natural alignment of the
"first member" if it is of a floating-point data type (or is an aggregate
whose recursively "first" member or element is such a type). The alignment
associated with these types for subsequent members use an alignment value
where the floating-point data type is considered to have 4-byte alignment.
GCC had been stripping array type but had not recursively looked
within structs and unions. This also applies to classes and
subclasses and, therefore, becomes more prominent with C++.
For example,
struct A {
double x[2];
int y;
};
struct B {
int i;
struct A a;
};
struct A has double-word alignment for the bare type, but
word alignment and offset within struct B despite the alignment of
struct A. If struct A were the first member of struct B, struct B
would have double-word alignment. One must search for the innermost
first member to increase the alignment if double and then search for
the innermost first member to reduce the alignment if the TYPE had
double-word alignment solely because the innermost first member was
double.
This patch recursively looks through the first member to apply the
double-word alignment to the struct / union as a whole and to apply
the word alignment to the struct or union as a member within a struct
or union.
This is an ABI change for GCC on AIX, but GCC on AIX had not correctly
implemented the AIX ABI and had not been compatible with the IBM XL
compiler.
Bootstrapped on powerpc-ibm-aix7.2.3.0.
gcc/ChangeLog:
* config/rs6000/aix.h (ADJUST_FIELD_ALIGN): Call function.
* config/rs6000/rs6000-protos.h (rs6000_special_adjust_field_align):
Declare.
* config/rs6000/rs6000.c (rs6000_special_adjust_field_align): New.
(rs6000_special_round_type_align): Recursively check innermost first
field.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr99557.c: New.
Jakub Jelinek [Fri, 26 Mar 2021 23:20:42 +0000 (00:20 +0100)]
dwarf2cfi: Defer queued register saves some more [PR99334]
On the testcase in the PR with
-fno-tree-sink -O3 -fPIC -fomit-frame-pointer -fno-strict-aliasing -mstackrealign
we have prologue:
0000000000000000 <_func_with_dwarf_issue_>:
0: 4c 8d 54 24 08 lea 0x8(%rsp),%r10
5: 48 83 e4 f0 and $0xfffffffffffffff0,%rsp
9: 41 ff 72 f8 pushq -0x8(%r10)
d: 55 push %rbp
e: 48 89 e5 mov %rsp,%rbp
11: 41 57 push %r15
13: 41 56 push %r14
15: 41 55 push %r13
17: 41 54 push %r12
19: 41 52 push %r10
1b: 53 push %rbx
1c: 48 83 ec 20 sub $0x20,%rsp
and emit
00000000 0000000000000014 00000000 CIE
Version: 1
Augmentation: "zR"
Code alignment factor: 1
Data alignment factor: -8
Return address column: 16
Augmentation data: 1b
DW_CFA_def_cfa: r7 (rsp) ofs 8
DW_CFA_offset: r16 (rip) at cfa-8
DW_CFA_nop
DW_CFA_nop
00000018 0000000000000044 0000001c FDE cie=
00000000 pc=
0000000000000000..
00000000000001d5
DW_CFA_advance_loc: 5 to
0000000000000005
DW_CFA_def_cfa: r10 (r10) ofs 0
DW_CFA_advance_loc: 9 to
000000000000000e
DW_CFA_expression: r6 (rbp) (DW_OP_breg6 (rbp): 0)
DW_CFA_advance_loc: 13 to
000000000000001b
DW_CFA_def_cfa_expression (DW_OP_breg6 (rbp): -40; DW_OP_deref)
DW_CFA_expression: r15 (r15) (DW_OP_breg6 (rbp): -8)
DW_CFA_expression: r14 (r14) (DW_OP_breg6 (rbp): -16)
DW_CFA_expression: r13 (r13) (DW_OP_breg6 (rbp): -24)
DW_CFA_expression: r12 (r12) (DW_OP_breg6 (rbp): -32)
...
unwind info for that. The problem is when async signal
(or stepping through in the debugger) stops after the pushq %rbp
instruction and before movq %rsp, %rbp, the unwind info says that
caller's %rbp is saved there at *%rbp, but that is not true, caller's
%rbp is either still available in the %rbp register, or in *%rsp,
only after executing the next instruction - movq %rsp, %rbp - the
location for %rbp is correct. So, either we'd need to temporarily
say:
DW_CFA_advance_loc: 9 to
000000000000000e
DW_CFA_expression: r6 (rbp) (DW_OP_breg7 (rsp): 0)
DW_CFA_advance_loc: 3 to
0000000000000011
DW_CFA_expression: r6 (rbp) (DW_OP_breg6 (rbp): 0)
DW_CFA_advance_loc: 10 to
000000000000001b
or to me it seems more compact to just say:
DW_CFA_advance_loc: 12 to
0000000000000011
DW_CFA_expression: r6 (rbp) (DW_OP_breg6 (rbp): 0)
DW_CFA_advance_loc: 10 to
000000000000001b
I've tried instead to deal with it through REG_FRAME_RELATED_EXPR
from the backend, but that failed miserably as explained in the PR,
dwarf2cfi.c has some rules (Rule 16 to Rule 19) that are specific to the
dynamic stack realignment using drap register that only the i386 backend
does right now, and by using REG_FRAME_RELATED_EXPR or REG_CFA* notes we
can't emulate those rules. The following patch instead does the deferring
of the hard frame pointer save rule in dwarf2cfi.c Rule 18 handling and
emits it on the (set hfp sp) assignment that must appear shortly after it
and adds assertion that it is the case.
The difference before/after the patch on the assembly is:
--- pr99334.s~ 2021-03-26 15:42:40.
881749380 +0100
+++ pr99334.s 2021-03-26 17:38:05.
729161910 +0100
@@ -11,8 +11,8 @@ _func_with_dwarf_issue_:
andq $-16, %rsp
pushq -8(%r10)
pushq %rbp
- .cfi_escape 0x10,0x6,0x2,0x76,0
movq %rsp, %rbp
+ .cfi_escape 0x10,0x6,0x2,0x76,0
pushq %r15
pushq %r14
pushq %r13
i.e. does just what we IMHO need, after pushq %rbp %rbp
still contains parent's frame value and so the save rule doesn't
need to be overridden there, ditto at the start of the next insn
before the side-effect took effect, and we override it only after
it when %rbp already has the right value.
If some other target adds dynamic stack realignment in the future and
the offset 0 case wouldn't be true there, the code can be adjusted so that
it works on all the drap architectures, I'm pretty sure the code would
need other adjustments too.
For the rule 18 and for the (set hfp sp) after it we already have asserts
for the drap cases that check whether the code looks the way i?86/x86_64
emit it currently.
2021-03-26 Jakub Jelinek <jakub@redhat.com>
PR debug/99334
* dwarf2out.h (struct dw_fde_node): Add rule18 member.
* dwarf2cfi.c (dwarf2out_frame_debug_expr): When handling (set hfp sp)
assignment with drap_reg active, queue reg save for hfp with offset 0
and flush queued reg saves. When handling a push with rule18,
defer queueing reg save for hfp and just assert the offset is 0.
(scan_trace): Assert that fde->rule18 is false.
Martin Sebor [Fri, 26 Mar 2021 22:37:34 +0000 (16:37 -0600)]
PR tree-optimization/59970 - Bogus -Wmaybe-uninitialized at low optimization levels
PR tree-optimization/59970
* gcc.dg/uninit-pr59970.c: New test.
Marek Polacek [Fri, 26 Mar 2021 15:20:03 +0000 (11:20 -0400)]
c++: ICE on invalid with NSDMI in C++98 [PR98352]
NSDMIs are a C++11 thing, and here we ICE with them on the non-C++11
path. Fortunately all we need is a small tweak to my recent r11-7835
patch.
gcc/cp/ChangeLog:
PR c++/98352
* method.c (implicitly_declare_fn): Pass &raises to
synthesized_method_walk.
gcc/testsuite/ChangeLog:
PR c++/98352
* g++.dg/cpp0x/inh-ctor37.C: Remove dg-error.
* g++.dg/cpp0x/nsdmi17.C: New test.
Jonathan Wakely [Fri, 26 Mar 2021 18:39:49 +0000 (18:39 +0000)]
libstdc++: Add PRNG fallback to std::random_device
This makes std::random_device usable on VxWorks when running on older
x86 hardware. Since the r10-728 fix for PR libstdc++/85494 the library
will use the new code unconditionally on x86, but the cpuid checks for
RDSEED and RDRAND can fail at runtime, depending on the hardware where
the code is executing. If the OS does not provide /dev/urandom then this
means the std::random_device constructor always fails. In previous
releases if /dev/urandom is unavailable then std::mt19937 was used
unconditionally.
This patch adds a fallback for the case where the runtime cpuid checks
for x86 hardware instructions fail, and no /dev/urandom is available.
When this happens a std::linear_congruential_engine object will be used,
with a seed based on hashing the engine's address and the current time.
Distinct std::random_device objects will use different seeds, unless an
object is created and destroyed and a new object created at the same
memory location within the clock tick. This is not great, but is better
than always throwing from the constructor, and better than always using
std::mt19937 with the same seed (as GCC 9 and earlier do).
libstdc++-v3/ChangeLog:
* src/c++11/random.cc (USE_LCG): Define when a pseudo-random
fallback is needed.
[USE_LCG] (bad_seed, construct_lcg_at, destroy_lcg_at, __lcg):
New helper functions and callback.
(random_device::_M_init): Add 'prng' and 'all' enumerators.
Replace switch with fallthrough with a series of 'if' statements.
[USE_LCG]: Construct an lcg_type engine and use __lcg when cpuid
checks fail.
(random_device::_M_init_pretr1) [USE_MT19937]: Accept "prng"
token.
(random_device::_M_getval): Check for callback unconditionally
and always pass _M_file pointer.
* testsuite/26_numerics/random/random_device/85494.cc: Remove
effective-target check. Use new random_device_available helper.
* testsuite/26_numerics/random/random_device/94087.cc: Likewise.
* testsuite/26_numerics/random/random_device/cons/default-cow.cc:
Remove effective-target check.
* testsuite/26_numerics/random/random_device/cons/default.cc:
Likewise.
* testsuite/26_numerics/random/random_device/cons/token.cc: Use
new random_device_available helper. Test "prng" token.
* testsuite/util/testsuite_random.h (random_device_available):
New helper function.
Nathan Sidwell [Fri, 26 Mar 2021 17:46:31 +0000 (10:46 -0700)]
c++: imported templates and alias-template changes [PR 99283]
During development of modules, I had difficulty deciding whether the
module flags of a template should live on the decl_template_result,
the template_decl, or both. I chose the latter, and require them to
be consistent. This and a few other defects show how hard that
consistency is. Hence this patch move to holding the flags on the
template-decl-result decl. That's the entity various bits of the
parser have at the appropriate time. Once needs STRIP_TEMPLATE in a
bunch of places, which this patch adds. Also a check that we never
give a TEMPLATE_DECL to the module flag accessors.
This left a problem with how I was handling template aliases. These
were in two parts -- separating the TEMPLATE_DECL from the TYPE_DECL.
That seemed somewhat funky, but development showed it necessary. Of
course, that causes problems if the TEMPLATE_DECL cannot contain 'am
imported' information. Investigating now shows that we do not need to
treat them separately. By reverting a bit of template instantiation
machinery that caused the problem, we're back on course. I think what
has happened is that between then and now, other typedef fixes have
corrected the underlying problem this separation was working around.
It allows a bunch of cleanup in the decl streamer, as we no longer
have to handle a null TEMPLATE_DECL_RESULT.
PR c++/99283
gcc/cp/
* cp-tree.h (DECL_MODULE_CHECK): Ban TEMPLATE_DECL.
(SET_TYPE_TEMPLATE_INFO): Restore Alias template setting.
* decl.c (duplicate_decls): Remove template_decl module flag
propagation.
* module.cc (merge_kind_name): Add alias tmpl spec as a thing.
(dumper::impl::nested_name): Adjust for template-decl module flag
change.
(trees_in::assert_definition): Likewise.
(trees_in::install_entity): Likewise.
(trees_out::decl_value): Likewise. Remove alias template
separation of template and type_decl.
(trees_in::decl_value): Likewise.
(trees_out::key_mergeable): Likewise,
(trees_in::key_mergeable): Likewise.
(trees_out::decl_node): Adjust for template-decl module flag
change.
(depset::hash::make_dependency): Likewise.
(get_originating_module, module_may_redeclare): Likewise.
(set_instantiating_module, set_defining_module): Likewise.
* name-lookup.c (name_lookup::search_adl): Likewise.
(do_pushdecl): Likewise.
* pt.c (build_template_decl): Likewise.
(lookup_template_class_1): Remove special alias_template handling
of DECL_TI_TEMPLATE.
(tsubst_template_decl): Likewise.
gcc/testsuite/
* g++.dg/modules/pr99283-2_a.H: New.
* g++.dg/modules/pr99283-2_b.H: New.
* g++.dg/modules/pr99283-2_c.H: New.
* g++.dg/modules/pr99283-3_a.H: New.
* g++.dg/modules/pr99283-3_b.H: New.
* g++.dg/modules/pr99283-4.H: New.
* g++.dg/modules/tpl-alias-1_a.H: Adjust scans.
* g++.dg/modules/tpl-alias-1_b.C: Adjust scans.
Dimitar Dimitrov [Fri, 26 Mar 2021 17:00:55 +0000 (19:00 +0200)]
MAINTAINERS: Add myself as pru port maintainer
ChangeLog:
* MAINTAINERS: Add myself as pru port maintainer.
Vladimir Makarov [Fri, 26 Mar 2021 17:09:24 +0000 (17:09 +0000)]
[PR99766] Consider relaxed memory associated more with memory instead of special memory.
Relaxed memory should be considered more like memory then special memory.
gcc/ChangeLog:
PR target/99766
* ira-costs.c (record_reg_classes): Put case with
CT_RELAXED_MEMORY adjacent to one with CT_MEMORY.
* ira.c (ira_setup_alts): Ditto.
* lra-constraints.c (process_alt_operands): Ditto.
* recog.c (asm_operand_ok): Ditto.
* reload.c (find_reloads): Ditto.
gcc/testsuite/ChangeLog:
PR target/99766
* g++.target/aarch64/sve/pr99766.C: New.
Richard Sandiford [Fri, 26 Mar 2021 16:08:38 +0000 (16:08 +0000)]
aarch64: Add costs for LD[34] and ST[34] postincrements
Most postincrements are cheap on Neoverse V1, but it's
generally better to avoid them on LD[34] and ST[34] instructions.
This patch adds separate address costs fields for these cases.
Other CPUs continue to use the same costs for all postincrements.
gcc/
* config/aarch64/aarch64-protos.h
(cpu_addrcost_table::post_modify_ld3_st3): New member variable.
(cpu_addrcost_table::post_modify_ld4_st4): Likewise.
* config/aarch64/aarch64.c (generic_addrcost_table): Update
accordingly, using the same costs as for post_modify.
(exynosm1_addrcost_table, xgene1_addrcost_table): Likewise.
(thunderx2t99_addrcost_table, thunderx3t110_addrcost_table):
(tsv110_addrcost_table, qdf24xx_addrcost_table): Likewise.
(a64fx_addrcost_table): Likewise.
(neoversev1_addrcost_table): New.
(neoversev1_tunings): Use neoversev1_addrcost_table.
(aarch64_address_cost): Use the new post_modify costs for CImode
and XImode.
Richard Sandiford [Fri, 26 Mar 2021 16:08:38 +0000 (16:08 +0000)]
aarch64: Take issue rate into account for vector loop costs
When SVE is enabled, GCC needs to do a three-way comparison
between scalar, Advanced SIMD and SVE code. The normal costs
tend to be latency-based, which is well-suited to SLP. However,
comparing sums of latency costs means that we effectively treat
the code as executing sequentially. This can hide the effect of
pipeline bubbles or resource contention that in practice are quite
important for loop vectorisation. This is particularly true for
loops that involve reductions.
This patch therefore tries to estimate how quickly each piece
of code could issue, using a very (very) simplistic model.
It then uses this to adjust the loop vector costs up or down as
appropriate. Part of the Advanced SIMD vs. SVE adjustment is
opt-in and is not enabled by default even for use_new_vector_costs.
Like with the previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs. The code also mostly ignores
CPUs that have no issue information, even if use_new_vector_costs
is enabled for some reason.
gcc/
* config/aarch64/aarch64.opt
(-param=aarch64-loop-vect-issue-rate-niters=): New parameter.
* doc/invoke.texi: Document it.
* config/aarch64/aarch64-protos.h (aarch64_base_vec_issue_info)
(aarch64_scalar_vec_issue_info, aarch64_simd_vec_issue_info)
(aarch64_advsimd_vec_issue_info, aarch64_sve_vec_issue_info)
(aarch64_vec_issue_info): New structures.
(cpu_vector_cost): Write comments above the variables rather
than to the side.
(cpu_vector_cost::issue_info): New member variable.
* config/aarch64/aarch64.c: Include gimple-pretty-print.h
and tree-ssa-loop-niter.h.
(generic_vector_cost, a64fx_vector_cost, qdf24xx_vector_cost)
(thunderx_vector_cost, tsv110_vector_cost, cortexa57_vector_cost)
(exynosm1_vector_cost, xgene1_vector_cost, thunderx2t99_vector_cost)
(thunderx3t110_vector_cost): Initialize issue_info to null.
(neoversev1_scalar_issue_info, neoversev1_advsimd_issue_info)
(neoversev1_sve_issue_info, neoversev1_vec_issue_info): New structures.
(neoversev1_vector_cost): Use them.
(aarch64_vec_op_count, aarch64_sve_op_count): New structures.
(aarch64_vector_costs::saw_sve_only_op): New member variable.
(aarch64_vector_costs::num_vector_iterations): Likewise.
(aarch64_vector_costs::scalar_ops): Likewise.
(aarch64_vector_costs::advsimd_ops): Likewise.
(aarch64_vector_costs::sve_ops): Likewise.
(aarch64_vector_costs::seen_loads): Likewise.
(aarch64_simd_vec_costs_for_flags): New function.
(aarch64_analyze_loop_vinfo): Initialize num_vector_iterations.
Count the number of predicate operations required by SVE WHILE
instructions.
(aarch64_comparison_type, aarch64_multiply_add_p): New functions.
(aarch64_sve_only_stmt_p, aarch64_in_loop_reduction_latency): Likewise.
(aarch64_count_ops): Likewise.
(aarch64_add_stmt_cost): Record whether see an SVE operation
that cannot currently be implementing using Advanced SIMD.
Record issue information about the scalar, Advanced SIMD
and (where relevant) SVE versions of a loop.
(aarch64_vec_op_count::dump): New function.
(aarch64_sve_op_count::dump): Likewise.
(aarch64_estimate_min_cycles_per_iter): Likewise.
(aarch64_adjust_body_cost): If issue information is available,
try to compare the issue rates of the various loop implementations
and increase or decrease the vector body cost accordingly.
Richard Sandiford [Fri, 26 Mar 2021 16:08:37 +0000 (16:08 +0000)]
aarch64: Ignore inductions when costing vector code
In practice it seems to be better not to cost a vector induction.
The scalar code generally needs the same induction but doesn't
cost it, making an apples-for-apples comparison harder. Most
inductions also have a low latency and their cost usually gets
hidden by other operations.
Like with the previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64.c (aarch64_detect_vector_stmt_subtype):
Assume a zero cost for induction phis.
Richard Sandiford [Fri, 26 Mar 2021 16:08:36 +0000 (16:08 +0000)]
aarch64: Cost comparisons embedded in COND_EXPRs
So far the costing of COND_EXPRs hasn't distinguished between
cases in which the condition is calculated separately or is
built into the COND_EXPR itself. This patch adds the cost
of any embedded comparison.
Like with the previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64.c (aarch64_embedded_comparison_type): New
function.
(aarch64_adjust_stmt_cost): Add the costs of embedded scalar and
vector comparisons.
Richard Sandiford [Fri, 26 Mar 2021 16:08:35 +0000 (16:08 +0000)]
aarch64: Detect scalar extending loads
If the scalar code does an integer load followed by an integer
extension, we've tended to cost that as two separate operations,
even though the extension is probably going to be free in practice.
This patch treats the extension as having zero cost, like we already
do for extending SVE loads.
Like with previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64.c (aarch64_detect_scalar_stmt_subtype):
New function.
(aarch64_add_stmt_cost): Call it.
Richard Sandiford [Fri, 26 Mar 2021 16:08:35 +0000 (16:08 +0000)]
aarch64: Try to detect when Advanced SIMD code would be completely unrolled
GCC usually costs the SVE and Advanced SIMD versions of a loop
and picks the one with the lowest cost. By default it will choose
SVE over Advanced SIMD in the event of tie.
This is normally the correct behaviour, not least because SVE can
handle every scalar iteration count whereas Advanced SIMD can only
handle full vectors. However, there is one important exception
that GCC failed to consider: we can completely unroll Advanced SIMD
code at compile time, but we can't do the same for SVE.
This patch therefore adds an opt-in heuristic to guess whether
the Advanced SIMD version of a loop is likely to be unrolled.
This will only be suitable for some CPUs, so it is not enabled
by default and is controlled separately from use_new_vector_costs.
Like with previous patches, this one only becomes active if a
CPU selects both of the new tuning parameters. It should therefore
have a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64-tuning-flags.def (matched_vector_throughput):
New tuning parameter.
* config/aarch64/aarch64.c (neoversev1_tunings): Use it.
(aarch64_estimated_sve_vq): New function.
(aarch64_vector_costs::analyzed_vinfo): New member variable.
(aarch64_vector_costs::is_loop): Likewise.
(aarch64_vector_costs::unrolled_advsimd_niters): Likewise.
(aarch64_vector_costs::unrolled_advsimd_stmts): Likewise.
(aarch64_record_potential_advsimd_unrolling): New function.
(aarch64_analyze_loop_vinfo, aarch64_analyze_bb_vinfo): Likewise.
(aarch64_add_stmt_cost): Call aarch64_analyze_loop_vinfo or
aarch64_analyze_bb_vinfo on the first use of a costs structure.
Detect whether we're vectorizing a loop for SVE that might be
completely unrolled if it used Advanced SIMD instead.
(aarch64_adjust_body_cost_for_latency): New function.
(aarch64_finish_cost): Call it.
Richard Sandiford [Fri, 26 Mar 2021 16:08:34 +0000 (16:08 +0000)]
aarch64: Use an aarch64-specific structure for vector costing
This patch makes the AArch64 vector code use its own vector
costs structure, rather than just using the default unsigned[3].
Unfortunately, it's not easy to make this change specific to
use_new_vector_costs, so this part is one that affects all CPUs.
The change is relatively mechanical though.
gcc/
* config/aarch64/aarch64.c (aarch64_vector_costs): New structure.
(aarch64_init_cost): New function.
(aarch64_add_stmt_cost): Use aarch64_vector_costs instead of
the default unsigned[3].
(aarch64_finish_cost, aarch64_destroy_cost_data): New functions.
(TARGET_VECTORIZE_INIT_COST): Override.
(TARGET_VECTORIZE_FINISH_COST): Likewise.
(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
Richard Sandiford [Fri, 26 Mar 2021 16:08:33 +0000 (16:08 +0000)]
aarch64: Add a CPU-specific cost table for Neoverse V1
This patch adds dedicated vector costs for Neoverse V1.
Previously we just used the Cortex-A57 costs, which isn't
ideal given that Cortex-A57 doesn't support SVE.
gcc/
* config/aarch64/aarch64.c (neoversev1_advsimd_vector_cost)
(neoversev1_sve_vector_cost): New cost structures.
(neoversev1_vector_cost): Likewise.
(neoversev1_tunings): Use them. Enable use_new_vector_costs.
Richard Sandiford [Fri, 26 Mar 2021 16:08:32 +0000 (16:08 +0000)]
aarch64: Add costs for one element of a scatter store
Currently each element in a gather load is costed as a scalar_load
and each element in a scatter store is costed as a scalar_store.
The load side seems to work pretty well in practice, since many
CPU-specific costs give loads quite a high cost relative to
arithmetic operations. However, stores usually have a cost
of just 1, which means that scatters tend to appear too cheap.
This patch adds a separate cost for one element in a scatter store.
Like with the previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64-protos.h
(sve_vec_cost::scatter_store_elt_cost): New member variable.
* config/aarch64/aarch64.c (generic_sve_vector_cost): Update
accordingly, taking the cost from the cost of a scalar_store.
(a64fx_sve_vector_cost): Likewise.
(aarch64_detect_vector_stmt_subtype): Detect scatter stores.
Richard Sandiford [Fri, 26 Mar 2021 16:08:31 +0000 (16:08 +0000)]
aarch64: Add costs for storing one element of a vector
Storing one element of a vector is costed as a vec_to_scalar
followed by a scalar_store. However, vec_to_scalar is also
used for reductions and for vector-to-GPR moves, which makes
it difficult to pick one cost for them all.
This patch therefore adds a cost for extracting one element
of a vector in preparation for storing it out. The store
itself is still costed separately.
Like with the previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64-protos.h
(simd_vec_cost::store_elt_extra_cost): New member variable.
* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
accordingly, using the vec_to_scalar cost for the new field.
(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
(thunderx3t110_advsimd_vector_cost): Likewise.
(aarch64_detect_vector_stmt_subtype): Detect single-element stores.
Richard Sandiford [Fri, 26 Mar 2021 16:08:31 +0000 (16:08 +0000)]
aarch64: Add costs for LD[234]/ST[234] permutes
At the moment, we cost LD[234] and ST[234] as N vector loads
or stores, which effectively treats the implied permute as free.
This patch adds additional costs for the permutes, which apply on
top of the costs for the loads and stores.
Like with the previous patches, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64-protos.h (simd_vec_cost::ld2_st2_permute_cost)
(simd_vec_cost::ld3_st3_permute_cost): New member variables.
(simd_vec_cost::ld4_st4_permute_cost): Likewise.
* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
accordingly, using zero for the new costs.
(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
(thunderx3t110_advsimd_vector_cost): Likewise.
(aarch64_ld234_st234_vectors): New function.
(aarch64_adjust_stmt_cost): Likewise.
(aarch64_add_stmt_cost): Call aarch64_adjust_stmt_cost if using
the new vector costs.
Richard Sandiford [Fri, 26 Mar 2021 16:08:30 +0000 (16:08 +0000)]
aarch64: Add vector costs for SVE CLAST[AB] and FADDA
Following on from the previous reduction costs patch, this one
adds costs for the SVE CLAST[AB] and FADDA instructions.
These instructions occur within the loop body, whereas the
reductions handled by the previous patch occur outside.
Like with the previous patch, this one only becomes active if
a CPU selects use_new_vector_costs. It should therefore have
a very low impact on other CPUs.
gcc/
* config/aarch64/aarch64-protos.h (sve_vec_cost): Turn into a
derived class of simd_vec_cost. Add information about CLAST[AB]
and FADDA instructions.
* config/aarch64/aarch64.c (generic_sve_vector_cost): Update
accordingly, using the vec_to_scalar costs for the new fields.
(a64fx_sve_vector_cost): Likewise.
(aarch64_reduc_type): New function.
(aarch64_sve_in_loop_reduction_latency): Likewise.
(aarch64_detect_vector_stmt_subtype): Take a vinfo parameter.
Use aarch64_sve_in_loop_reduction_latency to handle SVE reductions
that occur in the loop body.
(aarch64_add_stmt_cost): Update call accordingly.
Richard Sandiford [Fri, 26 Mar 2021 16:08:29 +0000 (16:08 +0000)]
aarch64: Add reduction costs to simd_vec_costs
This patch is part of a series that makes opt-in tweaks to the
AArch64 vector cost model.
At the moment, all reductions are costed as vec_to_scalar, which
also includes things like extracting a single element from a vector.
This is a bit too coarse in practice, since the cost of a reduction
depends very much on the type of value that it's processing.
This patch therefore adds separate costs for each case. To start with,
all the new costs are copied from the associated vec_to_scalar ones.
Due the extreme lateness of this patch in the GCC 11 cycle, I've added
a new tuning flag (use_new_vector_costs) that selects the new behaviour.
This should help to ensure that the risk of the new code is only borne
by the CPUs that need it. Generic tuning is not affected.
gcc/
* config/aarch64/aarch64-tuning-flags.def (use_new_vector_costs):
New tuning flag.
* config/aarch64/aarch64-protos.h (simd_vec_cost): Put comments
above the fields rather than to the right.
(simd_vec_cost::reduc_i8_cost): New member variable.
(simd_vec_cost::reduc_i16_cost): Likewise.
(simd_vec_cost::reduc_i32_cost): Likewise.
(simd_vec_cost::reduc_i64_cost): Likewise.
(simd_vec_cost::reduc_f16_cost): Likewise.
(simd_vec_cost::reduc_f32_cost): Likewise.
(simd_vec_cost::reduc_f64_cost): Likewise.
* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
accordingly, using the vec_to_scalar_cost for the new fields.
(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
(thunderx3t110_advsimd_vector_cost): Likewise.
(aarch64_use_new_vector_costs_p): New function.
(aarch64_simd_vec_costs): New function, split out from...
(aarch64_builtin_vectorization_cost): ...here.
(aarch64_is_reduction): New function.
(aarch64_detect_vector_stmt_subtype): Likewise.
(aarch64_add_stmt_cost): Call aarch64_detect_vector_stmt_subtype if
using the new vector costs.
Iain Buclaw [Fri, 26 Mar 2021 14:46:24 +0000 (15:46 +0100)]
libphobos: Build all modules with -fversion=Shared when configured with --enable-shared
The libgdruntime_convenience library was built with `-fversion=Shared',
but the libphobos part wasn't when creating the static library.
As there are no issues compiling in Shared code into the static library,
to avoid mismatches the flag is now always present when --enable-shared
is turned on. Libtool's compiler PIC D flag is now the combination of
compiler PIC and D Shared flags, and AM_DFLAGS passes `-prefer-pic' to
libtool unless --enable-shared is turned off.
libphobos/ChangeLog:
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.ac: Substitute enable_shared, enable_static, and
phobos_lt_pic_flag.
* libdruntime/Makefile.am (AM_DFLAGS): Replace
phobos_compiler_pic_flag with phobos_lt_pic_flags, and
phobos_compiler_shared_flag.
* libdruntime/Makefile.in: Regenerate.
* src/Makefile.am (AM_DFLAGS): Replace phobos_compiler_pic_flag
with phobos_lt_pic_flag, and phobos_compiler_shared_flag.
* src/Makefile.in: Regenerate.
* testsuite/Makefile.in: Regenerate.
* testsuite/libphobos.druntime_shared/druntime_shared.exp: Remove
-fversion=Shared and -fno-moduleinfo from default extra test flags.
* testsuite/libphobos.phobos_shared/phobos_shared.exp: Likewise.
* testsuite/testsuite_flags.in: Add phobos_compiler_shared_flag to
--gdcflags.
Iain Buclaw [Sat, 13 Mar 2021 16:05:52 +0000 (17:05 +0100)]
Fix ICE: in function_and_variable_visibility, at ipa-visibility.c:795 [PR99466]
In get_emutls_init_templ_addr, only thread-local declarations that were
DECL_ONE_ONLY would have a public initializer symbol, ignoring variables
that were declared with __attribute__((weak)).
gcc/ChangeLog:
PR ipa/99466
* tree-emutls.c (get_emutls_init_templ_addr): Mark initializer of weak
TLS declarations as public.
gcc/testsuite/ChangeLog:
PR ipa/99466
* gcc.dg/tls/pr99466-1.c: New test.
* gcc.dg/tls/pr99466-2.c: New test.
Iain Buclaw [Fri, 26 Mar 2021 12:12:59 +0000 (13:12 +0100)]
d: Define IN_TARGET_CODE in all machine-specific D language files.
This is to be consistent with the rest of the back-end.
gcc/ChangeLog:
* config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define.
* config/arm/arm-d.c (IN_TARGET_CODE): Likewise.
* config/i386/i386-d.c (IN_TARGET_CODE): Likewise.
* config/mips/mips-d.c (IN_TARGET_CODE): Likewise.
* config/pa/pa-d.c (IN_TARGET_CODE): Likewise.
* config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise.
* config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise.
* config/s390/s390-d.c (IN_TARGET_CODE): Likewise.
* config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise.
Iain Buclaw [Sun, 22 Mar 2020 00:18:42 +0000 (01:18 +0100)]
d: Add windows support for D compiler [PR91595]
gcc/ChangeLog:
PR d/91595
* config.gcc (*-*-cygwin*): Add winnt-d.o
(*-*-mingw*): Likewise.
* config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): New macro.
* config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Likewise.
* config/i386/t-cygming: Add winnt-d.o.
* config/i386/winnt-d.c: New file.
Iain Buclaw [Sun, 21 Mar 2021 16:51:39 +0000 (17:51 +0100)]
[freebsd] d: Fix build failures on sparc64-*-freebsd*
All target platforms that could run on SPARC should include this header
in order to avoid errors from memmodel being used in sparc-protos.h.
gcc/ChangeLog:
* config/freebsd-d.c: Include memmodel.h.
Iain Buclaw [Sun, 21 Mar 2021 10:00:29 +0000 (11:00 +0100)]
d: Add openbsd support for D compiler [PR99691]
gcc/ChangeLog:
PR d/99691
* config.gcc (*-*-openbsd*): Add openbsd-d.o.
* config/t-openbsd: Add openbsd-d.o.
* config/openbsd-d.c: New file.
Jakub Jelinek [Fri, 26 Mar 2021 08:35:26 +0000 (09:35 +0100)]
c++: Fix ICE with nsdmi [PR99705]
When adding P0784R7 constexpr new support, we still didn't have
P1331R2 implemented and so I had to change also build_vec_delete_1
- instead of having uninitialized tbase temporary later initialized
by MODIFY_EXPR I've set the DECL_INITIAL for it - because otherwise
it would be rejected during constexpr evaluation which didn't like
uninitialized vars. Unfortunately, that change broke the following
testcase.
The problem is that these temporaries (not just tbase but tbase was
the only one with an initializer) are created during NSDMI parsing
and current_function_decl is NULL at that point. Later when we
clone body of constructors, auto_var_in_fn_p is false for those
(as they have NULL DECL_CONTEXT) and so they aren't duplicated,
and what is worse, the DECL_INITIAL isn't duplicated either nor processed,
and during expansion we ICE because the code from DECL_INITIAL of that
var refers to the abstract constructor's PARM_DECL (this) rather than
the actual constructor's one.
So, either we can just revert those build_vec_delete_1 changes (as done
in the second patch - in attachment), or, as the first patch does, we can
copy the temporaries during bot_manip like we copy the temporaries of
TARGET_EXPRs. To me that looks like a better fix because e.g. if
break_out_of_target_exprs is called for the same NSDMI multiple times,
sharing the temporaries looks just wrong to me. If the temporaries
are declared as BIND_EXPR_VARS of some BIND_EXPR (which is the case
of the tbase variable built by build_vec_delete_1 and is the only way
how the DECL_INITIAL can be walked by *walk_tree*), then we need to
copy it also in the BIND_EXPR BIND_EXPR_VARS chain, other temporaries
(those that don't need DECL_INITIAL) often have just DECL_EXPR and no
corresponding BIND_EXPR.
Note, ({ }) are rejected in nsdmis, so all we run into are temporaries
the FE creates artificially.
2021-03-26 Jakub Jelinek <jakub@redhat.com>
PR c++/99705
* tree.c (bot_manip): Remap artificial automatic temporaries mentioned
in DECL_EXPR or in BIND_EXPR_VARS.
* g++.dg/cpp0x/new5.C: New test.
Tobias Burnus [Fri, 26 Mar 2021 07:39:24 +0000 (08:39 +0100)]
Fortran: Fix intrinsic null() handling [PR99651]
gcc/fortran/ChangeLog:
PR fortran/99651
* intrinsic.c (gfc_intrinsic_func_interface): Set
attr.proc = PROC_INTRINSIC if FL_PROCEDURE.
gcc/testsuite/ChangeLog:
PR fortran/99651
* gfortran.dg/null_11.f90: New test.
GCC Administrator [Fri, 26 Mar 2021 00:16:25 +0000 (00:16 +0000)]
Daily bump.
Martin Sebor [Thu, 25 Mar 2021 23:23:06 +0000 (17:23 -0600)]
PR tree-optimization/55060 - False un-initialized variable warnings
gcc/testsuite/ChangeLog:
PR tree-optimization/55060
* gcc.dg/uninit-pr55060.c: New.
Martin Sebor [Thu, 25 Mar 2021 22:08:00 +0000 (16:08 -0600)]
PR tree-optimization/48483 - Construct from yourself w/o warning
gcc/testsuite/ChangeLog:
PR tree-optimization/48483
* g++.dg/warn/uninit-pr48483.C: New test.
Martin Sebor [Thu, 25 Mar 2021 21:31:46 +0000 (15:31 -0600)]
New test for PR tree-optimization/44547 - -Wuninitialized reports false warning in nested switch statements.
gcc/testsuite/ChangeLog:
* gcc.dg/uninit-pr44547.c: New.
François Dumont [Fri, 5 Mar 2021 17:50:22 +0000 (18:50 +0100)]
libstdc++: Fix and complete __gnu_debug::basic_string implementation
Fix and complete __gnu_debug::basic_string so that it can be used as a transparent
replacement of std::basic_string.
libstdc++-v3/ChangeLog:
* include/debug/string
(basic_string(const basic_string&, const _Alloc&)): Define even if !_GLIBCXX_USE_CXX11_ABI.
(basic_string(basic_string&&, const _Alloc&)): Likewise and add noexcept qualification.
(basic_string<>::erase): Adapt to take __const_iterator.
(basic_string(const _CharT*, const _Allocator&)): Remove assign call.
(basic_string<>::insert(const_iterator, _InputIte, _InputIte)): Try to
remove iterator debug layer even if !_GLIBCXX_USE_CXX11_ABI.
[_GLIBCXX_USE_CHAR8_T] (__gnu_debug::u8string): New.
(__gnu_debug::u16string, __gnu_debug::u32string): New.
(std::hash<__gnu_debug::basic_string<>>): New partial specialization.
(std::__is_fast_hash<__gnu_debug::basic_string<>>): Likewise.
* testsuite/util/exception/safety.h
(erase_base<__gnu_debug::basic_string<>>): New partial specialization.
(insert_base<__gnu_debug::basic_string<>>): Likewise.
* testsuite/util/testsuite_container_traits.h (traits<__gnu_debug::basic_string<>>):
New partial specialization.
* testsuite/21_strings/basic_string/hash/debug.cc: New test.
* testsuite/21_strings/basic_string/requirements/citerators.cc:
Add test on __gnu_debug::string.
* testsuite/21_strings/basic_string/requirements/dr438/constructor.cc: Likewise.
* testsuite/21_strings/basic_string/requirements/exception/basic.cc: Likewise.
* testsuite/21_strings/basic_string/requirements/exception/generation_prohibited.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/exception/propagation_consistent.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/explicit_instantiation/char/1.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/explicit_instantiation/char16_t/1.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/explicit_instantiation/char32_t/1.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/explicit_instantiation/char8_t/1.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/explicit_instantiation/wchar_t/1.cc:
Likewise.
* testsuite/21_strings/basic_string/requirements/typedefs.cc: Likewise.
Joseph Myers [Thu, 25 Mar 2021 20:43:27 +0000 (20:43 +0000)]
Update gcc fr.po.
* fr.po: Update.
Jakub Jelinek [Thu, 25 Mar 2021 20:35:11 +0000 (21:35 +0100)]
c++: Fix source_location inconsistency between calls from templates and non-templates [PR99672]
The srcloc19.C testcase shows inconsistency in
std::source_location::current() locations between calls from
templates and non-templates. The location used by __builtin_source_location
comes in both cases from input_location which is set on it by bot_manip
when handling the default argument, called during finish_call_expr.
The problem is that in templates that input_location comes from the
CALL_EXPR we built earlier and that has the combined locus with
range between first character of the function name and closing paren
with caret on the opening paren, so something printed as caret as:
foobar ();
~~~~~~^~
But outside of templates, finish_call_expr is called when input_location
is just the closing paren token, i.e.
foobar ();
^
and only after that returns we create the combined location and set
the CALL_EXPR location to that. So, it means std::source_location::current()
reports in templates the column of opening (, while outside of templates
closing ).
The following patch makes it consistent by creating the combined location
already before calling finish_call_expr and temporarily overriding
input_location to that.
2021-03-25 Jakub Jelinek <jakub@redhat.com>
PR c++/99672
* parser.c (cp_parser_postfix_expression): For calls, create
combined_loc and temporarily set input_location to it before
calling finish_call_expr.
* g++.dg/concepts/diagnostic2.C: Adjust expected caret line.
* g++.dg/cpp1y/builtin_location.C (f4, n6): Move #line directives
to match locus changes.
* g++.dg/cpp2a/srcloc1.C: Adjust expected column numbers.
* g++.dg/cpp2a/srcloc2.C: Likewise.
* g++.dg/cpp2a/srcloc15.C: Likewise.
* g++.dg/cpp2a/srcloc16.C: Likewise.
* g++.dg/cpp2a/srcloc19.C: New test.
* g++.dg/modules/adhoc-1_b.C: Adjust expected column numbers
and caret line.
* g++.dg/modules/macloc-1_c.C: Adjust expected column numbers.
* g++.dg/modules/macloc-1_d.C: Likewise.
* g++.dg/plugin/diagnostic-test-expressions-1.C: Adjust expected
caret line.
* testsuite/18_support/source_location/consteval.cc (main): Adjust
expected column numbers.
* testsuite/18_support/source_location/1.cc (main): Likewise.
Marek Polacek [Fri, 5 Mar 2021 20:46:50 +0000 (15:46 -0500)]
c++: ICE on invalid with inheriting constructors [PR94751]
This is an ICE on invalid where we crash because since r269032 we
keep error_mark_node around instead of using noexcept_false_spec
when things go wrong; see the walk_field_subobs hunk.
We crash in deduce_inheriting_ctor which calls synthesized_method_walk
to deduce the exception-specification, but fails to do so in this case,
because the testcase is invalid so get_nsdmi returns error_mark_node for
the member 'c', and per r269032 the error_mark_node propagates back to
deduce_inheriting_ctor which subsequently calls build_exception_variant
whereon we crash. I think we should return early if the deduction fails
and I decided to call mark_used to get an error right away instead of
hoping that it would get called later. My worry is that we could forget
that there was an error and think that we just deduced noexcept(false).
And then I noticed that the test still crashes in C++98. Here again we
failed to deduce the exception-specification in implicitly_declare_fn,
but nothing reported an error between synthesized_method_walk and the
assert. Well, not much we can do except calling synthesized_method_walk
again, this time in the verbose mode and making sure that we did get an
error.
gcc/cp/ChangeLog:
PR c++/94751
* call.c (build_over_call): Maybe call mark_used in case
deduce_inheriting_ctor fails and return error_mark_node.
* cp-tree.h (deduce_inheriting_ctor): Adjust declaration.
* method.c (deduce_inheriting_ctor): Return bool if the deduction
fails.
(implicitly_declare_fn): If raises is error_mark_node, call
synthesized_method_walk with diag being true.
gcc/testsuite/ChangeLog:
PR c++/94751
* g++.dg/cpp0x/inh-ctor37.C: New test.
Jakub Jelinek [Thu, 25 Mar 2021 20:06:09 +0000 (21:06 +0100)]
c++: Diagnose bare parameter packs in bitfield widths [PR99745]
The following invalid tests ICE because we don't diagnose (and drop) bare
parameter packs in bitfield widths.
2021-03-25 Jakub Jelinek <jakub@redhat.com>
PR c++/99745
* decl2.c (grokbitfield): Diagnose bitfields containing bare parameter
packs and don't set DECL_BIT_FIELD_REPRESENTATIVE in that case.
* g++.dg/cpp0x/variadic181.C: New test.
Marek Polacek [Fri, 5 Mar 2021 01:20:40 +0000 (20:20 -0500)]
c++: -Wconversion vs value-dependent expressions [PR99331]
This PR complains that we issue a -Wconversion warning in
template <int N> struct X {};
template <class T> X<sizeof(T)> foo();
saying "conversion from 'long unsigned int' to 'int' may change value".
While it's not technically wrong, I suspect -Wconversion warnings aren't
all that useful for value-dependent expressions. So this patch disables
them. This is a regression that started with r241425:
@@ -7278,7 +7306,7 @@ convert_template_argument (tree parm,
val = error_mark_node;
}
}
- else if (!dependent_template_arg_p (orig_arg)
+ else if (!type_dependent_expression_p (orig_arg)
&& !uses_template_parms (t))
/* We used to call digest_init here. However, digest_init
will report errors, which we don't want when complain
Here orig_arg is SIZEOF_EXPR<T>; dependent_template_arg_p (orig_arg) was
true, but type_dependent_expression_p (orig_arg) is false so we warn in
convert_nontype_argument.
gcc/cp/ChangeLog:
PR c++/99331
* call.c (build_converted_constant_expr_internal): Don't emit
-Wconversion warnings.
gcc/testsuite/ChangeLog:
PR c++/99331
* g++.dg/warn/Wconversion5.C: New test.
Jonathan Wakely [Thu, 25 Mar 2021 18:24:37 +0000 (18:24 +0000)]
libstdc++: Declare malloc for freestanding
For a target with none of aligned_alloc, memalign etc. we defined our
own aligned_alloc using malloc, so we need a declaration of malloc. As
in libsupc++/new_op.cc we need to declare it ourselves for freestanding
environments.
libstdc++-v3/ChangeLog:
* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Declare malloc.
Jonathan Wakely [Thu, 25 Mar 2021 13:51:08 +0000 (13:51 +0000)]
libstdc++: Allow seeding random engines in testsuite
The testsuite utilities that use random numbers use a
default-constructed mersenne_twister_engine, meaning the values are
reproducable. This adds support for seeding them, controlledby an
environment variable. Defining GLIBCXX_SEED_TEST_RNG=val in the
environment will cause the engines to be seeded with atoi(val) if that
is non-zero, or with a value read from std::random_device otherwise.
Running with different seeds revealed some bugs in the tests, where a
randomly selected iterator was past-the-end (which can't be erased), or
where the randomly populated container was empty, and then we tried to
remove elements from it unconditionally.
libstdc++-v3/ChangeLog:
* testsuite/util/exception/safety.h (setup_base::generate):
Support seeding random engine.
(erase_point, erase_range): Adjust range of random numbers to
ensure dereferenceable iterators are used where required.
(generation_prohibited::run): Do not try to erase from empty
containers.
* testsuite/util/testsuite_containergen.h (test_containers):
Support seeding random engine.
Stam Markianos-Wright [Thu, 25 Mar 2021 15:29:41 +0000 (15:29 +0000)]
tree-optimization/96974 - avoid ICE by replacing assert with standard failure
Minor patch to add a graceful exit in the rare case where an invalid
combination of TYPE_VECTOR_SUBPARTS for nunits_vectype and
*stmt_vectype_out is reached in vect_get_vector_types_for_stmt.
This resolves the ICE seen in PR tree-optimization/96974, however the issue
of correctly handling this rare vectorization combination is left for a
later patch.
Bootstrapped and reg-tested on aarch64-linux-gnu.
2021-03-25 Stam Markianos-Wright <stam.markianos-wright@arm.com>
gcc/ChangeLog:
PR tree-optimization/96974
* tree-vect-stmts.c (vect_get_vector_types_for_stmt): Replace assert
with graceful exit.
gcc/testsuite/ChangeLog:
PR tree-optimization/96974
* g++.target/aarch64/sve/pr96974.C: New test.
H.J. Lu [Thu, 25 Mar 2021 13:57:37 +0000 (06:57 -0700)]
Revert "x86: Skip ISA check for always_inline in system headers"
This reverts commit
72982851d70dfbc547d83ed2bb45356b9ebe3ff0.
Thomas Schwinge [Thu, 25 Jun 2020 09:59:42 +0000 (11:59 +0200)]
libgomp HSA/GCN plugins: don't prepend the 'HSA_RUNTIME_LIB' path to 'libhsa-runtime64.so'
For unknown reasons, this had gotten added for the libgomp HSA plugin in commit
b8d89b03db5f212919e4571671ebb4f5f8b1e19d (r242749) "Remove build dependence on
HSA run-time", and later propagated into the GCN plugin.
libgomp/
* plugin/plugin-gcn.c (init_environment_variables): Don't prepend
the 'HSA_RUNTIME_LIB' path to 'libhsa-runtime64.so'.
* plugin/configfrag.ac (HSA_RUNTIME_LIB): Clean up.
* config.h.in: Regenerate.
* configure: Likewise.
Kewen Lin [Thu, 25 Mar 2021 12:53:06 +0000 (07:53 -0500)]
vect: Init inside_cost in vect_model_reduction_cost
This patch is to initialize the inside_cost as zero, can avoid
to use its uninitialized value when some path doesn't assign it.
gcc/ChangeLog:
* tree-vect-loop.c (vect_model_reduction_cost): Init inside_cost.
Jakub Jelinek [Thu, 25 Mar 2021 10:33:35 +0000 (11:33 +0100)]
c-family: Fix up -Wduplicated-branches for union members [PR99565]
Honza has fairly recently changed operand_equal_p to compare
DECL_FIELD_OFFSET for COMPONENT_REFs when comparing addresses.
As the first testcase in this patch shows, while that is very nice
for optimizations, for the -Wduplicated-branches warning it causes
regressions. Pedantically a union in both C and C++ has only one
active member at a time, so using some other union member even if it has the
same type is UB, so I think the warning shouldn't warn when it sees access
to different fields that happen to have the same offset and should consider
them different.
In my first attempt to fix this I've keyed the old behavior on
OEP_LEXICOGRAPHIC, but unfortunately that has various problems, the warning
has a quick non-lexicographic compare in build_conditional_expr* and another
lexicographic more expensive one later during genericization and turning the
first one into lexicographic would mean wasting compile time on large
conditionals.
So, this patch instead introduces a new OEP_ flag and makes sure to pass it
to operand_equal_p in all -Wduplicated-branches cases.
The cvt.c changes are because on the other testcase we were warning with
UNKNOWN_LOCATION, so the user wouldn't really know where the questionable
code is.
2021-03-25 Jakub Jelinek <jakub@redhat.com>
PR c++/99565
* tree-core.h (enum operand_equal_flag): Add OEP_ADDRESS_OF_SAME_FIELD.
* fold-const.c (operand_compare::operand_equal_p): Don't compare
field offsets if OEP_ADDRESS_OF_SAME_FIELD.
* c-warn.c (do_warn_duplicated_branches): Pass also
OEP_ADDRESS_OF_SAME_FIELD to operand_equal_p.
* c-typeck.c (build_conditional_expr): Pass OEP_ADDRESS_OF_SAME_FIELD
to operand_equal_p.
* call.c (build_conditional_expr_1): Pass OEP_ADDRESS_OF_SAME_FIELD
to operand_equal_p.
* cvt.c (convert_to_void): Preserve location_t on COND_EXPR or
or COMPOUND_EXPR.
* g++.dg/warn/Wduplicated-branches6.C: New test.
* g++.dg/warn/Wduplicated-branches7.C: New test.
H.J. Lu [Wed, 24 Mar 2021 03:04:58 +0000 (20:04 -0700)]
x86: Skip ISA check for always_inline in system headers
For always_inline in system headers, we don't know if caller's ISAs are
compatible with callee's ISAs until much later. Skip ISA check for
always_inline in system headers if caller has target attribute.
gcc/
PR target/98209
PR target/99744
* config/i386/i386.c (ix86_can_inline_p): Don't check ISA for
always_inline in system headers.
gcc/testsuite/
PR target/98209
PR target/99744
* gcc.target/i386/pr98209.c: New test.
* gcc.target/i386/pr99744-1.c: Likewise.
* gcc.target/i386/pr99744-2.c: Likewise.
Thomas Schwinge [Thu, 11 Mar 2021 16:01:22 +0000 (17:01 +0100)]
Avoid OpenMP/nvptx execution-time hangs for simple nested OpenMP 'target'/'parallel'/'task' constructs [PR99555]
... awaiting proper resolution, of course.
libgomp/
PR target/99555
* testsuite/lib/on_device_arch.c: New file.
* testsuite/libgomp.c/pr99555-1.c: Likewise.
* testsuite/libgomp.c-c++-common/task-detach-6.c: Until resolved,
skip for nvptx offloading, with error status.
* testsuite/libgomp.fortran/task-detach-6.f90: Likewise.
Thomas Schwinge [Thu, 11 Mar 2021 09:52:59 +0000 (10:52 +0100)]
'libgomp.oacc-fortran/derivedtypes-arrays-1.f90' OpenACC 'serial' construct diagnostic for nvptx offloading
Fixup for recent commit
d28f3da11d8c0aed9b746689d723022a9b5ec04c "openacc: Fix
lowering for derived-type mappings through array elements". With nvptx
offloading we see the usual:
[...]/libgomp.oacc-fortran/derivedtypes-arrays-1.f90: In function 'MAIN__._omp_fn.0':
[...]/libgomp.oacc-fortran/derivedtypes-arrays-1.f90:90:40: warning: using vector_length (32), ignoring 1
libgomp/
* testsuite/libgomp.oacc-fortran/derivedtypes-arrays-1.f90:
OpenACC 'serial' construct diagnostic for nvptx offloading.
Richard Biener [Wed, 24 Mar 2021 11:55:16 +0000 (12:55 +0100)]
tree-optimization/99746 - avoid confusing hybrid code
This avoids confusing the hybrid vectorization code with SLP
patterns by not marking SLP pattern covered stmts as patterns
(they are marked as SLP patterns already). This means that loop
vectorization will vectorize the scalar stmt rather than the SLP
pattern stmt (which it can't anyway).
2021-03-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/99746
* tree-vect-slp-patterns.c (complex_pattern::build): Do not mark
the scalar stmt as patterned. Instead set up required things
manually.
* gfortran.dg/vect/pr99746.f90: New testcase.
Xionghu Luo [Thu, 25 Mar 2021 00:46:12 +0000 (19:46 -0500)]
rs6000: Correct Power8 cost of l2 cache size [PR97329]
l2 cache size for Power8 is 512kB, it was copied from Power7 before
public. Tested no performance change for SPEC2017.
gcc/ChangeLog:
2021-03-24 Xionghu Luo <luoxhu@linux.ibm.com>
* config/rs6000/rs6000.c (power8_costs): Change l2 cache
from 256 to 512.
David Malcolm [Thu, 25 Mar 2021 00:47:57 +0000 (20:47 -0400)]
analyzer; reset sm-state for SSA names at def-stmts [PR93695,PR99044,PR99716]
Various false positives from -fanalyzer involve SSA names in loops,
where sm-state associated with an SSA name from one iteration is
erroneously reused in a subsequent iteration.
For example, PR analyzer/99716 describes a false
"double 'fclose' of FILE 'fp'"
on:
for (i = 0; i < 2; ++i) {
FILE *fp = fopen ("/tmp/test", "w");
fprintf (fp, "hello");
fclose (fp);
}
where the gimple of the loop body is:
fp_7 = fopen ("/tmp/test", "w");
__builtin_fwrite ("hello", 1, 5, fp_7);
fclose (fp_7);
i_10 = i_1 + 1;
where fp_7 transitions to "closed" at the fclose, but is not
reset at the subsequent fopen, leading to the false positive
when the fclose is re-reached.
The fix is to reset sm-state for svalues that involve an SSA name
at the SSA name's def-stmt, since the def-stmt effectively changes
the meaning of those related svalues.
gcc/analyzer/ChangeLog:
PR analyzer/93695
PR analyzer/99044
PR analyzer/99716
* engine.cc (exploded_node::on_stmt): Clear sm-state involving
an SSA name at the def-stmt of that SSA name.
* program-state.cc (sm_state_map::purge_state_involving): New.
* program-state.h (sm_state_map::purge_state_involving): New decl.
* region-model.cc (selftest::test_involves_p): New.
(selftest::analyzer_region_model_cc_tests): Call it.
* svalue.cc (class involvement_visitor): New class
(svalue::involves_p): New.
* svalue.h (svalue::involves_p): New decl.
gcc/testsuite/ChangeLog:
PR analyzer/93695
PR analyzer/99044
PR analyzer/99716
* gcc.dg/analyzer/attr-malloc-CVE-2019-19078-usb-leak.c: Remove
xfail.
* gcc.dg/analyzer/pr93695-1.c: New test.
* gcc.dg/analyzer/pr99044-1.c: New test.
* gcc.dg/analyzer/pr99044-2.c: New test.
* gcc.dg/analyzer/pr99716-1.c: New test.
* gcc.dg/analyzer/pr99716-2.c: New test.
* gcc.dg/analyzer/pr99716-3.c: New test.
GCC Administrator [Thu, 25 Mar 2021 00:16:48 +0000 (00:16 +0000)]
Daily bump.
Martin Liska [Wed, 24 Mar 2021 14:58:03 +0000 (15:58 +0100)]
i386: fix -march=amd crash
It started with g:
3e2ae3ee285a57455d5a23bd352a68c289130186 where
new entry was added to processor_alias_table after generic node:
+ {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM19H), P_NONE},
and then the following is violated:
/* NB: processor_alias_table stops at the "generic" entry. */
gcc/ChangeLog:
PR target/99753
* common/config/i386/i386-common.c (ARRAY_SIZE): Fix off-by-one
error.
* config/i386/i386-options.c (ix86_option_override_internal):
Add run-time assert.
gcc/testsuite/ChangeLog:
PR target/99753
* gcc.target/i386/pr99753.c: New test.
Martin Jambor [Wed, 24 Mar 2021 19:27:27 +0000 (20:27 +0100)]
ipa: Check that scalar types that IPA-CP comes up with are sane (PR99122)
This patch fixes the last bit of PR 99122 where various bits of IPA
infrastructure are presented with a program with type mismatches that
make it have undefined behavior, and when inlining or performing
IPA-CP, and encountering such mismatch, we basically try to
VIEW_CONVERT_EXPR whatever the caller has into whatever the callee has
or simply use an empty constructor if that cannot be done. This
however does not work when the callee has VLA parameters because we
ICE in the process.
Richi has already disabled inlining for such cases, this patch avoids
the issue in IPA-CP. It adds checks that whatever constant the
propagation arrived at is actually compatible or fold_convertible to
the callees formal parameer type. Unlike in the past, we now have
types of all parameters of functions that we have analyzed, even with
LTO, and so can do it.
This should prevent only bogus propagations. I have looked at the
effect of the patch on WPA of Firefox and did not have any.
I have bootstrapped and LTO bootstrapped and tested the patch on
x86_64-linux. OK for trunk? And perhaps later for GCC 10 too?
Thanks
gcc/ChangeLog:
2021-02-26 Martin Jambor <mjambor@suse.cz>
PR ipa/99122
* ipa-cp.c (initialize_node_lattices): Mark as bottom all
parameters with unknown type.
(ipacp_value_safe_for_type): New function.
(propagate_vals_across_arith_jfunc): Verify that the constant type
can be used for a type of the formal parameter.
(propagate_vals_across_ancestor): Likewise.
(propagate_scalar_across_jump_function): Likewise. Pass the type
also to propagate_vals_across_ancestor.
gcc/testsuite/ChangeLog:
2021-02-26 Martin Jambor <mjambor@suse.cz>
PR ipa/99122
* gcc.dg/pr99122-3.c: Remove -fno-ipa-cp from options.
Christophe Lyon [Wed, 24 Mar 2021 08:51:41 +0000 (08:51 +0000)]
arm: Fix MVE constraints for movmisalign [PR target/99727]
MVE has different constraints than Neon for load/store: we should use
the Ux constraint instead of Um.
2021-03-24 Christophe Lyon <christophe.lyon@linaro.org>
PR target/99727
gcc/
* config/arm/mve.md (movmisalign<mode>_mve_store): Use Ux
constraint.
(movmisalign<mode>_mve_load): Likewise.
gcc/testsuite/
* gcc.target/arm/pr99727.c: New test.
Matthias Klose [Wed, 24 Mar 2021 12:28:21 +0000 (12:28 +0000)]
Fix installation of the jit header files
gcc/jit/
2021-03-24 Matthias Klose <doko@ubuntu.com>
* Make-lang.in (jit.sphinx.html, jit.sphinx.pdf): Use $(mkinstalldirs),
(jit.install-headers): Depend on installdirs.
Jakub Jelinek [Wed, 24 Mar 2021 10:22:35 +0000 (11:22 +0100)]
arm: Fix some more vec-common.md patterns for iwmmxt [PR99724]
The following patch fixes similar issues as in PR98849;
in older gcc versions, the expanders were present in neon.md guarded
with TARGET_NEON, but they got moved to vec-common.md and guarded with
ARM_HAVE_<MODE>_ARITH so that they handle both MVE and Neon.
The macros are enabled for some modes even for iwmmxt which has some
vector support for those modes, but only limited. In particular,
neither the one_cmpl, nor neg, nor movmisalign patterns are present.
For some reason I've failed to construct something that ICEs with
movmisalign, so that is not covered by the testsuite, but both
one_cmpl and neg ICE.
2021-03-24 Jakub Jelinek <jakub@redhat.com>
PR target/99724
* config/arm/vec-common.md (one_cmpl<mode>2, neg<mode>2,
movmisalign<mode>): Disable expanders for TARGET_REALLY_IWMMXT.
* gcc.target/arm/pr99724.c: New test.
Alexandre Oliva [Wed, 24 Mar 2021 08:50:37 +0000 (05:50 -0300)]
run sysconf-requiring test on systems that support it
Some gcc.target/i386 tests requires the mmap feature, but that's not
enough for the test to be able to call sysconf.
This patch introduces a sysconf feature, analogous to mmap, and adds
it to tests in gcc.target/i386 that call sysconf.
There are other tests within gcc.dg and g++.dg that call sysconf, but
I haven't added the tag to them, because they already cover it with
target triplets. I was a little nervous about dropping the triplets,
and saw how they implied sysconf, so I left those alone.
for gcc/ChangeLog
* doc/sourcebuild.texi (sysconf): New effective target.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_effective_target_sysconf): New.
* gcc.target/i386/pr95443-1.c: Require it.
* gcc.target/i386/pr95443-2.c: Likewise.
* gcc.target/i386/sse2-mmx-maskmovq.c: Likewise.
* gcc.target/i386/strncmp-1.c: Likewise.
Alexandre Oliva [Wed, 24 Mar 2021 08:44:39 +0000 (05:44 -0300)]
require et feature pie for PIE tests
Both of these tests fail on platforms that reject -fPIC/-fPIE
altogether.
Other tests that perform PIE compilation or linking require the pie
feature, whether for -fpie/-fPIE compilation or for -pie linking.
This patch annotates both tests with the required target feature.
for gcc/testsuite/ChangeLog
* gcc.target/i386/pr97313.c: Require effective target feature pie.
* g++.target/i386/pr94185.C: Likewise.
Alexandre Oliva [Wed, 24 Mar 2021 08:44:36 +0000 (05:44 -0300)]
tighten funcspec regexps
In -mcmodel=large, callee symbols are pulled ahead of the call insns.
The patterns in funcspec-[12].c tests in gcc.target/i386 match even
line breaks between 'call' and a function symbol expected to be
called, however, so it ends up unexpectedly matching a previous,
unrelated indirect call, up to the insn that loads the address of the
intended callee to a register, for all but the first callee, that
doesn't have a call insn before it.
All of these apparent passes are false positives. We are NOT
generating the expected call insns.
This patch fixes only the patterns, so that they won't trigger false
positives any more. There are several dozens of other tests that fail
with -mcmodel=large for similar reasons, but I'm still not sure about
how to deal with them. I see no point in holding up this small
improvement over the lack of a larger solution of a different problem,
though.
for gcc/testsuite/ChangeLog
* gcc.target/i386/funcspec-2.c: Tighten regexps to avoid false
positives with -mcmodel=large.
* gcc.target/i386/funcspec-3.c: Likewise.
Alexandre Oliva [Wed, 24 Mar 2021 08:44:35 +0000 (05:44 -0300)]
fix ssse3_pshufbv8qi3 post-reload const pool load
The split in ssse3_pshufbv8qi3 forces a const vector into the constant
pool, and loads from it. That runs after reload, so if the load
requires any reloading, we're out of luck. Indeed, if the load
address is not legitimate, e.g. -mcmodel=large, the insn is no longer
recognized.
This patch turns the constant into an input operand, introduces an
expander to generate the constant unconditionally, and arranges for
this input operand to be retained as an unused immediate in the
alternatives that don't undergo splitting, and for it to be loaded
into the scratch register for those that do.
It is now the register allocator that arranges to load the const
vector into a register, so it deals with whatever legitimizing steps
needed for the target configuration.
for gcc/ChangeLog
* config/i386/predicates.md (reg_or_const_vec_operand): New.
* config/i386/sse.md (ssse3_pshufbv8qi3): Add an expander for
the now *-prefixed insn_and_split, turn the splitter const vec
into an input for the insn, making it an ignored immediate for
non-split cases, and loaded into the scratch register
otherwise.
for gcc/testsuite/ChangeLog
* gcc.target/i386/pr94467-3.c: New.
Tobias Burnus [Wed, 24 Mar 2021 06:50:22 +0000 (07:50 +0100)]
Fortran: Extend buffer, use snprintf to avoid overflows [PR99369]
gcc/fortran/ChangeLog:
PR fortran/99369
* resolve.c (resolve_operator): Make 'msg' buffer larger
and use snprintf.
gcc/testsuite/ChangeLog:
PR fortran/99369
* gfortran.dg/longnames.f90: New test.
GCC Administrator [Wed, 24 Mar 2021 00:16:25 +0000 (00:16 +0000)]
Daily bump.
Vladimir N. Makarov [Tue, 23 Mar 2021 21:51:21 +0000 (17:51 -0400)]
[PR99581] Use relaxed memory for more aarch64 memory constraints
The original patch for PR99581 resulted in GCC testsuite regression as
some constraints were not declared as relaxed memory ones. This patch
fixes this.
gcc/ChangeLog:
PR target/99581
* config/aarch64/constraints.md (Utq, UOb, UOh, UOw, UOd, UOty):
Use define_relaxed_memory_constraint for them.
Joseph Myers [Tue, 23 Mar 2021 20:50:53 +0000 (20:50 +0000)]
Update gcc .po files.
* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
zh_TW.po: Update.
Iain Sandoe [Tue, 23 Mar 2021 19:42:36 +0000 (19:42 +0000)]
Darwin : Address a translation comment.
Add a ':' to make the diagnostic read 'pch_address_space': xxx.
gcc/ChangeLog:
PR target/99733
* config/host-darwin.c (darwin_gt_pch_use_address): Add a
colon to the diagnostic message.
Nathan Sidwell [Tue, 23 Mar 2021 19:23:30 +0000 (12:23 -0700)]
c++: Note duplicates in symbol table [PR 99283]
I ran into this reducing 99283, we were failing to mark binding
vectors when the current TU declares a duplicate decl (as opposed to
an import introduces a duplicate).
PR c++/99283
gcc/cp/
* name-lookup.c (check_module_override): Set global or partition
DUP on the binding vector.
gcc/testsuite/
* g++.dg/modules/pr99283-1_a.H: New.
* g++.dg/modules/pr99283-1_b.H: New.
Ilya Leoshkevich [Tue, 2 Mar 2021 22:37:26 +0000 (23:37 +0100)]
fwprop: Fix single_use_p calculation
Commit
efb6bc55a93a ("fwprop: Allow (subreg (mem)) simplifications")
introduced a check that was supposed to look at the propagated def's
number of uses. It uses insn_info::num_uses (), which in reality
returns the number of uses def's insn has. The whole change therefore
works only by accident.
Fix by looking at set_info's uses instead of insn_info's uses. This
requires passing around set_info instead of insn_info.
gcc/ChangeLog:
2021-03-02 Ilya Leoshkevich <iii@linux.ibm.com>
* fwprop.c (fwprop_propagation::fwprop_propagation): Look at
set_info's uses.
(try_fwprop_subst_note): Use set_info instead of insn_info.
(try_fwprop_subst_pattern): Likewise.
(try_fwprop_subst_notes): Likewise.
(try_fwprop_subst): Likewise.
(forward_propagate_subreg): Likewise.
(forward_propagate_and_simplify): Likewise.
(forward_propagate_into): Likewise.
* rtl-ssa/accesses.h (set_info::single_nondebug_use) New
method.
(set_info::single_nondebug_insn_use): Likewise.
(set_info::single_phi_use): Likewise.
* rtl-ssa/member-fns.inl (set_info::single_nondebug_use) New
method.
(set_info::single_nondebug_insn_use): Likewise.
(set_info::single_phi_use): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/long-double-asm-abi.c: New test.
Jonathan Wakely [Tue, 23 Mar 2021 18:22:18 +0000 (18:22 +0000)]
libstdc++: Improve test for views::reverse
libstdc++-v3/ChangeLog:
* testsuite/std/ranges/adaptors/reverse.cc: Replace duplicated
line with a check that uses the const being/end overloads.
David Malcolm [Tue, 23 Mar 2021 17:09:07 +0000 (13:09 -0400)]
MAINTAINERS: add myself as static analyzer maintainer
ChangeLog:
* MAINTAINERS: Add myself as static analyzer maintainer.
Moritz Sichert [Tue, 23 Mar 2021 15:47:37 +0000 (15:47 +0000)]
libstdc++: Avoid accidental ADL when calling make_reverse_iterator
std::ranges::reverse_view uses make_reverse_iterator in its
implementation as described in [range.reverse.view]. This accidentally
allows ADL as an unqualified name is used in the call. According to
[contents], however, this should be treated as a qualified lookup into
the std namespace.
This leads to errors due to ambiguous name lookups when another
make_reverse_iterator function is found via ADL.
libstdc++-v3/Changelog:
* include/std/ranges (reverse_view::begin, reverse_view::end):
Qualify make_reverse_iterator calls to avoid ADL.
* testsuite/std/ranges/adaptors/reverse.cc: Test that
views::reverse works when make_reverse_iterator is defined
in an associated namespace.
Jakub Jelinek [Tue, 23 Mar 2021 15:29:47 +0000 (16:29 +0100)]
Add forgotten attribution on PR target/99593 testcase.
Christophe Lyon [Tue, 21 Apr 2020 07:31:59 +0000 (07:31 +0000)]
testsuite/arm: Add arm_dsp_ok effective target and use it in arm/acle/dsp_arith.c
gcc.target/arm/acle/dsp_arith.c uses DSP intrinsics, which arm_acle.h
defines only with __ARM_FEATURE_DSP, so make the test check for that
property rather than arm_qbit_ok.
However, the existing arm_dsp effective target only checks if DSP
features are supported with the current multilib rather than trying
-march and -mfloat-abi options. Thus we introduce a similar effective
target, arm_dsp_ok and associated dg-add-options.
This makes dsp_arith.c unsupported rather than failed when no option
combination is suitable, for instance when running the tests with
-mcpu=cortex-m3.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* doc/sourcebuild.texi (arm_dsp_ok, arm_dsp): Document.
gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_arm_dsp_ok_nocache)
(check_effective_target_arm_dsp_ok, add_options_for_arm_dsp): New.
* gcc.target/arm/acle/dsp_arith.c: Use arm_dsp_ok effective target
and add arm_dsp options.
Christophe Lyon [Tue, 21 Apr 2020 17:45:02 +0000 (17:45 +0000)]
testsuite/arm: Fix -mfloat-abi order in arm_v8_1m_mve_ok_nocache and arm_v8_1m_mve_fp_ok_nocache
Make the order in which we try -mfloat-abi options consistent with the
other similar effective targets: try softfp first, then hard.
This shows that a few tests implicitly rely on -mfloat-abi=hard, so we
add this option via dg-additional-options so that it comes after any
potential -mfloat-abi option that the preceding effective-targets
might have added.
armv8_1m-fpXX-move-1.c tests don't need arm_hard_ok because they don't
include arm_mve.h: adding -mfloat-abi=hard when using a soft/softfp
toolchain does not lead to the missing include gnu/stubs-*.h error.
This patch makes armv8_1m-fpXX-move-1.c pass on arm-linux-gnueabi, and
the other tests become unsupported (instead of fail) on this target.
On arm-eabi with default cpu/fpu/mode and a+rm multilibs, the same
mve/intrinsics/* tests become unsupported instead of pass because
arm_hard_ok fails with "selected processor lacks an FPU". Since we
also override the fpu via dg-options, we'd need another effective
target (say arm_hard_mve_ok) that would check -mfloat-abi=hard
-mfpu=auto -march=armv8.1-m.main+mve.fp at the same time. But we have
already so many arm effective targets, it doesn't seem like a good way
forward.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Fix
-mfloat-abi= options order.
(check_effective_target_arm_v8_1m_mve_ok_nocache): Likewise
* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Add
arm_hard_ok effective target and -mfloat-abi=hard additional
option.
* gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
* gcc.target/arm/armv8_1m-fp16-move-1.c: Add -mfloat-abi=hard
additional option.
* gcc.target/arm/armv8_1m-fp32-move-1.c: Likewise.
* gcc.target/arm/armv8_1m-fp64-move-1.c: Likewise.
Christophe Lyon [Mon, 20 Apr 2020 15:40:54 +0000 (15:40 +0000)]
testsuite/arm: Fix -mfloat-abi order in arm_v8_2a_bf16_neon_ok_nocache and arm_v8_2a_i8mm_ok_nocache
Make the order in which we try -mfloat-abi options consistent with the
other similar effective targets: try softfp first, then hard.
This shows that a few tests implicitly rely on -mfloat-abi=hard, so we
now check arm_hard_ok where needed.
This makes these tests unsupported rather than fail on
arm-linux-gnueabi.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_arm_v8_2a_i8mm_ok_nocache): Fix
-mfloat-abi= options order.
(check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): Likewise.
* gcc.target/arm/bfloat16_scalar_1_1.c: Add arm_hard_ok effective
target and -mfloat-abi=hard additional option.
* gcc.target/arm/bfloat16_simd_1_1.c: Likewise.
* gcc.target/arm/simd/bf16_ma_1.c: Likewise.
* gcc.target/arm/simd/bf16_mmla_1.c: Likewise.
* gcc.target/arm/simd/vdot-2-1.c: Likewise.
* gcc.target/arm/simd/vdot-2-2.c: Likewise.
Christophe Lyon [Sun, 26 Apr 2020 18:56:11 +0000 (18:56 +0000)]
testsuite/arm: Add arm_hard_ok check in armv8_2-fp16-scalar-2.c
This test relies on -mfloat-abi=hard to pass (otherwise
test_mov_imm_[12] directly build the 1.0 fp16 representation via movw
r0, #15360 rather than using vmov.f16 s0, #1.0e+0 as expected by
scan-assembler-times)
Adding the arm_hard_ok check makes the test unsupported eg. on
arm-linux-gnueabi instead of reporting a failure.
2021-03-20 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* gcc.target/arm/armv8_2-fp16-scalar-2.c: Add arm_hard_ok.
Christophe Lyon [Mon, 20 Apr 2020 22:37:23 +0000 (22:37 +0000)]
testsuite/arm: Add arm_softfp_ok or arm_hard_ok as needed.
Several tests override the -mfloat-abi option detected by their
effective targets. Make sure it is supported, so that these tests are
unsupported rather than failures (the inclusion of arm_neon.h
otherwise fails for lack of gnu/stubs-*.h)
This avoids failures with
bfloat16_simd_2_1.c
bfloat16_simd_3_1.c
bf16_vldn_1.c
bf16_vstn_1.c on arm-linux-gnueabi
and
pr51968.c
bfloat16_simd_1_2.c
bfloat16_simd_2_2.c
bfloat16_simd_3_2.c on arm-linux-gnueabihf.
On arm-eabi with default cpu/fpu/mode and a+rm multilibs,
bfloat16_simd_2_1.c, bfloat16_simd_3_1.c, bf16_vstn_1.c and
bf16_vldn_1.c become unsupported instead of pass because arm_hard_ok
fails with "selected processor lacks an FPU". Since we also override
the fpu in dg-additional-options, we'd need another effective target
(say arm_hard_neon_ok) that would check -mfloat-abi=hard -mfpu=neon at
the same time. But we have already so many arm effective targets, it
doesn't seem like a good way forward.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* gcc.target/arm/bfloat16_simd_1_2.c: Add arm_softfp_ok.
* gcc.target/arm/bfloat16_simd_2_2.c: Likewise.
* gcc.target/arm/bfloat16_simd_3_2.c: Likewise.
* gcc.target/arm/pr51968.c: Likewise.
* gcc.target/arm/bfloat16_simd_2_1.c: arm_hard_ok.
* gcc.target/arm/bfloat16_simd_3_1.c: Likewise.
* gcc.target/arm/simd/bf16_vldn_1.c: Likewise.
* gcc.target/arm/simd/bf16_vstn_1.c: Likewise.
Christophe Lyon [Tue, 21 Apr 2020 16:04:34 +0000 (16:04 +0000)]
testsuite/arm: Remove useless -mfloat-abi option
These tests pass with their current dg-add-options, no need to force
-mfloat=abi.
I've noticed no impact on armv8_1m-shift-imm-1.c and
armv8_1m-shift-reg-1.c, bf16_reinterpret.c now passes on
arm-linux-gnueabi and bf16_dup.c now passes on arm-linux-gnueabihf.
This allows pr51534.c to pass when forcing -mfloat-abi=soft in
runtestflags, otherwise we get an error '-mfloat-abi=soft and
-mfloat-abi=hard may not be used together' because we try to compile
with both flags.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* gcc.target/arm/armv8_1m-shift-imm-1.c: Remove -mfloat=abi option.
* gcc.target/arm/armv8_1m-shift-reg-1.c: Likewise.
* gcc.target/arm/bf16_dup.c: Likewise.
* gcc.target/arm/bf16_reinterpret.c: Likewise.
* gcc.target/arm/pr51534.c: Remove -mfloat=abi option.
Christophe Lyon [Mon, 20 Apr 2020 22:36:09 +0000 (22:36 +0000)]
testsuite/arm: Add arm_v8_2a_i8mm options in gcc.target/arm/simd/vmmla_1.c
We need to add the options corresponding to the arm_v8_2a_i8mm_ok
effective target in order to use the right float-abi option:
-mfloat-abi=softfp makes the test pass for arm-linux-gnueabi,
while no -mfloat-abi option is needed for arm-linux-gnueabihf.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* gcc.target/arm/simd/vmmla_1.c: Add arm_v8_2a_i8mm options.
Christophe Lyon [Thu, 18 Mar 2021 14:02:53 +0000 (14:02 +0000)]
testsuite/arm: Add arm_v8_2a_fp16_neon and arm_v8_2a_bf16_neon options
A few tests lack the dg-add-options directives associated with the
dg-require-effective-target they are using. Adding them enables to
pass the right float-abi option, and thus make the tests pass instead
of emit an error.
For instance, we now pass -mfloat-abi=softfp on arm-linux-gnueabi
targets and the tests pass.
2021-03-19 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
* gcc.target/arm/bfloat16_scalar_typecheck.c: Add
arm_v8_2a_fp16_neon and arm_v8_2a_bf16_neon.
* gcc.target/arm/bfloat16_vector_typecheck_1.c: Likewise.
* gcc.target/arm/bfloat16_vector_typecheck_2.c: Likewise.
Jonathan Wakely [Tue, 23 Mar 2021 13:08:32 +0000 (13:08 +0000)]
libstdc++: Disable "ALT128" long double support for Clang
Clang does not currently support the __ibm128 type [1] and only supports
the __ieee128 type in the unreleased 12.0.0 version [2]. That means it
is not possible to provide support for -mabi=ieeelongdouble with Clang
in an ABI compatible way (as we do for GCC by defining new facets and
other types in the __gnu_cxx_ldbl128 namespace).
By preventing the definition of _GLIBCXX_LONG_DOUBLE_ALT128_COMPAT when
compiling with Clang, all uses of __ibm128 and __ieee128 types will be
disabled. This can be revisited in future when Clang supports the types
(and provides a way to detect that support using the preprocessor).
[1] https://reviews.llvm.org/D93377
[2] https://reviews.llvm.org/D97846
libstdc++-v3/ChangeLog:
* include/bits/c++config (_GLIBCXX_LONG_DOUBLE_ALT128_COMPAT):
Do not define when compiling with Clang.
Marek Polacek [Wed, 10 Mar 2021 00:23:48 +0000 (19:23 -0500)]
c++: Fix bogus warning in deprecated namespace [PR99318]
In GCC 10, I introduced cp_warn_deprecated_use_scopes so that we can
handle attribute deprecated on a namespace declaration. This
function walks the decl's contexts so that we warn for code like
namespace [[deprecated]] N { struct S { }; }
N::S s;
We call cp_warn_deprecated_use_scopes when we encounter a TYPE_DECL.
But in the following testcase we have a TYPE_DECL whose context is
a deprecated function; that itself is not a reason to warn. This
patch limits for which entities we call cp_warn_deprecated_use;
essentially it's what can follow ::.
I noticed that we didn't test that
struct [[deprecated]] S { static void fn(); };
S::fn();
produces the expected warning, so I've added gen-attrs-73.C.
gcc/cp/ChangeLog:
PR c++/99318
* decl2.c (cp_warn_deprecated_use_scopes): Only call
cp_warn_deprecated_use when decl is a namespace, class, or enum.
gcc/testsuite/ChangeLog:
PR c++/99318
* g++.dg/cpp0x/attributes-namespace6.C: New test.
* g++.dg/cpp0x/gen-attrs-73.C: New test.
Tobias Burnus [Tue, 23 Mar 2021 14:45:36 +0000 (15:45 +0100)]
Fortran: Fix func decl mismatch [PR93660]
gcc/fortran/ChangeLog:
PR fortran/93660
* trans-decl.c (build_function_decl): Add comment;
increment hidden_typelist for caf_token/caf_offset.
* trans-types.c (gfc_get_function_type): Add comment;
add missing caf_token/caf_offset args.
gcc/testsuite/ChangeLog:
PR fortran/93660
* gfortran.dg/gomp/declare-simd-coarray-lib.f90: New test.
Richard Sandiford [Tue, 23 Mar 2021 14:02:03 +0000 (14:02 +0000)]
aarch64: Make aarch64_add_offset work with -ftrapv [PR99540]
aarch64_add_offset uses expand_mult to multiply the SVE VL by an
out-of-range constant. expand_mult takes an argument to indicate
whether the multiplication is signed or unsigned, but in this
context the multiplication is effectively signless and so the
choice seemed arbitrary.
However, one of the things that the signedness input does is
indicate whether signed overflow should be trapped for -ftrapv.
We don't want that here, so we must treat the multiplication
as unsigned.
gcc/
2021-03-23 Jakub Jelinek <jakub@redhat.com>
PR target/99540
* config/aarch64/aarch64.c (aarch64_add_offset): Tell
expand_mult to perform an unsigned rather than a signed
multiplication.
gcc/testsuite/
2021-03-23 Richard Sandiford <richard.sandiford@arm.com>
PR target/99540
* gcc.dg/vect/pr99540.c: New test.
H.J. Lu [Mon, 22 Mar 2021 02:47:24 +0000 (19:47 -0700)]
x86: Add __volatile__ to __cpuid and __cpuid_count
Since CPUID instruction may return different values on hybrid core.
volatile is needed on asm statements in <cpuid.h>.
PR target/99704
* config/i386/cpuid.h (__cpuid): Add __volatile__.
(__cpuid_count): Likewise.
Nathan Sidwell [Tue, 23 Mar 2021 12:18:04 +0000 (05:18 -0700)]
c++: Over-zealous assert [PR 99239]
This was simply an overzealous assert. Possibly correct thinking at
the time that code was written, but not true now. Of course we can
have imported artificial decls.
PR c++/99239
gcc/cp/
* decl.c (duplicate_decls): Remove assert about maybe-imported
artificial decls.
gcc/testsuite/
* g++.dg/modules/pr99239_a.H: New.
* g++.dg/modules/pr99239_b.H: New.
Richard Biener [Tue, 23 Mar 2021 08:10:17 +0000 (09:10 +0100)]
tree-optimization/99721 - avoid SLP nodes we cannot schedule
This makes sure we'll not run into SLP scheduling issues later by
rejecting all-constant children nodes without any scalar stmts early.
2021-03-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/99721
* tree-vect-slp.c (vect_slp_analyze_node_operations):
Make sure we can schedule the node.
* gfortran.dg/vect/pr99721.f90: New testcase.