Nathan Ridge [Mon, 15 Jun 2020 16:17:14 +0000 (12:17 -0400)]
[clangd] Follow-up to fix lit-test bustage in type-hierarchy.test
This is a follow-up to D81845.
Jacques Pienaar [Mon, 15 Jun 2020 16:04:54 +0000 (09:04 -0700)]
[mlir][shape] Update test case to new op asm format
Nathan Ridge [Mon, 15 Jun 2020 00:17:15 +0000 (20:17 -0400)]
[clangd] Support typeHierarchy/resolve for children of parents as well
Summary:
The initial implementation of typeHierarchy/resolve only supported
cases where an initial request was made for children, and then
typeHierarchy/resolve was used to get additional levels of children.
However, a client may also want to make an initial request for
parents, and then show other children of those parents, so support
typeHierarchy/resolve for items returned in response to a request
for parents as well.
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81845
Alex Zinenko [Mon, 15 Jun 2020 09:41:06 +0000 (11:41 +0200)]
[mlir] Introduce callback-based builders for AffineForOp
Similarly to `scf::ForOp`, introduce additional `function_ref` arguments to
`AffineForOp::build` that can be used to populate the body of the loop during
its construction. Provide compatibility functions for constructing affine loop
nests using `edsc::ScopedContext`.
`edsc::AffineLoopNestBuilder` and reletad functionality is now deprecated and
will be removed soon, users are expected to switch to `affineLoopNestBuilder`
that provides similar functionality with a simpler OpBuilder-based
implementation.
Differential Revision: https://reviews.llvm.org/D81754
Alex Zinenko [Mon, 15 Jun 2020 09:40:56 +0000 (11:40 +0200)]
[mlir] Affine symbols: do not expect AffineScope to always exist
In the affine symbol and dimension check, the code currently assumes
`getAffineScope` and its users `isValidDim` and `isValidSymbol` are only called
on values defined in regions that have a parent Op with `AffineScope` trait.
This is not necessarily the case, and these functions may be called on valid IR
that does not satisfy this assumption. Return `nullptr` from `getAffineScope`
if there is no parent op with `AffineScope` trait. Treat this case
conservatively in `isValidSymbol` by only accepting as symbols the values that
are guaranteed to be symbols (constants, and certain operations). No
modifications are necessary to `isValidDim` that delegates most of the work to
`isValidDim`.
Differential Revision: https://reviews.llvm.org/D81753
Alexander Belyaev [Mon, 15 Jun 2020 15:14:21 +0000 (17:14 +0200)]
[mlir][shape] Add a pattern to rewrite `shape.reduce` as `scf.for`.
Differential Revision: https://reviews.llvm.org/D81694
Denys Petrov [Mon, 15 Jun 2020 12:31:10 +0000 (15:31 +0300)]
[analyzer] Reasoning about comparison expressions in RangeConstraintManager
Summary:
Implemented RangeConstraintManager::getRangeForComparisonSymbol which handles comparison operators.
RangeConstraintManager::getRangeForComparisonSymbol cares about the sanity of comparison expressions sequences helps reasonably to branch an exploded graph.
It can significantly reduce the graph and speed up the analysis. For more details, please, see the differential revision.
This fixes https://bugs.llvm.org/show_bug.cgi?id=13426
Differential Revision: https://reviews.llvm.org/D78933
Matt Arsenault [Sat, 30 May 2020 23:50:55 +0000 (19:50 -0400)]
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.
Wouter van Oortmerssen [Tue, 19 May 2020 00:45:31 +0000 (17:45 -0700)]
[WebAssembly] Adding 64-bit versions of all load & store ops.
Context: https://github.com/WebAssembly/memory64/blob/master/proposals/memory64/Overview.md
This is just a first step, adding the new instruction variants while keeping the existing 32-bit functionality working.
Some of the basic load/store tests have new wasm64 versions that show that the basics of the target are working.
Further features need implementation, but these will be added in followups to keep things reviewable.
Differential Revision: https://reviews.llvm.org/D80769
Erich Keane [Mon, 15 Jun 2020 15:10:41 +0000 (08:10 -0700)]
[NFCI] Change the data structure of MaybeODRUseExprSet
In
1eddce41, I fixed a non-deterministic result problem by switching a
SmallPtrSet to a SmallSetVector to ensure we iterated it
deterministically. Unfortunately, this seems to show a surprisingly
significant compiletime impact.
This patch does 2 things in an attempt to fix this:
First, it makes the 'small size' optimization 4 instead of 2. As these
are pointers, this only increases the size of Sema by 4
sizeof(pointer)s (2 for the set, 2 for the vector).
Second, instead of using SmallSetVector, which is a SmallVector +
SmallDenseSet, it uses a SetVector of SmallVector + SmallPtrSet. The
hope is that the pointer-specific optimizations of the SmallPtrSet will
minimize the impact on compile-time.
Florian Hahn [Mon, 15 Jun 2020 14:59:09 +0000 (15:59 +0100)]
[DSE,MSSA] Delete instructions after printing it.
Also enables a now-passing test case, that exposed a crash caused by the
wrong order.
Simon Pilgrim [Mon, 15 Jun 2020 14:54:12 +0000 (15:54 +0100)]
[X86][SSE] Add LowerVectorAllZero helper for checking if all bits of a vector are zero.
Pull the lowering code out of LowerVectorAllZeroTest (and rename it MatchVectorAllZeroTest).
We should be able to reuse this in combineVectorSizedSetCCEquality as well.
Another cleanup to simplify D81547.
Stefan Pintilie [Mon, 15 Jun 2020 14:40:02 +0000 (09:40 -0500)]
[PowerPC] Do not add the relocation addend to the instruction encoding
We should not be adding the relocation addend to the instruction encoding.
This patch removes that and sets those bits to zero.
Differential Revision: https://reviews.llvm.org/D81082
Florian Hahn [Mon, 15 Jun 2020 11:34:12 +0000 (12:34 +0100)]
[DSE,MSSA] Add additional merging test cases (NFC).
Additional tests added ahead of partial overlapping store merging.
Dmitry Polukhin [Sat, 2 May 2020 09:35:41 +0000 (02:35 -0700)]
[clang-tidy] Add diagnostics level to YAML output
Summary:
Also added BuildDirectory for completness and removed unused `Fix`.
Test Plan: check-all
Reviewers: alexfh, gribozavr2
Subscribers: xazax.hun, cfe-commits
Tags: #clang-tools-extra, #clang
Differential Revision: https://reviews.llvm.org/D79285
Dominik Montada [Mon, 15 Jun 2020 14:35:18 +0000 (16:35 +0200)]
[NFC] Remove unnecessary require global-isel from tests
Dominik Montada [Mon, 15 Jun 2020 14:33:56 +0000 (16:33 +0200)]
[NFC] Add braces to if-statement in MachineVerifier
Simon Pilgrim [Mon, 15 Jun 2020 14:30:06 +0000 (15:30 +0100)]
[X86][SSE] LowerVectorAllZeroTest - add support for >256-bit vectors
Reduce by splitting the vector until we reach the target size for PTEST/MOVMSK_PCMPEQ. There might be some cases where AVX512 can perform this with 512-bit vectors but so far I haven't encountered any such pattern that reaches LowerVectorAllZeroTest.
Prep work for D81547
Hans Wennborg [Mon, 15 Jun 2020 14:08:25 +0000 (16:08 +0200)]
Revert "[X86] Separate imm from relocImm handling."
> relocImm was a complexPattern that handled both ConstantSDNode
> and X86Wrapper. But it was only applied selectively because using
> it would cause patterns to be not importable into FastISel or
> GlobalISel. So it only got applied to flag setting instructions,
> stores, RMW arithmetic instructions, and rotates.
>
> Most of the test changes are a result of making patterns available
> to GlobalISel or FastISel. The absolute-cmp.ll change is due to
> this fixing a pattern ordering issue to make an absolute symbol
> match to an 8-bit immediate before trying a 32-bit immediate.
>
> I tried to use PatFrags to reduce the repetition, but I was getting
> errors from TableGen.
This caused "Invalid EmitNode" assertions, see the llvm-commits thread for
discussion.
Simon Pilgrim [Mon, 15 Jun 2020 14:12:32 +0000 (15:12 +0100)]
[X86][SSE] LowerVectorAllZeroTest - remove unnecessary bitcasts
matchScalarReduction should return all its source vectors with the same type, so we can safely perform the OR reduction with the original type.
So we just need to bitcast for PTEST/PCMPEQB with the final reduced vector.
Yvan Roux [Mon, 15 Jun 2020 14:03:56 +0000 (16:03 +0200)]
[ARM][MachineOutliner] Fix no-lr-save testcase.
Now that saving LR into a register is handled, some register constraints
are needed to keep machine-outliner-no-lr-save.mir meaningful.
Kevin P. Neal [Thu, 14 May 2020 18:57:19 +0000 (11:57 -0700)]
[strictfp] Replace dangling strictfp attrs with nobuiltin
In preparation for a patch that will enforce new rules for the usage of
the strictfp attribute, this patch introduces auto-upgrade behavior that
will replace the strictfp attribute on callsites with nobuiltin if the
enclosing function declaration doesn't also have the strictfp attribute.
This auto-upgrade isn't being performed on .ll files because that would
prevent us from writing a test for the forthcoming verifier behavior.
Differential Revision: https://reviews.llvm.org/D70096
Jeff Mott [Mon, 15 Jun 2020 13:08:58 +0000 (06:08 -0700)]
[clang] Fix or emit diagnostic for checked arithmetic builtins with
_ExtInt types
- Fix computed size for _ExtInt types passed to checked arithmetic
builtins.
- Emit diagnostic when signed _ExtInt larger than 128-bits is passed
to __builtin_mul_overflow.
- Change Sema checks for builtins to accept placeholder types.
Differential Revision: https://reviews.llvm.org/D81420
Marcel Koester [Mon, 15 Jun 2020 11:51:53 +0000 (13:51 +0200)]
[mlir] Fixed GCC compile issues and linking problems using SHARED_LIBS.
Differential Revision: https://reviews.llvm.org/D81839
Balázs Kéri [Mon, 15 Jun 2020 12:59:54 +0000 (14:59 +0200)]
[Analyzer][StreamChecker] Add check for pointer escape.
Summary:
After an escaped FILE* stream handle it is not possible to make
reliable checks on it because any function call can have effect
on it.
Reviewers: Szelethus, baloghadamsoftware, martong, NoQ
Reviewed By: NoQ
Subscribers: NoQ, rnkovacs, xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, gamesh411, Charusso, martong, ASDenysPetrov, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D80699
Yvan Roux [Mon, 15 Jun 2020 13:22:08 +0000 (15:22 +0200)]
[ARM][MachineOutliner] Add LR RegSave mode.
Outline chunks of code which need to save and restore the link register
when a spare register can be used to it.
Differential Revision: https://reviews.llvm.org/D80127
Daniel Kiss [Mon, 15 Jun 2020 13:02:38 +0000 (15:02 +0200)]
[AArch64] Fix BTI instruction emission.
Summary:
SCTLR_EL1.BT[01] controls the PACI[AB]SP compatibility with PBYTE 11
(see [1])
This bit will be set to zero so PACI[AB]SP are equal to BTI C
instruction only.
[1] https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/sctlr_el1
Reviewers: chill, tamas.petz, pbarrio, ostannard
Reviewed By: tamas.petz, ostannard
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81746
Jacques Pienaar [Mon, 15 Jun 2020 13:01:31 +0000 (06:01 -0700)]
[mlir] Remove OperandAdaptor
Use ::Adaptor alias instead uniformly. Makes the naming more consistent as
adaptor can refer to attributes now too.
Differential Revision: https://reviews.llvm.org/D81789
Matt Arsenault [Wed, 10 Jun 2020 00:05:05 +0000 (20:05 -0400)]
AMDGPU/GlobalISel: Workaround some load/store type selection patterns
The logic is written for what loads/stores should be selectable. There
are a set of cases that should be selectable, but due to missing MVTs
and/or selection patterns, will fail to select. I think eventually
load/store select patterns should ignore the type and only look at the
value size, but until that happens, bitcast these to equivalent i32
vectors.
Matt Arsenault [Tue, 9 Jun 2020 20:21:07 +0000 (16:21 -0400)]
AMDGPU/GlobalISel: Use less artifical example to avoid abort=0
These were failing due to an unlegalizable G_CONCAT_VECTORS due to
registers with types that are naturally illegal.
Matt Arsenault [Tue, 9 Jun 2020 15:19:12 +0000 (11:19 -0400)]
GlobalISel: Support lowering vector->vector G_BITCAST
Extract subvectors and cast to the result element type before
remerging.
Sander de Smalen [Mon, 15 Jun 2020 08:47:49 +0000 (09:47 +0100)]
Fix clang/test/Modules/empty.modulemap by increasing limit.
This fixes a buildbot failure on Builder llvm-clang-win-x-aarch64.
The size of the module increased to just over 30kb due to new
Decl TypeDefs being added to the module after D81459 that
adds new ACLE types.
Tyker [Sun, 14 Jun 2020 12:39:14 +0000 (14:39 +0200)]
attempt to fix failing buildbots after
3bab88b7baa20b276faaee0aa7ca87f636c91877
Prevent IR-gen from emitting consteval declarations
Summary: with this patch instead of emitting calls to consteval function. the IR-gen will emit a store of the already computed result.
James Henderson [Tue, 9 Jun 2020 14:37:55 +0000 (15:37 +0100)]
[DebugInfo] Report errors for truncated debug line standard opcode
Standard opcodes usually have ULEB128 arguments, so it is generally not
possible to recover from such errors. This patch causes the parser to
stop parsing the table in such situations.
Also don't emit the operands or add data to the table if there is an
error reading these opcodes.
Reviewed by: JDevlieghere
Differential Revision: https://reviews.llvm.org/D81470
Frederik Gossen [Mon, 15 Jun 2020 10:45:03 +0000 (10:45 +0000)]
[MLIR][Standard] Simplify complex operand unpacking
Apply post-commit suggestions (see https://reviews.llvm.org/D79479).
Differential Revision: https://reviews.llvm.org/D81731
Frederik Gossen [Mon, 15 Jun 2020 10:39:05 +0000 (10:39 +0000)]
[MLIR][Standard] Add documentation for `std.dim` and fix test cases
Apply post-commit suggestions (see https://reviews.llvm.org/D81551).
Add documentation, simplify, and fix test cases.
Differential Revision: https://reviews.llvm.org/D81722
Kirill Bobyrev [Mon, 15 Jun 2020 10:27:30 +0000 (12:27 +0200)]
Revert "[lld-macho] No need to explicitly specify -arch in tests"
This reverts commit
51c5baacf36f5d5d0dbed00590a9e56a5f4a0d73 and also
337fb8c767ea93058517cb9b0be5daf21b448b71 - "[lld-macho] Set REQUIRES:
x86 on more tests".
These patches cause test crashes:
http://lab.llvm.org:8011/builders/ppc64le-lld-multistage-test/builds/10054
Marcel Koester [Wed, 6 May 2020 13:06:19 +0000 (15:06 +0200)]
[mlir] Extended BufferPlacement to support more sophisticated scenarios in which
allocations cannot be moved freely and can remain in divergent control flow.
The current BufferPlacement pass does not support allocation nodes that carry
additional dependencies (like in the case of dynamic shaped types). These
allocations can often not be moved freely and in turn might remain in divergent
control-flow branches. This requires a different strategy with respect to block
arguments and aliases. This CL adds additinal functionality to support
allocation nodes in divergent control flow while avoiding memory leaks.
Differential Revision: https://reviews.llvm.org/D79850
Kirill Bobyrev [Mon, 15 Jun 2020 10:14:15 +0000 (12:14 +0200)]
Revert "Prevent IR-gen from emitting consteval declarations"
This reverts commit
3bab88b7baa20b276faaee0aa7ca87f636c91877.
This patch causes test failures:
http://lab.llvm.org:8011/builders/clang-cmake-armv7-quick/builds/17260
Georgii Rymar [Thu, 11 Jun 2020 13:46:56 +0000 (16:46 +0300)]
[yaml2obj] - Introduce the "NoHeaders" key for "SectionHeaderTable"
We have an issue currently. The following YAML piece just ignores the `Excluded` key.
```
SectionHeaderTable:
Sections: []
Excluded:
- Name: .foo
```
Currently the meaning is: exclude the whole table.
The code checks that the `Sections` key is empty and doesn't catch/check
invalid/duplicated/missed `Excluded` entries.
Also there is no way to exclude all sections except the first null section,
because `Sections: []` currently just excludes the whole the sections header table.
To fix it, I suggest a change of the behavior.
1) A new `NoHeaders` key is added. It provides an explicit syntax to drop the whole table.
2) The meaning of the following is changed:
```
SectionHeaderTable:
Sections: []
Excluded:
- Name: .foo
```
Assuming there are 2 sections in the object (a null section and `.foo`), with this patch it
means: exclude the `.foo` section, keep the null section. The null section is an implicit
section and I think it is reasonable to make "Sections: []" to mean it is implicitly added.
It will be consistent with the global "Sections" tag that is used to describe sections.
3) `SectionHeaderTable->Sections` is now optional. No `Sections` is the same as
`Sections: []` (I think it avoids a confusion).
4) Using of `NoHeaders` together with `Sections`/`Excluded` is not allowed.
5) It is possible to use the `Excluded` key without the `Sections` key now (in this case
`Excluded` must contain all sections).
6) `SectionHeaderTable:` or `SectionHeaderTable: []` is not allowed.
7) When the `SectionHeaderTable` key is present, we still require all sections to be
present in `Sections` and `Excluded` lists. No changes here, we are still strict.
Differential revision: https://reviews.llvm.org/D81655
Simon Pilgrim [Mon, 15 Jun 2020 09:40:27 +0000 (10:40 +0100)]
[X86][SSE] Add tests for and/or reduction results compared to zero
These should fold to memcmp/ptest/movmsk+cmpeq patterns
Haojian Wu [Fri, 12 Jun 2020 14:05:38 +0000 (16:05 +0200)]
[clangd] Turn on RecoveryAST for clangd by default.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81739
Kazushi (Jam) Marukawa [Mon, 15 Jun 2020 09:21:54 +0000 (11:21 +0200)]
[VE] Support relocation information in MC layer
Summary:
Change VEAsmParser to support identification with relocation information
in assmebler. Change VEAsmBackend to support relocation information in
MC layer. Change VEDisassembler and VEMCCodeEmitter to support binary
generation of branch target operands. Add REFLONG fixup and variant kind
to support new R_VE_REFLONG ELF symbol. And, add regression test in both
MC and CodeGen to check binary genaration with relocation information.
Differential Revision: https://reviews.llvm.org/D81553
Dominik Montada [Wed, 10 Jun 2020 15:15:09 +0000 (17:15 +0200)]
[MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT
Summary:
Teach MachineVerifier to check branches for MBB operands if they are not declared indirect.
Add `isBarrier`, `isIndirectBranch` to `G_BRINDIRECT` and `G_BRJT`.
Without these, `MachineInstr.isConditionalBranch()` was giving a
false-positive for those instructions.
Reviewers: aemerson, qcolombet, dsanders, arsenm
Reviewed By: dsanders
Subscribers: hiraditya, wdng, simoncook, s.egerton, arsenm, rovka, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81587
Max Kazantsev [Mon, 15 Jun 2020 08:56:06 +0000 (15:56 +0700)]
[Test] Add an example of unprofitable PR Phi insertion
This test demonstrates weird behavior of SimplifyCFG: seems that bigger
size of block leads to worse optimization choice.
Tyker [Sun, 14 Jun 2020 12:39:14 +0000 (14:39 +0200)]
Prevent IR-gen from emitting consteval declarations
Summary: with this patch instead of emitting calls to consteval function. the IR-gen will emit a store of the already computed result.
Reviewers: rsmith
Reviewed By: rsmith
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D76420
Kirill Bobyrev [Mon, 15 Jun 2020 08:45:08 +0000 (10:45 +0200)]
NFC: Make sure function arguments have the same name in declaration and definition
This code generates Clang-Tidy warnings otherwise.
Alexander Belyaev [Fri, 12 Jun 2020 13:50:03 +0000 (15:50 +0200)]
[mlir][shape] Lower Shape `ConstSizeOp` to Standard `ConstantOp`.
Differential Revision: https://reviews.llvm.org/D81735
Sam Parker [Mon, 15 Jun 2020 07:58:25 +0000 (08:58 +0100)]
[CostModel] getCFInstrCost in getUserCost.
Have BasicTTI call the base implementation so that both agree on the
default behaviour, which the default being a cost of '1'. This has
required an X86 specific implementation as it seems to be very
reliant on those instructions being free. Changes are also made to
AMDGPU so that their implementations distinguish between cost kinds,
so that the unrolling isn't affected. PowerPC also has its own
implementation to prevent changes to the reg-usage vectorizer test.
The cost model test changes now reflect that ret instructions are not
generally free.
Differential Revision: https://reviews.llvm.org/D79164
Kirill Bobyrev [Mon, 15 Jun 2020 08:18:59 +0000 (10:18 +0200)]
[lldb] Handle all Clang::Type::Builtin enums
Cleanup after https://reviews.llvm.org/D81459
Kristina Bessonova [Wed, 10 Jun 2020 14:18:30 +0000 (16:18 +0200)]
[CMake][runtimes] Skip adding 2nd set of the same variables for a generic target
No need to parse and add the same variables twice if runtimes is being
built for a generic target (i.e. w/o multilib).
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D81574
Sam Parker [Thu, 11 Jun 2020 08:59:12 +0000 (09:59 +0100)]
[NFCI][CostModel] Unify FNeg cost
Enable TTIImpl::getUserCost to handle FNeg so that
getInstructionThroughput can call that instead. This means we can
remove the code in the AMDGPU backend too.
Differential Revision: https://reviews.llvm.org/D81635
Nikita Popov [Sun, 14 Jun 2020 21:52:39 +0000 (23:52 +0200)]
[IR] Prefer hasFnAttribute() where possible (NFC)
When checking for an enum function attribute, use hasFnAttribute()
rather than hasAttribute() at FunctionIndex, because it is
significantly faster (and more concise to boot).
Sam Parker [Mon, 15 Jun 2020 07:27:14 +0000 (08:27 +0100)]
[CostModel] Unify ExtractElement cost.
Move the cost modelling, with the reduction pattern matching, from
getInstructionThroughput into generic TTIImpl::getUserCost. The
modelling in the AMDGPU backend can now be removed.
Differential Revision: https://reviews.llvm.org/D81643
Max Kazantsev [Mon, 15 Jun 2020 06:58:54 +0000 (13:58 +0700)]
[NFC] Bail early simplifying unconditional branches
Fangrui Song [Mon, 15 Jun 2020 06:00:04 +0000 (23:00 -0700)]
[msan] Fix comment of __msan::Origin::isHeapOrigin
Sam Parker [Mon, 15 Jun 2020 06:46:28 +0000 (07:46 +0100)]
Revert "Return "[InstCombine] Simplify compare of Phi with constant inputs against a constant""
This reverts commit
23291b9863c8af7ad348c4a7d85d8d784df88eb1.
This caused performance regressions.
Sander de Smalen [Mon, 15 Jun 2020 06:20:55 +0000 (07:20 +0100)]
[SVE] Ensure proper mangling of ACLE tuple types
The AAPCS specifies that the tuple types such as `svint32x2_t`
should use their `arm_sve.h` names when mangled instead of their
builtin names.
This patch also renames the internal types for the tuples to
be prefixed with `__clang_`, so they are not misinterpreted as
specified internal types like the non-tuple types which *are* defined
in the AAPCS. Using a builtin type for the tuples is a purely
a choice of the Clang implementation.
Reviewers: rsandifo-arm, c-rhodes, efriedma, rengolin
Reviewed By: efriedma
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81721
Sander de Smalen [Mon, 15 Jun 2020 06:20:43 +0000 (07:20 +0100)]
[SveEmitter] Add SVE tuple types and builtins for svundef.
This patch adds new SVE types to Clang that describe tuples of SVE
vectors. For example `svint32x2_t` which maps to the twice-as-wide
vector `<vscale x 8 x i32>`. Similarly, `svint32x3_t` will map to
`<vscale x 12 x i32>`.
It also adds builtins to return an `undef` vector for a given
SVE type.
Reviewers: c-rhodes, david-arm, ctetreau, efriedma, rengolin
Reviewed By: c-rhodes
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81459
Vitaly Buka [Mon, 15 Jun 2020 06:03:13 +0000 (23:03 -0700)]
[SafeStack,NFC] Make StackColoring read-only
Move core which removes markers out of StackColoring.
Vitaly Buka [Mon, 15 Jun 2020 04:28:34 +0000 (21:28 -0700)]
[SafeStack,NFC] Remove unneded branch
Vitaly Buka [Mon, 15 Jun 2020 02:04:47 +0000 (19:04 -0700)]
[SafeStack,NFC] Fix naming style
Vitaly Buka [Mon, 15 Jun 2020 01:59:23 +0000 (18:59 -0700)]
[SafeStack,NFC] Cleanup LiveRange interface
Vitaly Buka [Sun, 14 Jun 2020 23:31:09 +0000 (16:31 -0700)]
[SafeStack,NFC] "const" cleanup
Vitaly Buka [Sun, 14 Jun 2020 23:06:07 +0000 (16:06 -0700)]
[SafeStack,NFC] Add BlockLifetimeInfo constructor
Vitaly Buka [Sun, 14 Jun 2020 22:58:10 +0000 (15:58 -0700)]
[SafeStack,NFC] Use IntrinsicInst instead of Instruction
Vitaly Buka [Sun, 14 Jun 2020 22:32:07 +0000 (15:32 -0700)]
[SafeStack,NFC] Move ClColoring into SafeStack.cpp
This allows to reuse the code in other components.
Vitaly Buka [Sun, 14 Jun 2020 21:35:34 +0000 (14:35 -0700)]
[SafeStack,NFC] Move unconditional code into constructor
Prepare to move ClColoring from SafeStackCode to SafeStackLayout.
This will allow to reuse the code in other components.
Max Kazantsev [Mon, 15 Jun 2020 05:36:33 +0000 (12:36 +0700)]
[Test] Update test with check script, add two more motivating cases
Chen Zheng [Mon, 15 Jun 2020 01:34:52 +0000 (21:34 -0400)]
[PowerPC] fma chain break to expose more ILP
This patch tries to reassociate two patterns related to FMA to expose
more ILP on PowerPC.
// Pattern 1:
// A = FADD X, Y (Leaf)
// B = FMA A, M21, M22 (Prev)
// C = FMA B, M31, M32 (Root)
// -->
// A = FMA X, M21, M22
// B = FMA Y, M31, M32
// C = FADD A, B
// Pattern 2:
// A = FMA X, M11, M12 (Leaf)
// B = FMA A, M21, M22 (Prev)
// C = FMA B, M31, M32 (Root)
// -->
// A = FMUL M11, M12
// B = FMA X, M21, M22
// D = FMA A, M31, M32
// C = FADD B, D
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D80175
Wenlei He [Tue, 26 May 2020 20:53:35 +0000 (13:53 -0700)]
[NewPM] Avoid redundant CGSCC run for updated SCC
Summary:
When an SCC got split due to inlining, we have two mechanisms for reprocessing the updated SCC, first is UR.UpdatedC
that repeatedly rerun the new, current SCC; second is a worklist for all newly split SCCs. We can avoid rerun of
the same SCC when the SCC is set to be processed by both mechanisms *back to back*. In pathological cases, such redundant
rerun could cause exponential size growth due to inlining along cycles, even when there's no SCC mutation and hence
convergence is not a problem.
Note that it's ok to have SCC updated and rerun immediately, and also in the work list if we have actually moved an SCC
to be topologically "below" the current one due to merging. In that case, we will need to revisit the current SCC after
those moved SCCs. For that reason, the redundant avoidance here only targets back to back rerun of the same SCC - the
case described by the now removed FIXME comment.
Reviewers: chandlerc, wmi
Subscribers: llvm-commits, hoy
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80589
Kang Zhang [Mon, 15 Jun 2020 02:43:13 +0000 (02:43 +0000)]
[PowerPC] Add some InstAlias for mtspr/mfspr instructions
Summary:
We have defined MTSPR/MFSPR and MTSPR8/MFSPR8, but we only defined
mtspr/mfspr InstAlias for some MTSPR/MFSPR.
This patch is to add the InstAlias definitions for MTSPR8/MFSPR8,
and add the some new mtspr/mfspr InstAlias we may use.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D77531
Jez Ng [Mon, 15 Jun 2020 01:59:28 +0000 (18:59 -0700)]
[lld-macho] Set REQUIRES: x86 on more tests
Summary: Fixes the build break caused by D81802.
Chen Zheng [Mon, 15 Jun 2020 01:22:50 +0000 (21:22 -0400)]
[PowerPC] fold a bug for rlwinm folding when with full mask.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D81006
Jez Ng [Sun, 14 Jun 2020 02:52:20 +0000 (19:52 -0700)]
[lld-macho] Properly handle & validate relocation r_length
Summary:
We should be reading / writing our addends / relocated addresses based on
r_length, and not just based on the type of the relocation. But since only
some r_length values are valid for a given reloc type, I've also added some
validation.
ld64 has code to allow for r_length = 0 in X86_64_RELOC_BRANCH relocs, but I'm
not sure how to create such a relocation...
Reviewed By: smeenai
Differential Revision: https://reviews.llvm.org/D80854
Jez Ng [Sun, 14 Jun 2020 04:45:29 +0000 (21:45 -0700)]
[lld-macho] No need to explicitly specify -arch in tests
Summary: After {D81326} landed, some tests started failing if they did
not have `-arch` specified. I think one of the reasons happened was due
to the fact that we were taking a reference to a temporary value that
was freed too early. Fixing that got the error to go away on my local
Linux machine.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D81802
Simon Pilgrim [Sun, 14 Jun 2020 16:53:33 +0000 (17:53 +0100)]
[X86][SSE] Fold BITOP(MOVMSK(X),MOVMSK(Y)) -> MOVMSK(BITOP(X,Y))
Reduce XMM->GPR traffic by performing bitops on the vectors, and using a single MOVMSK call.
This requires us to use vectors of the same size and element width, but we can mix fp/int type equivalents with suitable bitcasting.
Nikita Popov [Sun, 14 Jun 2020 20:27:17 +0000 (22:27 +0200)]
[IR] Remove unused IndexAttrPair typedef (NFC)
This was part of an older attributes implementation.
Nikita Popov [Sat, 13 Jun 2020 19:10:22 +0000 (21:10 +0200)]
[IR] Support efficient AssertingVH/PoisoningVH lookup
Currently, there doesn't seem to be any way to look up a Value*
in a map/set indexed by AssertingVH/PoisoningVH, without creating
a value handle -- which is fairly expensive, because it involves
adding the value handle to the use list and immediately removing
it again. Using find_as(Value *) does not work (and is in fact
worse than just using find(Value *)), because it will end up
creating multiple value handles during the lookup itself.
For AssertingVH, address this by simply using DenseMapInfo<T *>
instead of manually implementing something. The AssertingVH<T>
will now get coerced to T*, rather than the other way around.
For PoisoningVH, add extra overloads of getHashValue() and
isEqual() that accept a T* argument.
This allows using find_as(Value *) to perform efficient lookups
in assertion-enabled builds.
Differential Revision: https://reviews.llvm.org/D81793
Florian Hahn [Sat, 13 Jun 2020 13:24:50 +0000 (14:24 +0100)]
[LAA] Do not set CanDoRT to false for AS that do not need RT checks.
Alternative approach to D80570.
canCheckPtrAtRT already contains checks the figure out for which alias
sets runtime checks are needed. But it currently sets CanDoRT to false
for alias sets for which we cannot do RT checks but also do not need
any.
If we know that we do not need RT checks based on the number of
reads/writes in the alias set, we can skip processing the AS.
This patch also adds an assertion to ensure that DepCands does not
contain more than one write from the alias set.
Reviewers: Ayal, anemet, hfinkel, dmgreen
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D80622
Whitney Tsang [Sun, 14 Jun 2020 18:42:24 +0000 (18:42 +0000)]
[LoopUnroll] Allow loops with multiple exiting blocks where loop latch
is not necessary one of them.
Summary: Currently LoopUnrollPass already allow loops with multiple
exiting blocks, but it is only allowed when the loop latch is one of the
exiting blocks.
When the loop latch is not an exiting block, then only single exiting
block is supported.
When possible, the single loop latch or the single exiting block
terminator is optimized to an unconditional branch in the unrolled loop.
This patch allows loops with multiple exiting blocks even if the loop
latch is not one of them. However, the optimization of exiting block
terminator to unconditional branch is not done when there exists more
than one exiting block.
Reviewer: dmgreen, Meinersbur, etiotto, fhahn, efriedma, bmahjour
Reviewed By: efriedma
Subscribers: hiraditya, zzheng, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D81053
Matt Arsenault [Sun, 14 Jun 2020 16:16:38 +0000 (12:16 -0400)]
AMDGPU: Add some baseline immediate encoding test changes
Add some encoding checks and add a few new cases.
Matt Arsenault [Thu, 11 Jun 2020 20:09:41 +0000 (16:09 -0400)]
AMDGPU: Do not bundle inline asm
Fixes bug 46285
Matt Arsenault [Wed, 10 Jun 2020 13:40:51 +0000 (09:40 -0400)]
GlobalISel: Add some basic getters to GISelKnownBits
Matt Arsenault [Sat, 23 May 2020 21:10:58 +0000 (17:10 -0400)]
AMDGPU/GlobalISel: Select general case for G_PTRMASK
Matt Arsenault [Fri, 12 Jun 2020 01:40:21 +0000 (21:40 -0400)]
AMDGPU: Fix spill/restore of 192-bit registers
I tried to use an IR inline asm test, but that doesn't work since the
inline asm handling asserts without an MVT to use.
Simon Pilgrim [Sun, 14 Jun 2020 15:24:18 +0000 (16:24 +0100)]
[X86][SSE] Add tests for missing BITOP(MOVMSK(X),MOVMSK(Y)) -> MOVMSK(BITOP(X,Y)) fold
This would help reduce XMM->GPR traffic for some reduction cases.
Qiu Chaofan [Sun, 14 Jun 2020 15:43:31 +0000 (23:43 +0800)]
[PowerPC] Support constrained rounding operations
This patch adds handling of constrained FP intrinsics about round,
truncate and extend for PowerPC target, with necessary tests.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D64193
Qiu Chaofan [Sun, 14 Jun 2020 15:19:17 +0000 (23:19 +0800)]
[PowerPC] Exploit vnmsubfp instruction
On PowerPC, we have vnmsubfp Altivec instruction for fnmsub operation on
v4f32 type. Default pattern for this instruction never works since we
don't have legal fneg for v4f32 when VSX disabled.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D80617
Qiu Chaofan [Sun, 14 Jun 2020 14:58:22 +0000 (22:58 +0800)]
[DAGCombiner] Require ninf for division estimation
Current implementation of division estimation isn't correct for some
cases like 1.0/0.0 (result is nan, not expected inf).
And this change exposes a potential infinite loop: we use
isConstOrConstSplatFP in combineRepeatedFPDivisors to look up if the
divisor is some constant. But it doesn't work after legalized on some
platforms. This patch restricts the method to act before LegalDAG.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D80542
Sanjay Patel [Sun, 14 Jun 2020 13:50:10 +0000 (09:50 -0400)]
[PassManager] restore early-cse to vector cleanup
As noted in D80236 - the early-cse pass was included here before:
D75145 / rG71a316883d50
But it got moved outside of the "extra" option there, then it
got dropped while adjusting -vector-combine:
rG6438ea45e053
rG57bb4787d72f
So this is restoring the behavior and adding a test to prevent
accidental changes again. I don't see an equivalent option for
the new pass manager.
Joachim Protze [Wed, 11 Mar 2020 16:02:19 +0000 (17:02 +0100)]
[OpenMP][Tool] Extend reuse of OMPT testing
This patch allows to specify a prefix (default:empty) to be included into print-out
written by callback.h.
Also adding a cmake target to find the header file from other tests.
Reviewed by: jdoerfert
Differential Revision: https://reviews.llvm.org/D76008
Joachim Protze [Wed, 10 Jun 2020 14:44:52 +0000 (16:44 +0200)]
[OpenMP] support alloc of serialized tasks
Reviewed by: AndreyChurbanov
Differential Revision: https://reviews.llvm.org/D81497
Nikita Popov [Sun, 14 Jun 2020 13:42:27 +0000 (15:42 +0200)]
[LVI] Fix class indentation (NFC)
This class uses a mix of different indentation levels, normalize it.
Nikita Popov [Sat, 13 Jun 2020 13:36:55 +0000 (15:36 +0200)]
[LVI] Cache lookup of experimental.guard intrinsic (NFC)
When LVI is performing assume intersections, it also checks for
llvm.experimental.guard intrinsics. To avoid unnecessary block
scans, it first checks whether this intrinsic is declared in the
module at all. I've noticed that we end up spending quite a lot
of time looking up that function again and again...
Avoid this by only looking it up once when LazyValueInfo is
constructed. This of course assumes that we don't introduce new
guard intrinsics (which is the case for all existing uses of LVI --
and even if it weren't, it would not introduce miscompiles, just
potentially lose optimization power.)
Differential Revision: https://reviews.llvm.org/D81796
David Green [Sun, 14 Jun 2020 11:05:20 +0000 (12:05 +0100)]
[ARM] Additional cast cost tests.
This adds additional cast cpst tests useful for MVE, notably around half
types.
Sanjay Patel [Sun, 14 Jun 2020 13:09:03 +0000 (09:09 -0400)]
[InstCombine] reassociate FP diff of sums into sum of diffs
(a[0] + a[1] + a[2] + a[3]) - (b[0] + b[1] + b[2] +b[3]) -->
(a[0] - b[0]) + (a[1] - b[1]) + (a[2] - b[2]) + (a[3] - b[3])
This should be the last step in solving PR43953:
https://bugs.llvm.org/show_bug.cgi?id=43953
We started emitting reduction intrinsics with:
D80867/ rGe50059f6b6b3
So it's a relatively easy pattern match now to re-order those ops.
Also, I have not seen any complaints for the switch to intrinsics
yet, so I'll propose to remove the "experimental" tag from the
intrinsics soon.
Differential Revision: https://reviews.llvm.org/D81491
Sanjay Patel [Sun, 14 Jun 2020 13:01:33 +0000 (09:01 -0400)]
[InstCombine] allow undef elements when comparing vector constants for min/max bailout
This is a hacky, but low-risk fix to avoid the infinite loop in PR46271:
https://bugs.llvm.org/show_bug.cgi?id=46271
As discussed there, the problem is that FoldOpIntoSelect() can get into a conflict
with a transform that wants to pull a 'not' op through min/max via
SimplifyDemandedVectorElts(). We need to relax our matching of min/max to include
undefined elements in vector constants to avoid that. Alternatively, we could
improve or cripple the demanded elements analysis, but that could create even
more problems.
The likely better, safer alternative will be to create min/max intrinsics, so
we can remove all of the hacks related to min/max matching in instcombine.
Differential Revision: https://reviews.llvm.org/D81698
Simon Pilgrim [Sun, 14 Jun 2020 12:10:33 +0000 (13:10 +0100)]
[X86][SSE] LowerVectorAllZeroTest - add support for pre-SSE41 targets
Even without PTEST, we can still efficiently perform an OR reduction as PMOVMSKB(PCMPEQB(X,0)) == 0, avoiding xmm->gpr extractions.
Uday Bondhugula [Sun, 14 Jun 2020 12:29:06 +0000 (17:59 +0530)]
[MLIR][NFC] Update vim syntax file
Add a few more commonly used ops and missing keywords.