Jay Cornwall [Wed, 20 Nov 2019 22:13:03 +0000 (16:13 -0600)]
drm/amdkfd: Support newer assemblers in gfx10 trap handler
The contents of macros are parsed by the assembler before conditions
have been tested. This causes assembly errors when using IP-specific
instructions in the IP-unified trap handler.
Add a preprocessing step to filter IP-specific code.
Also guard a Navi1x-specific instruction (no effect on Sienna_Cichlid).
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sat, 2 Nov 2019 00:05:08 +0000 (19:05 -0500)]
drm/amdkfd: Add Sienna_Cichlid trap handler support
- Replace SQC stores with TCP stores
- Synchronize with MSG_SAVEWAVE via lgkmcnt
- HW_REG_IB_STS is now read-only
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Tue, 1 Oct 2019 21:42:20 +0000 (17:42 -0400)]
drm/amdkfd: Support Sienna_Cichlid KFD v4
v4: drop get_tile_config, comment out other callbacks
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jerry (Fangzhi) Zuo [Mon, 20 Jan 2020 16:39:18 +0000 (11:39 -0500)]
drm/amdgpu/dc: Add missing Sienna_Cichlid chip id
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 3 Mar 2020 02:40:32 +0000 (10:40 +0800)]
drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 4 Mar 2020 08:40:24 +0000 (16:40 +0800)]
drm/amdgpu: fix SDMA hdp flush engine conflict
Each of HDP flush engine should be used by one ring, correct allocate of
hdp flush engine to SDMA ring.
Correct me value of each SDMA ring, as it was cleared when init microcode.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 18 Mar 2020 21:33:47 +0000 (17:33 -0400)]
drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid.
Enable mmhub clockgating.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 06:14:00 +0000 (14:14 +0800)]
drm/amd/amdgpu: add athub ls support
athub ls is bounded with hdp ls,verified.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 06:09:31 +0000 (14:09 +0800)]
drm/amd/amdgpu: add IH cg support
IH cg verified
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 03:57:04 +0000 (11:57 +0800)]
drm/amd/amdgpu: add HDP mgcg and ls support
add HDP mgcg and ls support and verified
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 03:57:04 +0000 (11:57 +0800)]
drm/amd/amdgpu: fix the HDP LS/DS/SD programming
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 14 Feb 2020 08:45:56 +0000 (16:45 +0800)]
drm/amdgpu: update golden setting for gfx10.3
Update gfx golden setting for gfx10.3.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 28 Jan 2020 17:21:52 +0000 (12:21 -0500)]
drm/amdgpu: set the LMI ctrl and reset earlier
So the LMI register will be programmed properly
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 28 Jan 2020 16:50:00 +0000 (11:50 -0500)]
drm/amdgpu: fix the PSP front door loading VCN firmware
for the second instance with correct index
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 20 Jan 2020 15:07:40 +0000 (10:07 -0500)]
drm/amdgpu: change the offset for VCN FW cache window
The signed header is added
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 23 Jan 2020 19:57:55 +0000 (03:57 +0800)]
drm/amdgpu: open GFX clock gating for sienna_cichlid
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 23 Jan 2020 16:14:32 +0000 (00:14 +0800)]
drm/amdgpu: switch to query reserved fb size from vbios (v3)
For Sienna_Cichlid, query fw_reserved_fb_size from vbios directly.
For navi1x, fall back to default 64K TMR size.
For pre-navi, no need to reserve tmr region in top LFB.
v2: fix TMR define (Alex)
v3: partially revert size change
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 22 Jan 2020 20:13:01 +0000 (04:13 +0800)]
drm/amdgpu: add atomfirmware helper funciton to query reserved fb size
fw_reserved_size_in_kb is introduced for driver to query
the TMR region reserved by PSP BL in Sienna_Cichlid and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 22 Jan 2020 20:08:59 +0000 (04:08 +0800)]
drm/amdgpu: add firmware_info v3_4 structure for Sienna_Cichlid
firmware_info v3_4 strucure will be used by kernel driver
to query various parameters set by VBIOS for Sienna_Cichlid
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 20 Jan 2020 19:22:32 +0000 (03:22 +0800)]
drm/amdgpu: only send one sdma firmware for sienna_cichlid
As all four sdma firmware are same, PSP only receive one SDMA fw.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 19 Jan 2020 21:16:41 +0000 (05:16 +0800)]
drm/amdgpu: drop gfx_v10_0_tiling_mode_table_init
tiling mode table is not used anymore for gfx10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 19 Jan 2020 20:46:33 +0000 (04:46 +0800)]
drm/amdgpu: support query vram info for sienna_cichlid
support query vram_module v11 and vram_info v2_5
for sienna_cichlid
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 19 Jan 2020 20:41:40 +0000 (04:41 +0800)]
drm/amdgpu: add vram_info v2_5 in atomfirmware header
vram_info v2_5 was introduced to support sienna_cichlid
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Sun, 19 Jan 2020 21:29:06 +0000 (05:29 +0800)]
drm/amdgpu: disable gfxoff for sienna_cichlid
Temporary disable gfxoff for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 16 Jan 2020 20:35:09 +0000 (04:35 +0800)]
drm/amdgpu: add cp firmware backdoor loading triger
Triger CP ucode addr and data to backdoor load CP firmware.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 16 Jan 2020 03:07:20 +0000 (11:07 +0800)]
drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 9 Apr 2020 18:19:48 +0000 (14:19 -0400)]
drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid
Add gc golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 24 Mar 2020 20:31:23 +0000 (16:31 -0400)]
drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid
By adding JPEG HW block to Sienna_Cichlid
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 3 Dec 2019 14:23:24 +0000 (09:23 -0500)]
drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid
By setting up the flags to the ASIC
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 29 Nov 2019 17:47:55 +0000 (11:47 -0600)]
drm/amdgpu: add Sienna_Cichlid JPEG PG and CG support
This is for static powergating and clockgating
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 15 Nov 2019 18:23:10 +0000 (13:23 -0500)]
drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 24 Mar 2020 20:30:24 +0000 (16:30 -0400)]
drm/amdgpu: enable VCN3.0 for Sienna_Cichlid
By adding VCN HW block to Sienna_Cichlid
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 27 Sep 2019 16:28:48 +0000 (11:28 -0500)]
drm/amdgpu: add Sienna_Cichlid VCN to the VCN family
By adding Sienna_Cichlid VCN firmware
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 3 Dec 2019 14:18:51 +0000 (09:18 -0500)]
drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid
By setting up the flags to the ASIC
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 27 Nov 2019 16:03:39 +0000 (11:03 -0500)]
drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2)
This is for static powergating and clockgating
v2: fix registers (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 15 Nov 2019 17:45:55 +0000 (12:45 -0500)]
drm/amdgpu: add VCN3.0 support for Sienna_Cichlid
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 20 Nov 2019 08:21:22 +0000 (16:21 +0800)]
drm/amdgpu/mes: correct register offset for sienna_cichlid
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 24 Oct 2019 04:03:08 +0000 (12:03 +0800)]
drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid
The number of queue per pipe for mec on sienna_cichlid should be 4.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 24 Mar 2020 20:28:43 +0000 (16:28 -0400)]
drm/amdgpu: add mes block to sienna_cichlid
Add mes block support to sienna_cichlid.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 03:48:48 +0000 (11:48 +0800)]
drm/amdgpu/mes10.1: update mes initialization
Update mes initialization sequence.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 21 Oct 2019 05:49:38 +0000 (13:49 +0800)]
drm/amdgpu: no need to set up GPU scheduler for mes ring
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 09:54:15 +0000 (17:54 +0800)]
drm/amdgpu/psp: convert amdgpu mes ucode type
Convert to psp defined ucode item, so that psp can recognize them.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 09:52:37 +0000 (17:52 +0800)]
drm/amdgpu: upload mes firmware to gpu buffer
Copy mes firmware to gpu buffer.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 09:46:24 +0000 (17:46 +0800)]
drm/amdgpu/mes10.1: copy mes fw info into global fw array
Copy mes firmware info into into global fw array, preparing
for fw front door loading.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 05:45:11 +0000 (13:45 +0800)]
drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support
Add sienna_cichlid mes firmware support.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 03:12:48 +0000 (11:12 +0800)]
drm/amdgpu/mes10.1: implement setting hardware resources
The routine is implemented to generate mes command to
assign the hardware resources which can be scheduled
to mes.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:21:01 +0000 (17:21 +0800)]
drm/amdgpu/mes10.1: implement querying the scheduler status
The routine is implemented to generate mes command
to query the status of hardware scheduler.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:07:42 +0000 (17:07 +0800)]
drm/amdgpu/mes10.1: implement removing hardware queue
The routine is implemented to generate mes command to remove
a specified hardware queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:05:49 +0000 (17:05 +0800)]
drm/amdgpu/mes10.1: implement adding hardware queue
The routine is implemented to generate mes command
to install a hardware queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 08:35:30 +0000 (16:35 +0800)]
drm/amdgpu/mes10.1: add the helper function for mes command submission
The helper function is used to submit mes command and poll waiting
for the command completion.
v2: replaced with amdgpu_fence_wait_polling to wait.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:02:45 +0000 (17:02 +0800)]
drm/amdgpu/mes10.1: add the mes fw api
Add the definitions of mes commands.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:44:04 +0000 (11:44 +0800)]
drm/amdgpu/mes10.1: enable the mes ring during initialization
Enable the mes ring during mes block initialization.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:39:54 +0000 (11:39 +0800)]
drm/amdgpu/mes10.1: install mes queue via kiq
Install mes queue via kiq. Disable it temporarily
until it's workable.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:11:00 +0000 (11:11 +0800)]
drm/amdgpu/mes10.1: install mes queue by register programming
Directly writing mes queue registers to set up it.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:27:10 +0000 (11:27 +0800)]
drm/amdgpu/mes10.1: initialize the mqd
Initialize the mqd according to mes ring setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 03:14:07 +0000 (11:14 +0800)]
drm/amdgpu/mes10.1: allocate mqd buffer
Allocate mqd buffer preparing for mes queue setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 5 Jun 2019 08:57:35 +0000 (16:57 +0800)]
drm/amdgpu/mes10.1: implement the ring functions of mes specific
Implement mes ring functions and set up them.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 26 Apr 2019 10:59:35 +0000 (18:59 +0800)]
drm/amdgpu/mes10.1: initialize the software part of mes ring
Do the software initialization on the mes ring.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 02:55:23 +0000 (10:55 +0800)]
drm/amdgpu/mes10.1: allocate the eop buffer
eop buffer will be used for mes queue setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 03:13:50 +0000 (11:13 +0800)]
drm/amdgpu/mes: update some mes definitions
Update some mes definitions.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 5 Jun 2019 08:30:13 +0000 (16:30 +0800)]
drm/amdgpu: avoid dereferencing a NULL pointer
Check if irq_src is NULL to avoid dereferencing a NULL pointer,
for MES ring is uneccessary to recieve an interrupt notification.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 9 Apr 2020 18:16:40 +0000 (14:16 -0400)]
drm/amdgpu: add the ring type definition of MES
Add a new ring type definition.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 26 Apr 2019 10:58:41 +0000 (18:58 +0800)]
drm/amdgpu: assign the doorbell index to mes ring
MES ring will use the assigned doorbell index for
command submission.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 10 Oct 2019 13:43:34 +0000 (09:43 -0400)]
drm/amdgpu: add 2rd VCN instance doorbell support
Sienna_Cichlid have 2 VCN instances, using different register for range
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 20:27:43 +0000 (16:27 -0400)]
drm/amdgpu: add psp block load condition for sienna_cichlid
Enable PSP block for firmware loading and other security
setup only when amdgpu use PSP load type to load ucode.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Sun, 29 Sep 2019 03:32:24 +0000 (11:32 +0800)]
drm/amdgpu: add gmc cg support for sienna_cichlid
Add gmc clockgating support for sienna_cichlid.
The athub version used for sienna_cichlid is v2.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 25 Sep 2019 08:44:46 +0000 (16:44 +0800)]
drm/amdgpu: add support for athub v2.1
Add athub v2.1 function and support to compile it.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Thu, 19 Sep 2019 22:01:06 +0000 (18:01 -0400)]
drm/amdgpu: Use variable instead of constant for sdma doorbell range
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 28 Aug 2019 09:52:54 +0000 (17:52 +0800)]
drm/amdgpu: update SDMA 5.2 microcode init
Removed loading duplicate instances of SDMA FW for Sienna_Cichlid,
As sienna_cichlid only use a single image for all instances.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 20:26:17 +0000 (16:26 -0400)]
drm/amdgpu: enable psp ip block for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 5 Aug 2019 07:32:40 +0000 (15:32 +0800)]
drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 22 Jul 2019 08:52:20 +0000 (16:52 +0800)]
drm/amdgpu/psp: add psp support for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 23 Apr 2020 20:05:21 +0000 (16:05 -0400)]
drm/amdgpu: skip ASD fw load for sienna_cichlid
Skip ASD FW load for sienna_cichlid currently.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 20:24:44 +0000 (16:24 -0400)]
drm/amdgpu/powerplay: add smu block for sienna_cichlid
Add SMU block for sienna_cichlid with psp load type.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 13 Mar 2020 09:51:13 +0000 (17:51 +0800)]
drm/amd/powerplay: enable PPT and TDC for sienna_cichlid
Enable PPT and TDC for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 13 Mar 2020 08:36:08 +0000 (16:36 +0800)]
drm/amd/powerplay: support to get power index for sienna_cichlid
Add function to get smu power index for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 13 Mar 2020 05:06:49 +0000 (13:06 +0800)]
drm/amd/powerplay: enable Fan control for sienna_cichlid
Support for Advanced Fan Control (AFC+) for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 10 Mar 2020 09:15:56 +0000 (17:15 +0800)]
drm/amd/powerplay: enable GFX SS for sienna_cichlid
Enable Graphics Clock (GFXCLK) Spread Spectrum for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 10 Mar 2020 04:25:45 +0000 (12:25 +0800)]
drm/amd/powerplay: enable LCLK DPM for sienna_cichlid
Enable LCLK DPM for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 10 Mar 2020 04:22:34 +0000 (12:22 +0800)]
drm/amd/powerplay: support to print pcie levels for sienna_cichlid
Support to print PCIE clk levels for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 10 Mar 2020 03:51:49 +0000 (11:51 +0800)]
drm/amd/powerplay: support pcie value set and update for sienna_cichlid
Add support to set default pcie parameters for sienna_cichlid.
Add support to update pcie parameters for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 10 Mar 2020 03:22:07 +0000 (11:22 +0800)]
drm/amd/powerplay: enable DCEFCLK DPM and DS for sienna_cichlid
Enable Display Clocks Dynamic Power Management (DPM) for sienna_cichlid.
Enable Display Controller Engine Fabric Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 6 Mar 2020 09:01:22 +0000 (17:01 +0800)]
drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid
Enable FW DSTATE for sienna_cichlid.
Enable DF CSTATE for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 27 Feb 2020 03:30:14 +0000 (11:30 +0800)]
drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid
Make GFX deep sleep can be configure for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 3 Mar 2020 06:40:16 +0000 (14:40 +0800)]
drm/amdgpu/powerplay: set UCLK DPM for sienna_cichlid
Enable uclk dpm for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 26 Feb 2020 11:13:29 +0000 (19:13 +0800)]
drm/amdgpu/powerplay: set Thermal control for sienna_cichlid
Enable Auto Thermal Throttling for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 18 Mar 2020 21:00:27 +0000 (17:00 -0400)]
drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlid
Enable System On Chip Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 24 Feb 2020 03:31:13 +0000 (11:31 +0800)]
drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid
Enable Graphics Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 19 Feb 2020 08:39:04 +0000 (16:39 +0800)]
drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid
Support Ultra Low Voltage for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 14 Feb 2020 03:12:34 +0000 (11:12 +0800)]
drm/amd/powerplay: set FCLK DPM for sienna_cichlid
Support for FCLK DPM for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 4 Feb 2020 05:58:58 +0000 (13:58 +0800)]
drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid
Support for SOCCLK DPM for sienna_cichlid.
Use feature mask to control DPM for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 13 Feb 2020 04:05:36 +0000 (12:05 +0800)]
drm/amd/powerplay: add support to set performance level for sienna_cichlid
Support for performance level set for sienna_cichlid.
Set standard performance level not fully support, will set to auto
performance level.
Set peak performance level not fully support, will do nothing with it.
Force clk level only support for 2 level for fine grained DPM.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 29 May 2020 18:33:08 +0000 (14:33 -0400)]
drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)
SMU11 based similar to navi1x.
v2: squash in SMU IF updates
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 14 Aug 2019 09:39:03 +0000 (17:39 +0800)]
drm/amdgpu: add virtual display support for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 29 May 2020 22:02:26 +0000 (18:02 -0400)]
drm/amdgpu/gfx10: change register configure for sienna_cichlid
Update sienna_cichlid register configuration for sienna_cichlid
to match the update of header files.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 23 Aug 2019 06:35:45 +0000 (14:35 +0800)]
drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 17 Jun 2019 05:38:29 +0000 (13:38 +0800)]
drm/amdgpu: add sdma ip block for sienna_cichlid (v5)
Sienna_Cichlid have 4 sdma controllers.
v2: add missing license to sdma_common.h (Alex)
v3: rebase (Alex)
v4: squash in policy fix (Alex)
v4: squash in fw_name fix
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 17 Jun 2019 05:14:58 +0000 (13:14 +0800)]
drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)
Add irq src headers for additional SDMA blocks.
v2: Add missing licenses (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 1 May 2020 14:21:23 +0000 (10:21 -0400)]
drm/amdgpu: add gfx ip block for sienna_cichlid (v3)
Add support for GC 10.3.
v2: Squash in gb_addr_config fix (Alex)
v3: Add num_pkrs support (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Sun, 16 Jun 2019 14:37:56 +0000 (22:37 +0800)]
drm/amdgpu: add ih ip block for sienna_cichlid
Update IH handling for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / platform / kernel / linux-rpi.git / log