zink: move v3dv scalarBlockLayout workaround

this isn't actually device-level workaround, it's just error suppression

fixes #9895

Fixes: 2978b85789c ("zink: don't warn about missing scalarBlockLayout on v3dv")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25456>

zink: move push descriptor disable to driver workarounds

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25456>

zink: fix crashing in image rebinds

this is invalid for buffer textures

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25379>

radv/video: find SPS with pps_seq_parameter_set_id

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25490>

zink/ci: bump zink-anv-tgl-full timeout to 1h45m

It can timeout otherwise. Might be due to recent uprev CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

zink/ci: update list of expectations for zink-anv-tgl

See https://gitlab.freedesktop.org/mesa/mesa/-/pipelines/995410.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/crocus: Add a related flake to a known one.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/docker: Clear the results file before starting a new deqp test run.

crocus-hsw was failing because results.csv.zst was left around in the
results dir, and then zstd -o complained.  We shouldn't be uploading stale
results files, anyway, so do an rm -rf first to clean up when the docker
container gets reused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/zink: Skip more doubles tests on anv that flake at 3 minute timeouts.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/etnaviv: Skip a GLES2 test that times out the asan job.

We could make asan use a toml setup that just skipped this for asan, but
this is quick and easy and I don't think there's too much risk here.  This
would make every asan job I've looked at in the nightlies pass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/etnaviv: Minor xfail/flake polishing.

Now that the regular piglit GPU hangs are sorted, we can get some more signal.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/anv: Drop the 16bit.scalar.13 skip.

It's now at 1.5 sec on my ADL and CFL systems.

Closes: #4641
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

ci/anv: Drop incorrect xfail addition for TGL

This xfails file is for deqp-vk.  The xfail that was added was for
angle-on-anv, which has its own expectations files and has this test
recently listed as a flake already.

Fixes: a217c5c58c53 ("ci: update to vulkan-cts-1.3.6.3")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25509>

copyimage: check requested slice early when cube maps are involved

The generalized check for the z-slice happens in 'check_region_bounds',
but this function requires the image pointer that is acquired in
`prepare_target_err`, therefore replace the assertion with a proper test.

v2: Also check for negative value (Brian Paul)

CC: mesa-stable
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25507>

anv: Add support for a transfer queue on Alchemist

Alchemist has an improved blitter that's sufficiently powerful to
implement a transfer queue. Tigerlake's blitter lacks compression
handling and other features we need, unfortunately.

Rework (Sagar):
- Check blitter command buffer in EndCommandBuffer

v2: (Lionel)
- Look at image, buffer and memory barriers as well
- Flush cache if there is queue ownership transfer

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18325>

anv: Handle end of pipe with MI_FLUSH_DW on transfer queue

Blitter command streamer supports MI_FLUSH_DW command so make sure we
don't end up emitting pipe control with CS stall and also handle the end
of pipe timestamp with MI_FLUSH_DW command.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18325>

ci: Compile Turnip's virtio kmd in debian-arm64

Nothing compiled virtio kmd in CI.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25531>

tu/virtio: Fix incorrect call to tu_perfetto_submit

Virtio backend backend was not updated because it was not
compiled in CI and not compiled locally.

Fixes: 7f59e3723380e7ed72588040e4f496733ac5ec83
("tu/perfetto: Allow gpu time to be passed into tu_perfetto_submit")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25531>

tu/a7xx: Correctly record timestamps for u_trace

It was changed how CP_EVENT_WRITE works on A7XX.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25528>

freedreno: Add attach-bo debugging

Add asserts to verify that BOs referenced in cmdstream are attached to
the submit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Move/add some attach_bo()

In some cases we were missing this, in others we just needed to move it
before the OUT_RELOC().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Add missing indirect_draw_count tracking

Fixes: f677f64e80c4 ("freedreno: implement GL_ARB_indirect_parameters")
Fixes: b43e5aec0d2c ("freedreno/batch: Move submit bo tracking to batch")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Add private-BO tracking

There are some internally used buffers that we should just attach to
every submit up-front.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno/batch: Move query_buf allocation

This lets us move fd_batch_update_queries() after resource tracking.
Which will become needed in the next patch which adds validation to
assert needed BOs are attached to the submit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Fix user const buffer dirtiness

If we went the upload_user_buffer() path, cb->buffer would be null,
causing fd_dirty_shader_resource() to be a no-op.  What we want to
use is &so->cb[index].

Fixes: b43e5aec0d2c ("freedreno/batch: Move submit bo tracking to batch")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Fix streamout offset_buf dirtiness

We also need to mark the offset buffer as dirty.

Fixes: b43e5aec0d2c ("freedreno/batch: Move submit bo tracking to batch")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno/a6xx: Remove dummy packet for globals

Unneeded since commit b43e5aec0d2c ("freedreno/batch: Move submit bo
tracking to batch")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Use explicit QCOM_TILED3 modifier

Now that this is in upstream drm_fourcc.h we can drop the private
internal modifier.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

freedreno: Indentation fix

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25465>

tu/kgsl: Support u_trace and perfetto

Raw GPU time is retrieved via kgsl_cmdbatch_profiling_buffer,
offseted GPU time is retrieved via KGSL_PERFCOUNTER_GROUP_ALWAYSON.
This allows to calculate GPU time offset for each submission and
synchronize CPU/GPU time domains.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12805>

tu/kgsl: Fix memory leak of tmp allocations during submissions

cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12805>

tu/perfetto: Allow gpu time to be passed into tu_perfetto_submit

In preparation to support perfetto on KGSL, on KGSL GPU time is
retrieved on submission and requires minimal post-processing.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12805>

tu/perfetto: Remove now unnecessary tu_perfetto_util

Since Turnip now uses C++ we can directly include tu_device.h
into perfetto code.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12805>

nir/lower_subgroups: use intrinsic builder more

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25501>

nir: make quad intrinsic dst bit size match src0

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25501>

isaspec: Add BitSetEnumValue object

There might be cases where you describe an enum in isaspec and want it to use
for decoding but also for codegen with e.g. mako.

Lets have a look at the following exmaple:

<enum name="#cond">
<value val="0" display=""/>    <!-- always: display nothing -->
<value val="1" display=".gt"/>
...
</enum>

In the decoding case we want that nothing gets displayed if #cond has the value of "0". For
codegen with mako this could result in the following C code:

enum PACKED cond {
   COND_ = 0,
   COND_GT = 1,
   ...
};

What you really want is this:

enum PACKED cond {
   COND_ALWAYS = 0,
   COND_GT = 1,
   ...
};

To make this possible introduce BitSetEnumValue class which represents
an isaspec xml enum. It holds the value, displayname and now a name.

With the  __str__ method the old behaviour is still intact.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25451>

isaspec: Add support for custom meta information

Allows every user of isaspec to add custom meta information
to any bitset. This can be quite handy if you want to know
how many sources your instruction have, if this instruction has
a dest or provide some names for sources that can be used
by some debug tools.

All you need is to sprinkle <meta> tags in the xml file and
provide custom attributes.
  <meta has_dest="1" num_sources="3" .. />

With get_meta() method of any bitset you can get access to
the dict with all the attributes. get_meta() walks the whole
tree to collect all <meta> tags on the way to the root node.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25451>

isaspec: Add method to get all instrustions

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25451>

isaspec: encode: Correct used regex

The current regex misses the = sign and therefore fails to match
DST:align=16.

Fixes: 9e56f69edf5 ("isaspec: encode: handle special fieldname properties")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25451>

isaspec: Add support for templates

If you have a repeating <display> substring you can replace this
substring with a template and reference the template name instead.

Saves from doing lot of copy&paste and makes general changes to the
substring much easier.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25451>

v3dv/ci: update expected list

Remove dEQP-VK.api.driver_properties.conformance_version, as the version
it required is now the one used in the CI.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25518>

radv: enable DCC for MSAA images on GFX11

This seems to be working now! I suspect either the "recent" addrlib
update fixed it or recent comp-to-single fast clear fixes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8326
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25448>

tu: add a TU_DEBUG=rd option for cmdstream dumping

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25246>

freedreno: move redump.h to common code + cleanup

remove the unused parts and add an implementation of rd_write_section

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25246>

Revert "ci: disable Collabora's LAVA lab for maintance"

This reverts commit https://gitlab.freedesktop.org/mesa/mesa/-/commit/ccd3e68146fd7ee8732d497f367a0574e4cf84a8

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25369>

isl: Use 16-bit instead of 8-bits for surface format info fields

Comparing uint8_t max value 255 with devinfo->verx10 will work fine for
now but for future platforms, comparison will fail. To avoid this
let's switch the field data type from 8-bits to 16-bits.

v1: (Jordan)
- Use 16 bits instead of 32 and add assertion.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25478>

radv/amdgpu: fix alignment of command buffers

Fixes other recent regressions.

Fixes: 4f660f99 ("ac/gpu_info: pad IBs according to ib_size_alignment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25502>

ci: make B2C_JOB_VOLUME_EXCLUSIONS to all .b2c-test jobs

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25429>

aco: remove -0.0 for 32 bit fsign with mul_legacy/omod when denorms are flushed

v_mul_legacy_f32 and omod return +0.0 if any operand is +0.0/-0.0.

Foz-DB Navi21:
Totals from 4289 (5.60% of 76572) affected shaders:
Instrs: 8100571 -> 8099319 (-0.02%); split: -0.02%, +0.00%
CodeSize: 43433200 -> 43435088 (+0.00%); split: -0.01%, +0.01%
Latency: 88151566 -> 88147232 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 22966705 -> 22965192 (-0.01%); split: -0.01%, +0.00%
VClause: 190010 -> 190009 (-0.00%)
SClause: 269697 -> 269689 (-0.00%)
Copies: 687294 -> 687296 (+0.00%); split: -0.00%, +0.00%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25347>

aco/optimizer: copy propagate to output modifier instructions

Foz-DB Navi21:
Totals from 847 (1.11% of 76572) affected shaders:
Instrs: 2331245 -> 2330335 (-0.04%); split: -0.04%, +0.00%
CodeSize: 12451040 -> 12451736 (+0.01%); split: -0.00%, +0.01%
Latency: 26230953 -> 26229153 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 6297802 -> 6296788 (-0.02%); split: -0.02%, +0.00%
VClause: 64527 -> 64528 (+0.00%); split: -0.00%, +0.01%
SClause: 73150 -> 73121 (-0.04%); split: -0.06%, +0.02%
Copies: 180083 -> 179172 (-0.51%); split: -0.53%, +0.02%
PreSGPRs: 62311 -> 62316 (+0.01%)
PreVGPRs: 51720 -> 51710 (-0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25347>

aco/optimizer: check if we can use omod before labeling it

Allows to use omod for v_mul_legacy_f32 regardless of signedZeroInfNaNPreserve

Foz-DB Navi21:
Totals from 15 (0.02% of 76572) affected shaders:
Instrs: 20131 -> 20113 (-0.09%)
CodeSize: 107100 -> 107144 (+0.04%)
Latency: 400789 -> 400470 (-0.08%)
InvThroughput: 62342 -> 62278 (-0.10%)
Copies: 1194 -> 1176 (-1.51%)
PreVGPRs: 787 -> 785 (-0.25%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25347>

radv/ci: update list of flakes for NAVI10/VEGA10

This one is fixed since CTS 1.3.6.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25505>

radv/ci: update list of expected failures on PITCAIRN

This one is fixed since CTS 1.3.6.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25505>

radv: fix alignment of DGC command buffers

Otherwise, DGC command buffers might not be correctly aligned.

This fixes a regression with the vkd3d-proton DGC tests.

Fixes: 4f660f99378 ("ac/gpu_info: pad IBs according to ib_size_alignment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25500>

intel/genxml: remove HDC from gen11.xml, it is not available

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>

iris: HDC flush is available only for GFX_VER 12+

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>

anv: HDC flush is available only for GFX_VER 12+

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>

iris: flush data cache when flushing HDC on GFX < 12

This matches what anv driver does.

Fixes: a969ad1d ("iris: Demote DC flush to HDC flush in cache tracker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6314
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>

aco: remove zero offset optimization

This is done in nir_opt_constant_folding now.

No fossil-db changes on navi31.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25477>

nir/constant_folding: remove zero texel offset

fossil-db (navi31):
Totals from 7 (0.01% of 79330) affected shaders:
Instrs: 7001 -> 6993 (-0.11%)
CodeSize: 35736 -> 35692 (-0.12%)
InvThroughput: 3232 -> 3229 (-0.09%)
Copies: 552 -> 549 (-0.54%)
PreSGPRs: 277 -> 273 (-1.44%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25477>

aco: disable zero offset optimization for strict WQM coords

If we try to do this, we end up using {undef,coordx} as the coordinates
for an image_sample instruction, because we can't shrink the linear VGPR.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9767
Fixes: 859e059aa912 ("radv: use fix_derivs_in_divergent_cf")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25477>

nir: scalarize masked_swizzle_amd created from shuffle_xor

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9901
Fixes: 0ef87f148df ("nir/lower_subgroups: Don't do multiple lowerings at once")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25468>

iris/anv: move Wa_14018912822 as a drirc workaround

This should be toggled on only for applications that hit the issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9886
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25424>

iris: correct dst alpha blend factor in Wa_14018912822

Fixes: 0e9a26372bb4 ("iris: implement Wa_14018912822")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25424>

anv: fix internal compute copy shader build

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9907
Fixes: 2cc5b3b1e0 ("anv: add a memcpy compute internal kernel")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25480>

docs: Move isaspec out of drivers/freedreno

Lets put it under 'Developer Topics'.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25452>

v3d: get rid of shader_state pointer in v3d_key

Having this pointer in the key is undesirable since it makes
copying keys difficult and error prone (as seen in previous
patches), also, it is only there for convenience and we don't
strictly need it (in fact the vulkan driver doesn't use it at
all), so let's just get rid of it so our v3d_key is fully
static.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>

v3d: fix RAM shader cache

The RAM shader cache was using the v3d_key for hashes and
comparisons which is not correct. Particularly, this struct
has a void pointer where we store a reference to an uncompiled
shader with the NIR code, and that is of course not accounted
for when hashing and comparing keys, which can lead to bogus
cache hits.

This patch introduces a v3d_cache_key that has both the v3d key
and a sha1 of the uncompiled NIR. Now key hashing and comparison
is done on the static part of the v3d key (that is, excluding the
uncompiled shader pointer, which may be invalid in the cache if
the original shader was deleted) and taking the sha1 from the
uncompiled shader. This also makes sure the shader key we store
in the cache has a NULL shader_state pointer to make it more
clear that this field may not be used at all for caching purposes.

This fixes GPU hangs with some OpenCL tests (through Rusticl)
caused by incorrect RAM cache hits.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>

v3d: use pre-computed shader sha1 for disk cache

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>

v3d: compute nir sha1 for uncompiled shader state

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>

broadcom/compiler: add a couple of shader key helpers

Our shader key includes a void pointer that we can't just memcmp,
so add helpers that allow us toget the 'static' portion and size
of a key. We will use this to fix up the shader cache in v3d in
a later patch.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>

ci: disable Collabora's LAVA lab for maintance

This is to inform you of some planned downtime in the LAVA lab as follows:
* Start: 2023-10-02 08:00 BST (07:00 UTC)
* End: 2023-10-02 12:00 BST (11:00 UTC)

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25368>

ci/vkcts-navi21: mark more of the RT handles checks as flakes

We keep hitting more and more of them, so let's be more inclusive.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25495>

ci/vkcts-vangogh: mark dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.* as flake

This mirrors what we did on navi21, as there are just too many of these tests.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25495>

asahi: decode: Fix uint64_t format modifiers in agxdecode_stateful()

Fixes i386 build.

Fixes: acd5ed0451d6 ("asahi: decode: Implement VDM call/ret")
Signed-off-by: Janne Grunau <j@jannau.net>

asahi: Handle layered background programs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Generate layered EOT programs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Use a 2D Array texture for array render targets

Fixes KHR-GLES31.core.geometry_shader.layered_framebuffer.blending_support with
eMRT forced.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Write to cubes/etc attachments as 2D array

To reduce shader variants, the tilebuffer lowering code does not know the
actual texture targets of the spilled render targets, only whether they are
layered or not. As such, all layered targets (3D, cube map, etc) get written out
uniformly as 2D Arrays. For that to work, the driver needs to do the
corresponding transform.

Regular imageStore() instructions are not affected by any of this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Predicate layer ID reads

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Add pass to predicate layer ID reads

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Assume LAYER is flat-shaded

It can't be anything else, this makes sure the varyings are sorted properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Account for layering for attachment views

Do not force a single-layer view, use an actual array attachment when there are
multiple layers, since this corresponds to a layered framebuffer that will write
to an array with the eMRT path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Expose VS_LAYER_VIEWPORT behind a flag

We can't technically expose the extension without a higher GL version, but the
implemented subset should work and this lets us test with piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Use layered layouts

For correct eMRT code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx/lower_tilebuffer: Support spilled layered RTs

If we spill render targets with a layered framebuffer, our spilled targets are
assumed to be 2D Arrays (in general). We need to use arrayed image operations to
load/store from these. The layer is given by the layer as read in the fragemnt
shader. This handles the eMRT portion of layered rendering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx/tilebuffer: Support layered layouts

Just add a flag for it. We don't care about the actual # of layers when
calculating the layout, only the boolean fact of being layered or not. The
reason we need this at all is because the eMRT implementation needs to
account for layering and that is only keyed off the tilebuffer layout.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Support packed layered rendering writes

With the new pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi,agx: Select layered rendering outputs

These 2 are together

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

asahi: Add helper to get layer id in internal program

For background/EOT only.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Add pass to lower layer ID writes

The hardware needs the layer ID and the viewport index packed together. That
consumes an entire varying slot, if we want those available in the frag shader
we need a separate slot. Add a pass to insert the extra packed write.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Handle layered block image stores

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Pack block image store dim correctly

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx/nir_lower_texture: Allow disabling layer clamping

For background program with layered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

nir: Support arrays in block_image_store_agx

For layered rendering, runs once per layer.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

nir: Add layer_id_written_agx sysval

We'll implement layer ID reads in the frag shader with a varying read, but if
the VS doesn't write the varying we need to return 0 per the spec. Add a sysval
to detect that case so we can handle it at runtime without keys.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Insert jmp_exec_none instructions

With the exception of the backwards branch for loops, all the control flow we
insert during instruction selection just predicates instructions rather than
actually jumping around. That means, for example, we execute both sides of the
if even for a uniform condition! That's inefficient. The solution is insert
jmp_exec_none instructions after control flow in order to skip unexecuted
regions, which is much faster than predicating them out. However, jmp_exec_none
is costly in itself, so we need to use a heuristic to determine when it's
actually beneficial.

This uses a very simple heuristic for this purpose. However, it is a massive
performance speed-up for Dolphin uber shaders: 39fps -> 67fps at 2x resolution.
Nearly a doubling of performance!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Add agx_prev_block helper

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Add jumps to block ends

jmp_exec_none variant that jumps to the last instruction of the target block,
rather than the beginning. This is convenient for skipping over elses, while
still executing the block-final pop_exec instruction. Similarly for skipping
over loop bodies while still executing the block-final pop_exec, after break
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

agx: Augment if/else/while_cmp with a target

Add an optional pointer to a target block for these instructions. This does NOT
act like a logical branch, and does NOT get added to the logical control flow.
It is ignored wholesale until after RA, when physical edges may be inserted by a
pass we add later in this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>