Faith Ekstrand [Wed, 27 Sep 2023 17:45:39 +0000 (12:45 -0500)]
nvk: Store a 20-bit driver_build_sha in nvk_instance
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
Timothy Arceri [Tue, 26 Sep 2023 04:47:50 +0000 (14:47 +1000)]
nir: fix typo in comment
The variable is unused or dead, not used.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25414>
antonino [Thu, 17 Aug 2023 13:09:15 +0000 (15:09 +0200)]
vulkan: Handle vkSetDebugUtilsObjectNameEXT on WSI objects
Some WSI objects don't extend `vk_object_base` therefore they need
special handling.
Fixes:
3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
antonino [Thu, 17 Aug 2023 13:07:04 +0000 (15:07 +0200)]
vulkan: Extend vkGet/SetPrivateDataEXT handling to VkSurface
VkSurface is handled by WSI and it doesn't extend `vk_object_base` so it
needs special handling.
Fixes:
3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
antonino [Thu, 17 Aug 2023 13:06:18 +0000 (15:06 +0200)]
vulkan: Extend vkGet/SetPrivateDataEXT handling to all platforms
Non-android platforms use mesa WSI, however some WSI object still don't
extend `vk_object_base` so they still need special handling.
Fixes:
3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
Dave Airlie [Wed, 27 Sep 2023 05:30:05 +0000 (15:30 +1000)]
llvmpipe/cs: migrate cs image handle to common jit code.
This moves some of the code over, and uses the generic paths.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
Dave Airlie [Wed, 27 Sep 2023 05:26:47 +0000 (15:26 +1000)]
llvmpipe/cs: migrate to generic jit texture from pipe code.
This moves some cs specific bits to the generic code and uses it.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
Marcin Ślusarz [Mon, 20 Mar 2023 10:32:07 +0000 (11:32 +0100)]
intel/compiler: mask GS URB handles at thread payload construction
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Wed, 1 Feb 2023 13:56:56 +0000 (14:56 +0100)]
intel/compiler/mesh: implement IO for xe2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Wed, 1 Feb 2023 13:40:59 +0000 (14:40 +0100)]
intel/compiler/mesh: fix position of output URB handle for xe2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Thu, 29 Sep 2022 00:07:32 +0000 (17:07 -0700)]
intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB reads.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Wed, 28 Sep 2022 23:50:41 +0000 (16:50 -0700)]
intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB writes.
Rework:
* Marcin: update emit_urb_indirect_vec4_write
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Wed, 28 Sep 2022 23:38:35 +0000 (16:38 -0700)]
intel/fs: Specify number of data components of logical URB writes via control immediate.
This is what most logical SEND messages do when they take a variable
number of components. 'inst->mlen' is expected to be zero for logical
SEND opcodes, which are expected to behave like plain arithmetic
operations, so certain automated transformations (like SIMD lowering)
can manipulate them without opcode-specific special-casing.
Guessing the number of components from 'inst->mlen' has other
disadvantages, because it requires duplicating the logic that infers
the message payload size in every use of the instruction -- Instead we
can just do the computation once during logical send lowering. In
addition on LNL platform this causes the 'inst->mlen' field of URB
writes to have units inconsistent with every other SEND instruction,
which is likely to lead to confusion and bugs down the road.
Rework:
* Marcin: update emit_urb_indirect_vec4_write
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Thu, 29 Sep 2022 00:10:25 +0000 (17:10 -0700)]
intel/fs/xe2+: Fix URB writes with 0 data components.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Caio Oliveira [Thu, 8 Sep 2022 03:37:26 +0000 (20:37 -0700)]
intel/compiler/xe2: Update TCS ICP handle code to support SIMD16
Rework:
* Use ffs(grf_size_bytes) (s-b Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Caio Oliveira [Wed, 7 Sep 2022 07:21:20 +0000 (00:21 -0700)]
intel/compiler/xe2: Fix URB writes in TCS
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Caio Oliveira [Sat, 27 Aug 2022 02:02:16 +0000 (19:02 -0700)]
intel/compiler/xe2: URB fence uses LSC now
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Ian Romanick [Fri, 29 Jul 2022 00:44:06 +0000 (17:44 -0700)]
intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8
v2: Account for 512b physical registers which causes the URB handle to be in FIXED_GFR 2 instead of 1.
XXX - Use fs_builder::vgrf() instead of open-coded dispatch_width calculations.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Kenneth Graunke [Thu, 8 Sep 2022 00:48:07 +0000 (17:48 -0700)]
intel/fs: Fix Xe2 URB read/lowering with per-slot offsets
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Fri, 5 Aug 2022 21:58:09 +0000 (14:58 -0700)]
intel/compiler: Use enum xe2_lsc_cache_load on xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Fri, 5 Aug 2022 21:31:10 +0000 (14:31 -0700)]
intel/compiler: Add enum xe2_lsc_cache_load
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Thu, 8 Sep 2022 00:39:31 +0000 (17:39 -0700)]
intel/compiler: Use enum xe2_lsc_cache_store on xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Fri, 5 Aug 2022 21:18:43 +0000 (14:18 -0700)]
intel/compiler: Add enum xe2_lsc_cache_store
Rework:
* Rohan: Fix enum value for L1WB_L3WB
* Fix write-through comments (Ken)
Ref: bspec 71167
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Fri, 12 Aug 2022 14:02:50 +0000 (16:02 +0200)]
intel/compiler: add initial support for URB_LOGICAL_SRC_CHANNEL_MASK to lower_urb_write_logical_send_xe2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Fri, 12 Aug 2022 14:00:38 +0000 (16:00 +0200)]
intel/compiler: add lsc_msg_desc_wcmask
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Ian Romanick [Wed, 20 Jul 2022 17:21:21 +0000 (10:21 -0700)]
intel/compiler/xe2: Handle new URB write messages
Rework:
* idr v1: Fix compilation error.
* idr v2: Add support for per-channel offsets.
* idr v3: get_lowered_simd_width is 16 on Xe2+.
* idr v4: Add disassembly support. Add validation support.
* Sqaushed in changes Marcin Ślusarz's patches:
* "intel/compiler: skip adding 0 to payload address"
* "intel/compiler/xe2: drop masking off top 8 bits of URB handle"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Ian Romanick [Mon, 25 Jul 2022 17:03:39 +0000 (10:03 -0700)]
intel/compiler/xe2: Handle new URB read messages
Rework:
* Sqaushed in changes Marcin Ślusarz's patches:
* "intel/compiler: skip adding 0 to payload address"
* "intel/compiler/xe2: drop masking off top 8 bits of URB handle"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Konstantin Seurer [Fri, 18 Aug 2023 10:44:57 +0000 (12:44 +0200)]
vulkan: Remove vk_get_physical_device_core_1_*_feature_ext
It's unused.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>
Konstantin Seurer [Wed, 13 Sep 2023 15:07:32 +0000 (17:07 +0200)]
hasvk: Use the common GetPhysicalDeviceFeatures2 implementation
Reviewed-by: Julia Tatz <tatz.j@northeastern.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>
Rhys Perry [Tue, 26 Sep 2023 18:36:21 +0000 (19:36 +0100)]
nir/algebraic: optimize u2u32(a >> 32)
fossil-db (navi21):
Totals from 352 (0.44% of 79330) affected shaders:
Instrs: 271816 -> 271240 (-0.21%); split: -0.28%, +0.07%
CodeSize: 1546520 -> 1544448 (-0.13%); split: -0.23%, +0.09%
SpillVGPRs: 832 -> 827 (-0.60%); split: -1.08%, +0.48%
Latency: 4037120 -> 4021748 (-0.38%); split: -0.41%, +0.03%
InvThroughput: 1369540 -> 1362066 (-0.55%); split: -0.59%, +0.04%
VClause: 6476 -> 6471 (-0.08%); split: -0.12%, +0.05%
SClause: 6798 -> 6794 (-0.06%)
Copies: 44828 -> 44630 (-0.44%); split: -0.89%, +0.45%
Branches: 8845 -> 8844 (-0.01%); split: -0.05%, +0.03%
PreSGPRs: 14684 -> 14659 (-0.17%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>
Rhys Perry [Tue, 26 Sep 2023 18:29:37 +0000 (19:29 +0100)]
nir/lower_int64: fix find_lsb(0)
If the high 32 bits were zero, this would be umin(find_lsb(lo), 31). This
evaluates to 31 if lo is also zero, instead of -1.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes:
9293d8e64bc7 ("nir: Add find_lsb lowering to nir_lower_int64.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>
wangra [Wed, 27 Sep 2023 17:11:00 +0000 (13:11 -0400)]
tu/kgsl: Fix bitfield of DITHER_MODE_MRT6
The enum `adreno_rb_dither_mode` needs 2 bits, change the `high` to 13 to make sure 2 bits are used for `DITHER_MODE_MRT6`
Fixes:
e03259974e2f2c8e8c0295f8dab56d88e7bd896c ("freedreno: Generate headers from xml files")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25439>
Jordan Justen [Thu, 8 Sep 2022 08:37:04 +0000 (01:37 -0700)]
anv: Print warning that Xe2 is not supported rather than failing
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Wed, 29 Jun 2022 08:51:36 +0000 (01:51 -0700)]
anv: Build for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Wed, 6 Jul 2022 01:57:28 +0000 (18:57 -0700)]
anv: Disable Ray Tracing on xe2 until our compiler supports Xe2 RT
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Thu, 30 Jun 2022 00:34:44 +0000 (17:34 -0700)]
anv/blorp: Use anv_genX to set device->blorp.exec
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Wed, 29 Jun 2022 08:35:06 +0000 (01:35 -0700)]
iris: Build for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Lionel Landwerlin [Wed, 27 Sep 2023 12:42:32 +0000 (15:42 +0300)]
iris: add missing workaround for 3DSTATE_LINE_STIPPLE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>
Lionel Landwerlin [Wed, 27 Sep 2023 12:42:21 +0000 (15:42 +0300)]
anv: add missing workaround for 3DSTATE_LINE_STIPPLE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>
Lionel Landwerlin [Wed, 27 Sep 2023 12:53:25 +0000 (15:53 +0300)]
anv/iris: widen Wa_14015946265 to Gfx11+
We missed out that ICL+ added a programming requiring a CS_STALL.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25426>
Connor Abbott [Fri, 1 Sep 2023 17:10:56 +0000 (19:10 +0200)]
tu: Expose VK_KHR_maintenance5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Wed, 27 Sep 2023 09:03:39 +0000 (11:03 +0200)]
freedreno/ci: Skip dEQP-VK.info.device_extensions
Copied from anv and radv.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 17:10:39 +0000 (19:10 +0200)]
tu: Add maintenance5 properties
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 17:09:31 +0000 (19:09 +0200)]
tu: Check for DEVICE_LOST in vkGetEventStatus()
Required by maintenance5.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 14:07:30 +0000 (16:07 +0200)]
tu: Support VkPipelineCreateFlags2CreateInfoKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:46:37 +0000 (15:46 +0200)]
tu: Use new buffer usage flags
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:32:40 +0000 (15:32 +0200)]
tu: Implement vkGetRenderingAreaGranularityKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:31:57 +0000 (15:31 +0200)]
tu: Implement vkGetImageSubresourceLayout2KHR and vkGetDeviceImageSubresourceLayoutKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:31:08 +0000 (15:31 +0200)]
tu: Implement vkCmdBindIndexBuffer2KHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:30:11 +0000 (15:30 +0200)]
tu: Allow VK_WHOLE_SIZE in tu_CmdBindVertexBuffers2EXT pSizes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:28:27 +0000 (15:28 +0200)]
tu/clear_blit: Allow VK_REMAINING_ARRAY_LAYERS as layerCount
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:23:13 +0000 (15:23 +0200)]
tu/clear_blit: Fix staging image view layer count
This seems to be a mistake that didn't affect anything.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 12:22:18 +0000 (14:22 +0200)]
freedreno/fdl: Support PIPE_FORMAT_R5G5B5A1_UNORM on a6xx
This is just a different swap of the same format.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 17:08:57 +0000 (19:08 +0200)]
tu: Support clearing A8_UNORM
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 12:20:19 +0000 (14:20 +0200)]
freedreno/fdl: Use A8_UNORM HW format for sampling
We've already been using this for 3d blits on turnip and it works fine.
There's no need to emulate it, and it won't work on turnip where we
can't swizzle the border colors.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Wed, 27 Sep 2023 12:17:19 +0000 (14:17 +0200)]
zink: Rework color clamping and conversion
Before this commit, zink_format_clamp_channel_color() ignored the format
swizzle, so it was assuming that for emulated formats like alpha,
alpha-luminance etc. that the color had already been swizzled to match
the internal format rather than the emulated one. It's somewhat confusing
that passing in e.g. A8_UNORM actually means R8_UNORM, and led to a bug
when using VK_FORMAT_A8_UNORM for texture border colors because we
didn't swizzle it back. It also wouldn't have worked for media formats
like R10X6G10X6 due to the void channel in the middle.
In order to fix this, we need to untangle the mess in its users.
For convert_color() used when clearing, this means we now need to clamp
and then swizzle instead of swizzle and then clamp, and we can drop the
hack for A8_UNORM.
For texture border colors, the state tracker duplicates colors for the
emulated formats to help drivers, which zink was previously relying on,
but fixing zink_format_clamp_channel_color() breaks this because it
assumes that those duplicated colors are useless and clamps them.
However, because we know the format we can just swizzle the border color
ourself, which convert_color() was already doing. So, we pull that out
into a common zink_convert_color() function that handles both clamping
and format emulation, and have both clearing and border color handling
use it.
This fixes A8_UNORM in turnip+zink once we enable it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Erico Nunes [Wed, 20 Sep 2023 20:06:39 +0000 (22:06 +0200)]
v3dv: allow headless device without display device
When trying to create a headless Vulkan instance without a display
device available, device enumeration would fail.
Part of the physical device creation code already accounts for a missing
display device, allow device enumeration to continue in that case too so
headless instances can be created.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25313>
Matt Coster [Wed, 20 Sep 2023 15:00:19 +0000 (16:00 +0100)]
pvr: Force compile error on GNU void pointer arithmetic
This GNU extension caused a bug where a void pointer was modified then
interpreted as uint32_t* (instead of the other way round). Force a
compile error to (hopefully) prevent this from happening again.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25327>
Matt Coster [Wed, 20 Sep 2023 15:34:43 +0000 (16:34 +0100)]
pvr: Don't rely on GNU void pointer arithmetic
Besides being not standard C, one instance (in pvr_cmd_buffer.c) was a
bug caused by adding-then-casting, which would likely have been caught
if void pointer arithmetic were not allowed.
All instances detected by -Wpointer-arith have been fixed here.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25327>
Georg Lehmann [Tue, 26 Sep 2023 16:29:31 +0000 (18:29 +0200)]
aco: implement 64bit div find_lsb
This can be selected for divergent subgroupBallotFindLSB.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25407>
Georg Lehmann [Tue, 26 Sep 2023 15:13:12 +0000 (17:13 +0200)]
aco: fix p_extract with v1 dst and s1 operand
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
f14023666ca ("aco: Allow p_extract to have different definition and operand sizes.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25403>
Rhys Perry [Mon, 25 Sep 2023 11:29:26 +0000 (12:29 +0100)]
aco/waitcnt: add print helpers
These may be useful in the future.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25373>
Rhys Perry [Mon, 25 Sep 2023 11:22:05 +0000 (12:22 +0100)]
aco/waitcnt: replace wait_cnt::*_cnt with booleans
Previously, a loop could be revisited until a counter reaches it's
maximum:
loop {
store()
}
Each visit of that loop would increase vs_cnt until it reaches max.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25373>
Karol Herbst [Tue, 19 Sep 2023 12:44:26 +0000 (14:44 +0200)]
zink: lower vec8/16
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25330>
Karol Herbst [Thu, 21 Sep 2023 12:03:55 +0000 (14:03 +0200)]
nir: add nir_lower_alu_vec8_16_srcs pass
This pass is useful for vector based backends as we might end up with alu
instructions referencing vec8/vec16 values even though being vec4 or
smaller themselves.
This new pass intents to clean up any use of vec8/vec16 sources other
passes won't.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25330>
Jose Maria Casanova Crespo [Mon, 25 Sep 2023 19:16:59 +0000 (21:16 +0200)]
vc4: Fix mask RGBA validation at YUV blit
Solves regression on video players using GPU for
video decoding that just displays the video in green.
Fixes:
d13da7782cd80 ("vc4: call blit paths in chain")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25412>
Eric Engestrom [Wed, 20 Sep 2023 15:05:39 +0000 (16:05 +0100)]
ci/docs: drop extra overwritten rules
Every job re-defines its own rules, so there is no point in including these here.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25307>
Tapani Pälli [Tue, 19 Sep 2023 17:18:58 +0000 (20:18 +0300)]
iris: use intel_needs_workaround for Wa_14014414195 part 2
Commit
3ec953ed755 left couple of extra things, these changes are
based on a patch from Francisco Jerez.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25306>
Caio Oliveira [Mon, 25 Sep 2023 04:38:47 +0000 (21:38 -0700)]
intel/compiler: Don't store stage name and abbrev
Those are used in the failure paths and are easily retriavable from the
stage itself, so no need to store them.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25367>
Dave Airlie [Tue, 26 Sep 2023 01:40:18 +0000 (11:40 +1000)]
llvmpipe: reset viewport_index_slot in fb bind
I hit a problem running a set of lvp caselists with
dEQP-VK.transform_feedback.simple.draw_indirect_endqueryindexed_streamid_0_16,Crash
This was crashing due to
assert(setup->viewport_index_slot < 0);
in try_update_scene_state
This was because a previous draw had set viewport index slot to 2,
but a clear then draw sequence never resets it, so the clear gets
a scene, and when the subsequent flush happens for that scene,
the viewport_index_slot is never updated. It only gets updated on
draws.
This just resets it as lp_setup_update_state will always pick up
the correct one for the next draw.
Cc: mesa-stable
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25387>
Karol Herbst [Sat, 23 Sep 2023 10:01:14 +0000 (12:01 +0200)]
rusticl/mesa/context: fix clear_sampler_views
Even though drivers are required by documentation to handle the samplers
being NULL, st/mesa changed enough so it always sets the pointer.
As being similiar to st/mesa is more important than following docs, we
simply mimic st/mesa here and meet the expectations of drivers.
In the future we want to track the set state similiar to st/mesa, so
`clear_sampler_views` will probably go away and we'll just update what
we'll need.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: @LingMan <18294-LingMan@users.noreply.gitlab.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25363>
Charmaine Lee [Wed, 7 Jun 2023 20:49:28 +0000 (23:49 +0300)]
svga: sync resource content from backing resource before image upload
When a backing resource is created for a render target view when the
same resource is currently bound to a shader resource view, the content
update back to the original resource happens when the associated render
target view is unbound. But state update only happens at clear or draw
time. So if TexSubImage happens after BindFrameBuffer and before Draw,
the original texture resource that is mapped to for subimage update
would not have been updated. As a matter of fact at the subsequent state
update at the next draw, the render target views will be updated, the
content from the previous backing resource will be propogated to the
original resource, hence overwriting the changes from the last TexSubImage.
To fix the problem, this patch validates the texture resource, updates
any pending changes from the backing resource before transfer map upload
occurs.
Fixes the rendering issue demonstrated from the fbo_texsubimage_update trace
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25386>
Italo Nicola [Tue, 26 Sep 2023 13:44:33 +0000 (13:44 +0000)]
panfrost: advertise YUV formats for valhall
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24479>
Italo Nicola [Tue, 26 Sep 2023 13:24:53 +0000 (13:24 +0000)]
panfrost: use centered YUV chroma siting
This is likely a more reasonable default than co-sited samples, and will be
needed for valhall.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24479>
Italo Nicola [Thu, 3 Aug 2023 13:50:16 +0000 (13:50 +0000)]
panfrost: prepare v9+ to support YUV sampling
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24479>
Italo Nicola [Thu, 3 Aug 2023 13:57:01 +0000 (13:57 +0000)]
panfrost: rename _needs_multiplanar_descriptor to _is_yuv
This is only really used to condition on YUV formats, even on v7, but
moreso now on v9+.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24479>
Italo Nicola [Thu, 3 Aug 2023 13:54:26 +0000 (13:54 +0000)]
pan/genxml: add Width/Height fields to v9+ Plane descriptor
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24479>
Dave Airlie [Tue, 26 Sep 2023 02:43:37 +0000 (12:43 +1000)]
llvmpipe/fs: fix regression in sample mask handling from tgsi removal.
This got the bits the wrong way,
dEQP-VK.rasterization.frag_side_effects.color_at_beginning.sample_mask_after
Fixes:
a63c2daf7ad7 ("llvmpipe/fs: start using nir info in some places.")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25396>
Konrad Dybcio [Tue, 26 Sep 2023 16:53:34 +0000 (18:53 +0200)]
freedreno: Add Adreno 643
Just another funny speedbin of A635
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408>
Konrad Dybcio [Mon, 25 Sep 2023 16:28:27 +0000 (18:28 +0200)]
freedreno: Include speedbin fallback in 690 chipid to fix probing
The kernel exposes CHIP_ID, which consists of:
[63:48] const 0 / reserved
[47:32] speedbin (default 0xffff)
[31:0 ] actual gpu chip ID
Fix the 690 chip id to make it probe correctly.
Keep the existing entry for the downstream KGSL driver.
This is essentially the same as Commit
6067aba9e6db ("freedreno: Include
speedbin fallback in 740 chipid to fix probing"), except for the older
core.
Fixes:
210c6c11cc61 ("freedreno+tu: Add a690 support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408>
Eric Engestrom [Thu, 21 Sep 2023 09:38:43 +0000 (10:38 +0100)]
docs/meson: drop mention that our meson is ready
It's been ready for a very long time, and scons & autotools are long
gone with only meson left, so this note doesn't make much sense anymore.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25323>
Eric Engestrom [Tue, 19 Sep 2023 13:09:10 +0000 (14:09 +0100)]
ci: unify container and build jobs rules
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25294>
Lina Versace [Fri, 15 Sep 2023 23:55:39 +0000 (16:55 -0700)]
intel/pci_ids: Consistently use lowercase
The pci ids used a mixture of uppercase and lowercase, even in the same
file. The inconsistency introduces unnecessary complexity in regular
expressions.
Diff made in vim with `%s/\v(CHIPSET\()([^,]+)/\1\L\2\E/`.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>`
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25257>
Karol Herbst [Tue, 26 Sep 2023 11:52:29 +0000 (13:52 +0200)]
meson/rusticl: add sha1_h
This ensures this file is generated.
Fixes:
20c90fed5a0 ("rusticl: added")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25400>
Martin Roukala (né Peres) [Tue, 26 Sep 2023 05:00:46 +0000 (08:00 +0300)]
radv/ci/vkcts-navi10: catch all the line-related flakes
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25395>
Martin Roukala (né Peres) [Tue, 26 Sep 2023 04:57:17 +0000 (07:57 +0300)]
radv/ci/vkcts-navi21: document more flakes
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25395>
Martin Roukala (né Peres) [Tue, 26 Sep 2023 04:55:37 +0000 (07:55 +0300)]
radv/ci/vkcts-navi21: catch all the line_stipple_(enable|params) flakes
There are so many of these tests, so let's just write a regular
expression to catch them all.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25395>
David Rosca [Sat, 2 Sep 2023 08:00:09 +0000 (10:00 +0200)]
gallium/auxiliary/vl: Only map the shader constants buffer in render
Don't map the buffer in vl_compositor_set_csc_matrix.
This avoids mapping the buffer twice with compute shaders.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25258>
David Rosca [Sun, 3 Sep 2023 07:40:05 +0000 (09:40 +0200)]
gallium/auxiliary/vl: Fix YUV to RGB bob compute shader deinterlacing
This reverts commit
ef0d92459c3f and instead removes the y coordinate
divide by two in weave shaders. The scale ratio now works correctly
with interlaced input.
Also remove the YUV to YUV bob shader and reuse the progressive shader
for bob deinterlacing, same as in YUV to RGB case (video_buffer shader).
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25258>
David Rosca [Sat, 2 Sep 2023 15:19:44 +0000 (17:19 +0200)]
gallium/auxiliary/vl: Use chroma offset in YUV to RGB weave compute shader
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25258>
David Rosca [Wed, 30 Aug 2023 11:18:30 +0000 (13:18 +0200)]
gallium/auxiliary/vl: Add RGB to YUV compute shader
Compared to fragment shader that was being used before, it supports
chroma location and fixes wrong color at right/bottom edge when scaling.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25258>
Corentin Noël [Mon, 25 Sep 2023 09:08:13 +0000 (11:08 +0200)]
mesa: Ensure that the baselevel will never exceed the maximal supported number
GL_TEXTURE_BASE_LEVEL is only supported up to MAX_TEXTURE_LEVELS
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25332>
Samuel Pitoiset [Thu, 21 Sep 2023 12:01:34 +0000 (14:01 +0200)]
radv: declare shader_query_state for mesh/task shaders
This will control whether mesh/task queries is enabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Samuel Pitoiset [Wed, 20 Sep 2023 14:45:04 +0000 (16:45 +0200)]
radv: enable lowering of mesh/task shader queries when enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Samuel Pitoiset [Wed, 20 Sep 2023 15:11:17 +0000 (17:11 +0200)]
radv: adjust lowering of intrinsic queries for mesh/task shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Samuel Pitoiset [Wed, 20 Sep 2023 15:11:04 +0000 (17:11 +0200)]
radv: add GDS counters offset for mesh/task queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Samuel Pitoiset [Thu, 21 Sep 2023 11:53:59 +0000 (13:53 +0200)]
ac/nir: add lowering for task shader queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Samuel Pitoiset [Wed, 20 Sep 2023 15:03:29 +0000 (17:03 +0200)]
ac/nir: add lowering for mesh shader queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Samuel Pitoiset [Thu, 21 Sep 2023 06:38:09 +0000 (08:38 +0200)]
nir: rename atomic_add_gs_invocation_count_amd to make it more generic
It will be re-used to implement mesh/tash shader invocations queries.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
Kenneth Graunke [Tue, 19 Sep 2023 00:43:01 +0000 (17:43 -0700)]
mesa: Fix zeroing of new ParameterValues array entries when growing
On non-Windows OSes, align_realloc is the os_realloc_aligned() from
src/util/os_memory_aligned.h, which doesn't use realloc internally.
Instead, it uses os_malloc_aligned() and memcpy's over the old data,
which is why it needs an "old size" (unlike normal realloc).
In _mesa_reserve_parameter_storage, the call to align_realloc above
passes (oldValNum * sizeof(gl_constant_value)) as the old size, which
is all the actual data. The actual allocation size of the array may
be larger (in fact, we allocate 16 extra components), which is tracked
in SizeValues. After realloc, we memset to zero starting at the old
allocation size, to the new allocation size.
This would work if it were a real realloc. However, because we actually
malloc + memcpy and only copy the previous /data/, not the allocated
size, and then memset from the old /allocated size/, our new copy will
have the spaces between the old data and the old allocation size neither
copied nor memset, leaving them as uninitialized garbage memory.
These values then get written to the shader cache, meaning that if you
compile the same shader multiple times, you may get different shader
cache entries. This is bad for reproducible, deterministic compiles.
While at it, we also memset to zero in _mesa_add_parameter, as this
looks like another place where memset-to-zero is missing.
To reproduce this error, one can run shader-db:
$ MESA_SHADER_CACHE_DIR=a ./run -b shaders/godot3.4/49-28.shader_test
$ MESA_SHADER_CACHE_DIR=b ./run -b shaders/godot3.4/49-28.shader_test
and see an occasional difference in the end of the ParameterValues
array, where there's a padding gap between the last two elements that
was never zero-initialized.
Thanks to Mark Janes for discovering this and tracking it down together!
Cc: mesa-stable
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25316>