Brian Paul [Sat, 29 Apr 2017 03:32:05 +0000 (21:32 -0600)]
st/wgl: use ARRAY_SIZE() macro in wglChoosePixelFormatARB()
Trivial.
Brian Paul [Sat, 29 Apr 2017 03:32:05 +0000 (21:32 -0600)]
st/wgl: whitespace/formatting fixes in stw_ext_pixelformat.c
Trivial.
Neha Bhende [Thu, 27 Apr 2017 17:05:35 +0000 (10:05 -0700)]
svga: implement sRGB rendering for imported surfaces
If texture is imported and templ format is sRGB, use compatible sRGB format
to the imported texture format while creating surface view.
tested with MTT piglit, glretrace, viewperf and conform
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Neha Bhende [Thu, 27 Apr 2017 17:37:02 +0000 (10:37 -0700)]
svga: add function svga_linear_to_srgb()
This function will return compatible svga srgb format for corresponding
linear format
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Neha Bhende [Wed, 26 Apr 2017 23:21:32 +0000 (16:21 -0700)]
glx: add missing sRGB attribute check in fbconfigs_compatible()
This patch will allow driver to choose srgb capable FBconfig
if GLX_FRAMEBUFFER_SRGB_CAPABLE_ARB attribute is 1
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Thomas Hellstrom [Fri, 7 Apr 2017 12:54:56 +0000 (14:54 +0200)]
svga: Add a more elaborate format compatibility determination v2
dri3 is a bit sloppy about its format compatibility requirements, so add
a possibility to import xrgb surfaces as argb textures and vice versa.
At the same time, make the svga_texture_from_handle() function a bit more
readable and fix the error path where we leaked a winsys surface.
v2: Addressed review comments by Brian.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tim Rowley [Sat, 22 Apr 2017 03:14:16 +0000 (22:14 -0500)]
swr/rast: add memory api to SwrGetInterface()
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 21 Apr 2017 18:35:55 +0000 (13:35 -0500)]
swr/rast: use gather instruction for odd format fetch
Small fetch performance optimization - use gather instruction
for odd format fetch instead of slow emulated code.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 21 Apr 2017 18:18:55 +0000 (13:18 -0500)]
swr/rast: enable SIMD16 8x2 tile backend
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 21 Apr 2017 15:21:19 +0000 (10:21 -0500)]
swr/rast: add SwrInit() to init backend/memory tables
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 20 Apr 2017 23:34:29 +0000 (18:34 -0500)]
swr/rast: increment depth/stencil tile pointer in SIMD16 BE
Misplaced #endif preventing depth and stencil hot tile pointers
from incrementing in SIMD16 8x2 configuration of BackendPixelRate.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 20 Apr 2017 00:00:21 +0000 (19:00 -0500)]
swr/rast: add SwrGetInterface() function to return api
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 19 Apr 2017 22:03:32 +0000 (17:03 -0500)]
swr/rast: enable per-warp scratch space for CS
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 19 Apr 2017 17:21:05 +0000 (12:21 -0500)]
swr/rast: reduce simd{16}vertex stack for VS output
Frontend - reduce simdvertex/simd16vertex stack usage for VS output in
ProcessDraw, fixes stack overflow in some of the deeper call stacks under
SIMD16.
1. Move the vertex store out of PA_FACTORY, and off the stack
2. Allocate the vertex store out of the aligned heap (pointer is
temporarily stored in TLS, but will be migrated to thread pool
along with other frontend temporary buffers).
3. Grow the vertex store as necessary for the number of verts per
primitive, in chunks of 8/4 simdvertex/simd16vertex
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 19 Apr 2017 15:58:59 +0000 (10:58 -0500)]
swr/rast: remove default argument from SwrSync()
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 13 Apr 2017 21:26:08 +0000 (16:26 -0500)]
swr/rast: remove unused variables in the SIMD16 FE
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 13 Apr 2017 21:11:09 +0000 (16:11 -0500)]
swr/rast: move construction of const above goto
Fixes gcc error for SIMD16 FE.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 13 Apr 2017 21:01:12 +0000 (16:01 -0500)]
swr/rast: name threads to aid debugging
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 26 Apr 2017 18:11:00 +0000 (13:11 -0500)]
swr/rast: disable buffer overrun warning for Assemble()
Disabling buffer overrun warning for Assemble(uint32_t slot,
simdvector *verts) due to what looks like a MSVC compiler bug
when compiling the SIMD16 FE.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 26 Apr 2017 18:10:23 +0000 (13:10 -0500)]
swr/rast: clean up clipper comments
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 26 Apr 2017 18:09:00 +0000 (13:09 -0500)]
swr/rast: add SIMDAPI decorators in binner/clipper
Fixes MSVC errors with SIMD16 FE.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 11 Apr 2017 22:25:11 +0000 (17:25 -0500)]
swr/rast: add additional jit utility functions
Not used yet.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 10 Apr 2017 16:29:45 +0000 (11:29 -0500)]
swr/rast: more flexible max attribute slots
Ability to allocate space for an arbitrary number (at compile time)
of positions in the vertex layout.
Removes KNOB_NUM_ATTRIBUTES from knobs.h, replaces the VTX slot
number #defines with the SWR_VTX_SLOTS enum (which contains
replacement for NUM_ATTRIBUTES: SWR_VTX_NUM_SLOTS)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Kenneth Graunke [Thu, 27 Apr 2017 06:49:49 +0000 (23:49 -0700)]
i965: Drop BRW_NEW_CONTEXT from 3DSTATE_DS/GS on Gen7-7.5.
We already have BRW_NEW_BATCH, which completely covers all the cases
that BRW_NEW_CONTEXT would handle. Drop it.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 27 Apr 2017 06:48:49 +0000 (23:48 -0700)]
i965: Drop _NEW_TRANSFORM from 3DSTATE_DS/GS on Gen7-7.5.
There's no reason for this as far as I can tell.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 27 Apr 2017 05:34:50 +0000 (22:34 -0700)]
i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.
Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not. We ought to
be consistent - the answer depends on the API, not the hardware generation.
The Sandybridge PRM says about RASTRULE_UPPER_RIGHT:
"To match OpenGL point rasterization rules (round to +infinity, where
this is the upper right direction wrt OpenGL screen origin of lower
left).
So this is likely the one we should use.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Wed, 26 Apr 2017 21:27:15 +0000 (14:27 -0700)]
i965: Always set AALINEDISTANCE_TRUE on Sandybridge.
We set this unconditionally on every other platform. Zero (Manhattan)
isn't even listed as an option in the Sandybridge docs - only "true".
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Wed, 26 Apr 2017 21:28:49 +0000 (14:28 -0700)]
i965: Use true AA line distance on G45/Ironlake.
The original Broadwater and Crestline platforms computed antialiased
line distances using "manhattan" distance, aka a + b = c. Eaglelake
and Cantiga added "true" distance, which apparently does something
like max(a, b) + min(a, b) / 4. Not exactly "true", but at least
more accurate.
The G45 documentation indicates that the old manhattan distance setting
is "only for debug purposes" and should never be used. The Ironlake
documentation no longer mentions AALINEDISTANCE_MANHATTAN, though it
does still contain the narrative about the feature.
At any rate, we should use the more accurate mode.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Andres Gomez [Fri, 28 Apr 2017 17:45:32 +0000 (20:45 +0300)]
docs: add news item and link release notes for 17.0.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 28 Apr 2017 22:17:40 +0000 (01:17 +0300)]
docs: add sha256 checksums for 17.0.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit
6cb65ce2d3689ae7f692f8cf08559109037dd74e)
Andres Gomez [Fri, 28 Apr 2017 17:41:38 +0000 (20:41 +0300)]
docs: add release notes for 17.0.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit
61b134a862ecc1877bbe2f2c14e493b5fb607e04)
Marek Olšák [Mon, 24 Apr 2017 15:27:37 +0000 (17:27 +0200)]
radeonsi: don't load unused compute shader input SGPRs and VGPRs
Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine
whether to load BLOCK_ID for each component separately, and set the number
of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave
rate in most cases.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 24 Apr 2017 14:29:22 +0000 (16:29 +0200)]
tgsi/scan: record compute shader system value usage
v2: just do indexing with swizzle[i]
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 24 Apr 2017 10:10:24 +0000 (12:10 +0200)]
radeonsi: add a HUD query for draw calls with primitive restart
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sat, 22 Apr 2017 22:46:55 +0000 (00:46 +0200)]
radeonsi: tell LLVM not to remove s_barrier instructions
LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 19:12:08 +0000 (21:12 +0200)]
radeonsi: fix tess offchip offset for per-patch attributes
We need 4 more bits there. I don't know what is fixed by this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 17:34:26 +0000 (19:34 +0200)]
radeonsi: pass tessellation ring addresses via user SGPRs
This removes s_load_dword latency for tess rings.
We need just 1 SGPR for the address if we use 64K alignment. The final asm
for recreating the descriptor is:
// s2 is (address >> 16)
s_mov_b32 s3, 0
s_lshl_b64 s[4:5], s[2:3], 16
s_mov_b32 s6, -1
s_mov_b32 s7, 0x27fac
v2: bitcast the descriptor type from v2i64 to v4i32
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 16:56:12 +0000 (18:56 +0200)]
radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 16:04:00 +0000 (18:04 +0200)]
radeonsi: remove VS epilog code, compile VS with PrimID export on demand
The use of PrimID in the pixel shader is too rare to deserve such
a sizable support code.
The initial idea of the VS epilog was to move the clipping code there and
remove it based on states, but optimized variants are now used to do that
and are easier to support, so the VS epilog has turned out to be not so
useful.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 15:27:10 +0000 (17:27 +0200)]
radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3
VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 12:12:52 +0000 (14:12 +0200)]
radeonsi: don't load PrimID in TES if it's not used
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 23:07:19 +0000 (01:07 +0200)]
radeonsi: explain (non-)monolithic shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 15 Feb 2017 02:04:01 +0000 (03:04 +0100)]
radeonsi/gfx9: enable OpenGL 4.5
Tentatively enable it, expecting the scratch buffer support to be done before
the next Mesa release.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 20 Apr 2017 11:06:31 +0000 (13:06 +0200)]
radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 20 Apr 2017 11:04:02 +0000 (13:04 +0200)]
radeonsi: add reference counting for shader selectors
The 2nd shader of merged shaders should take a reference of the 1st shader.
The next commit will do that.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 00:53:19 +0000 (02:53 +0200)]
radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 00:48:02 +0000 (02:48 +0200)]
radeonsi/gfx9: set TES registers for merged ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:24:05 +0000 (03:24 +0200)]
radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS
not implemented yet
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 18 Apr 2017 23:53:35 +0000 (01:53 +0200)]
radeonsi/gfx9: always compile monolithic ES-GS (asynchronously)
In addition to the non-monolithic variant.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 18 Apr 2017 23:24:43 +0000 (01:24 +0200)]
radeonsi/gfx9: add support for monolithic ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 18 Apr 2017 21:49:07 +0000 (23:49 +0200)]
radeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:37:14 +0000 (03:37 +0200)]
radeonsi/gfx9: select shader parts for non-monolithic ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:37:04 +0000 (03:37 +0200)]
radeonsi/gfx9: add GS prolog support for merged ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:36:33 +0000 (03:36 +0200)]
radeonsi/gfx9: add VS prolog support for merged ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:34:56 +0000 (03:34 +0200)]
radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:34:03 +0000 (03:34 +0200)]
radeonsi/gfx9: store ES outputs to LDS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:33:03 +0000 (03:33 +0200)]
radeonsi/gfx9: load GS inputs from LDS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:31:12 +0000 (03:31 +0200)]
radeonsi/gfx9: get GS wave ID from the correct input
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:29:44 +0000 (03:29 +0200)]
radeonsi/gfx9: add the function signature of merged ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:21:16 +0000 (03:21 +0200)]
radeonsi/gfx9: set registers and shader key for merged ES-GS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:12:55 +0000 (03:12 +0200)]
radeonsi/gfx9: add GS user SGPRs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:17:24 +0000 (03:17 +0200)]
radeonsi: rename declare_tess_lds -> declare_lds_as_pointer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:15:52 +0000 (03:15 +0200)]
radeonsi: simplify some shader type conditions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 01:13:58 +0000 (03:13 +0200)]
radeonsi: rename the swizzle parameter of lds_store
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 7 Apr 2017 19:38:09 +0000 (21:38 +0200)]
radeonsi: add si_shader::prolog2
For a GS prolog in merged ES-GS.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 18:07:20 +0000 (20:07 +0200)]
radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 5 Apr 2017 22:33:45 +0000 (00:33 +0200)]
radeonsi/gfx9: add support for monolithic merged LS-HS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 14 Mar 2017 18:35:28 +0000 (19:35 +0100)]
radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 14 Mar 2017 13:11:41 +0000 (14:11 +0100)]
radeonsi/gfx9: don't store the HS control word
GFX9 doesn't have it.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 21 Feb 2017 02:07:37 +0000 (03:07 +0100)]
radeonsi/gfx9: pass inputs from LS to TCS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 21 Feb 2017 00:42:15 +0000 (01:42 +0100)]
radeonsi/gfx9: add TCS epilog support for merged LS-HS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 20 Feb 2017 21:25:17 +0000 (22:25 +0100)]
radeonsi/gfx9: add VS prolog support for merged LS-HS
HS input VGPRs must be reserved.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 18 Feb 2017 02:04:21 +0000 (03:04 +0100)]
radeonsi/gfx9: merged shaders have scratch offset at the beginning
also, screen wasn't initialized for compute shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 18 Feb 2017 00:47:27 +0000 (01:47 +0100)]
radeonsi/gfx9: define LS-HS main shader function prototype
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 17 Feb 2017 17:29:17 +0000 (18:29 +0100)]
radeonsi: assign VS/TCS/TES/GS shader input parameter locations dynamically
They will vary with merged stages.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 15 Feb 2017 21:47:57 +0000 (22:47 +0100)]
radeonsi/gfx9: define and set LS-HS user SGPRs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 15 Feb 2017 10:57:47 +0000 (11:57 +0100)]
radeonsi/gfx9: set up shader registers for merged LS-HS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 6 Apr 2017 20:55:06 +0000 (22:55 +0200)]
radeonsi/gfx9: add initial code generation for non-monolithic merged LS-HS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 19 Apr 2017 23:10:17 +0000 (01:10 +0200)]
radeonsi: separate out code for selecting the VS prolog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 7 Apr 2017 19:41:10 +0000 (21:41 +0200)]
radeonsi/gfx9: add si_shader::previous_stage for merged shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 16 Feb 2017 18:36:46 +0000 (19:36 +0100)]
radeonsi/gfx9: enlarge num_input_sgprs in shader keys due to higher hw limit
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 7 Apr 2017 23:04:56 +0000 (01:04 +0200)]
radeonsi/gfx9: update the summary of shader stage configs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 6 Apr 2017 20:03:07 +0000 (22:03 +0200)]
radeonsi: adjust the signature of si_get_vs_prolog_key
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 6 Apr 2017 20:55:06 +0000 (22:55 +0200)]
radeonsi: separate out VS prolog key generation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 6 Apr 2017 20:00:53 +0000 (22:00 +0200)]
radeonsi: separate out VS prolog key printing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 11 Nov 2016 21:37:39 +0000 (22:37 +0100)]
radeonsi: code shuffling in si_emit_derived_tess_state
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 15 Mar 2017 22:06:59 +0000 (23:06 +0100)]
radeonsi: separate out TGSI initialization of si_shader_context
so that we can put multiple different TGSI shaders into one module.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 25 Apr 2017 22:28:29 +0000 (00:28 +0200)]
st/mesa: use min_index and max_index directly from vbo
also remove the incorrect comment about primitive restart.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 25 Apr 2017 22:28:05 +0000 (00:28 +0200)]
vbo: set min_index = 0 so gallium can use the value directly
We could also remove index_bounds_valid and use max_index != ~0 instead.
Opinions on that are welcome.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Matt Turner [Fri, 28 Apr 2017 19:29:11 +0000 (12:29 -0700)]
Revert "glsl: reject image qualifiers with non-image types inside uniform blocks"
This reverts commit
24011ead71ea9980e6b34e40d9dbd64e6560f5a4.
This causes lots of ES 3.1 CTS tests to fail to compile a bit of code
like:
layout(binding = 0) buffer InOut
{
highp uint inputValues[384];
highp uint outputValues[384];
coherent highp uint groupValues[64]; <-----
} sb_inout;
error: memory qualifiers may only be applied to images
Brian Paul [Fri, 28 Apr 2017 02:59:44 +0000 (20:59 -0600)]
st/mesa: add more fallback gallium formats for GL integer formats
The VMware driver has a limited set of integer texture formats. We
often have to fall back to 4-component formats when 1- or 2-component
formats are missing.
This fixes about 8 integer texture Piglit tests with the VMware driver
on Linux. We've had this code in-house for a long time but I guess it
was never up-streamed to Mesa master.
This shouldn't regress any other drivers since we're either choosing
an earlier format in the list, or failing anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 27 Apr 2017 14:52:30 +0000 (08:52 -0600)]
mesa: optimize color_buffer_writes_enabled()
Return as soon as we find an existing color channel that's enabled for
writing. Typically, this allows us to return true on the first loop
iteration intead of doing four iterations.
No piglit regressions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 27 Apr 2017 15:03:02 +0000 (09:03 -0600)]
st/mesa: whitespace clean-ups in st_manager.c
Trivial.
Matt Turner [Fri, 28 Apr 2017 18:48:29 +0000 (11:48 -0700)]
Revert "glsl: set vector_elements to 1 for samplers"
This reverts commit
75a31a20af269c047661af33e28f793269537b79.
This breaks thousands of tests on i965 with malloc corruption.
Chad Versace [Mon, 24 Apr 2017 17:32:12 +0000 (10:32 -0700)]
anv: Drop 'x11' prefix from non-X11 WSI funcs
Drop it from x11_anv_wsi_image_create and x11_anv_wsi_image_free. The
functions are used by Wayland WSI too.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Jason Ekstrand [Fri, 28 Apr 2017 12:02:27 +0000 (05:02 -0700)]
anv: Alphabetize KHR extensions
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Emil Velikov [Fri, 28 Apr 2017 12:35:18 +0000 (13:35 +0100)]
ac: automake: sort sources list alphabetically
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 28 Apr 2017 12:33:58 +0000 (13:33 +0100)]
ac: include all sources in the tarball
Fixes:
e2659176cef ("radeonsi/ac: move vertex export remove to common code.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Nicolai Hähnle [Fri, 21 Apr 2017 13:11:34 +0000 (15:11 +0200)]
st/mesa: remove redundant stfb->iface checks
stfb->iface is always non-NULL for an st_framebuffer. These checks
were incorrect, relying on out-of-bounds memory access in the
surface-less case of EGL_KHR_surfaceless_context.
v2: remove redundant stread check (Marek)
Reviewed-by: Marek Olšák <marek@olsak@amd.com> (v2)
Nicolai Hähnle [Fri, 21 Apr 2017 13:06:47 +0000 (15:06 +0200)]
st/mesa: don't cast the incomplete framebufer to st_framebuffer
The incomplete framebuffer is set for a surfaceless context. This leads to
the following error in piglit spec@egl_khr_surfaceless_context@viewport:
==26703==ERROR: AddressSanitizer: global-buffer-overflow on address 0x7f6886e43240 at pc 0x7f68854db0fd bp 0x7ffca404b3b0 sp 0x7ffca404b3a0
READ of size 8 at 0x7f6886e43240 thread T0
#0 0x7f68854db0fc in st_viewport ../../../mesa-src/src/mesa/state_tracker/st_cb_viewport.c:57
#1 0x556840176cdb in main tests/egl/spec/egl_khr_surfaceless_context/viewport.c:101
#2 0x7f688edcf3f0 in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x203f0)
#3 0x556840176e19 in _start (/home/nha/amd/piglit/bin/egl-surfaceless-context-viewport+0xe19)
0x7f6886e43240 is located 32 bytes to the left of global variable 'DummyRenderbuffer' defined in '../../../mesa-src/src/mesa/main/fbobject.c:69:31' (0x7f6886e43260) of size 112
0x7f6886e43240 is located 8 bytes to the right of global variable 'IncompleteFramebuffer' defined in '../../../mesa-src/src/mesa/main/fbobject.c:73:30' (0x7f6886e42de0) of size 1112
SUMMARY: AddressSanitizer: global-buffer-overflow ../../../mesa-src/src/mesa/state_tracker/st_cb_viewport.c:57 in st_viewport
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek@olsak@amd.com>