Ben Widawsky [Thu, 25 Apr 2013 01:50:01 +0000 (18:50 -0700)]
gem_storedw_loop_vebox: Modernize test to look like blitter
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Xiang, Haihao [Tue, 23 Apr 2013 07:06:43 +0000 (15:06 +0800)]
tests: storedw on VEBOX
v2 (Ben): Define LOCAL_I915_EXEC_VEBOX
Small copyright fixes
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhong Li <zhong.li@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Xiang, Haihao [Tue, 23 Apr 2013 07:06:42 +0000 (15:06 +0800)]
gem_ring_sync_loop: test the new ring
The code is surround by a #ifdef...#endif to avoid to break compiling against
the current libdrm release
v2 (Ben): Use VEBOX get param. Thankfully Daniel let us carve this out
way back when.
Spacing cleanups
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhong Li <zhong.li@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Xiang, Haihao [Tue, 23 Apr 2013 07:06:41 +0000 (15:06 +0800)]
gem_ring_sync_loop: check the rings supported by the kernel
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhong Li <zhong.li@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Mon, 22 Apr 2013 18:36:03 +0000 (11:36 -0700)]
intel_error_decode: HEAD stuff
Show the decoded HEAD value, as well as print the calculated head offset
per ringbuffer.
This will be superceded in the next commit, but that patch is way more
complicated than this one (read: error prone), so I want this here.
Example:
ringbuffer (blitter ring) at 0x00044000; HEAD points to: 0x00044950
v2: Actually make it work for all rings.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Mon, 22 Apr 2013 18:07:35 +0000 (11:07 -0700)]
intel_error_decode: Whitespacing fix
The rest of igt has moved to kernel coding style. People had already
been not conforming with the existing formatting in error decode, so we
may as well fix it.
This addresses two primary issues, tabbing (remove spaces), and space
after function in function call. I may have missed some of the latter
since that was done by hand.
I have upcoming work in this file, and it was annoying me.
v2: Fix case alignment (Chris)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Imre Deak [Wed, 17 Apr 2013 20:18:02 +0000 (23:18 +0300)]
tests/prime_self_import: add subtest to export/import a second gem buffer
Also add a subtest for the fd=handle_to_fd(), fd2=dup(fd), close(fd)
case (idea from Kristian Høgsberg).
Signed-off-by: Imre Deak <imre.deak@intel.com>
v2:
- add a new subtest instead of modifying the original test (Daniel)
- add a new subtest for testing dup (Kristian)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Wed, 17 Apr 2013 06:09:25 +0000 (23:09 -0700)]
quick_dump: Add dpio read
The sample usage is in reg_access.dpio_read(). We should add some
semantics to the text files to detect DPIO registers, and do the right
thing.
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Fri, 22 Feb 2013 06:05:36 +0000 (22:05 -0800)]
reg_access: Forcewake as necessary
Don't try to be smart. Just poke all forcewake bits if it seems we need
it.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Fri, 22 Feb 2013 06:05:35 +0000 (22:05 -0800)]
quick_dump: add register write
Since there is no command line support, just do a pure integer version
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Fri, 22 Feb 2013 06:05:34 +0000 (22:05 -0800)]
intel_mmio: a query for forcewake requirement
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Fri, 22 Feb 2013 06:05:33 +0000 (22:05 -0800)]
intel_mmio: Allow mmio without debugfs
With the introduction of the forcewake dance:
commit
cac8f8b52621f246a7cff412f340a7db28cb1b99
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Thu Jul 28 13:40:19 2011 -0700
forcewake: Add mmio code to do proper forcewake stuff for gen6
We lost the ability to do register access when either debugfs isn't
mounted, or when the driver isn't loaded. The latter can be beneficial
in debugging situations.
This patch will allow the driver to still do mmio (leaving forcewake
management up to the callers) provided that the i915 driver appears to
not be loaded (according to sysfs)
Requested by Jesse.
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Fri, 22 Feb 2013 06:05:32 +0000 (22:05 -0800)]
quick_dump: say something when reg init fails
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Jesse Barnes [Tue, 16 Apr 2013 20:16:31 +0000 (13:16 -0700)]
fixup VLV reg offsets, add a few more
Jesse Barnes [Tue, 16 Apr 2013 20:14:58 +0000 (13:14 -0700)]
add VLV punit & north cluster read tools
Ville Syrjälä [Thu, 11 Apr 2013 17:43:40 +0000 (20:43 +0300)]
tests/gem_fenced_exec_thrash: Test with > max fences
Make sure the kernel returns EDEADLK when the number of fences is
exceeded for gen2-3. For gen4+ the test makes sure the kernel ignores
the EXEC_OBJECT_NEEDS_FENCE flag.
Note that I changed the code not to round the num_fences to an even
number. Not sure why that was there, and if there's a reason for it,
we need to add it back.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Thu, 11 Apr 2013 13:11:28 +0000 (16:11 +0300)]
tests/gem_seqno_wrap: verify debugfs write with readback
Make sure that debugfs entry works as expected by reading
back the sequence number that was written.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 9 Apr 2013 14:45:37 +0000 (17:45 +0300)]
tests/gem_tiling_max_stride: Add a test for max fence stride
gem_tiling_max_stride writes a data pattern to an X-tiled buffer using
the maximum supported stride, reads the data back as linear, and
verifies that the data didn't get scrambled on the way.
The test also checks that some invalid stride values are rejected
properly.
v2: Check invalid strides
v3: Check invalid stride with Y-tiling
Include a few more invalid stride values
Fix gen3 X-tile size
v4: A few more invalid strides :)
Drop the useless memset()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 9 Apr 2013 12:25:38 +0000 (15:25 +0300)]
tests: Use gem_available_fences()
lib/drmtest.c provides gem_available_fences(). Use it where
appropriate.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 9 Apr 2013 12:25:37 +0000 (15:25 +0300)]
tests/gem_fenced_exec_thrash: Increase MAX_FENCES to 32
IVB+ supports 32 fence registers, bump the maximum in the test.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Thu, 4 Apr 2013 17:33:59 +0000 (14:33 -0300)]
intel_reg_dumper: improve the dumping of backlight registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Ben Widawsky [Mon, 8 Apr 2013 17:50:57 +0000 (10:50 -0700)]
m4: Updates to ax_python_devel.m4
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Daniel Vetter [Mon, 8 Apr 2013 07:19:05 +0000 (09:19 +0200)]
tests/gem_fence_trash: make threaded tests more through-rough
With this at least the y-tiled test reliably fails on my machines, but
x-tiled still passes on some. More ideas to tune this highly welcome.
v2: Fill cpu caches with data for each newly allocated bo. This seems
to do the trick on my snb here _really_ reliably. So apparently the
backsnoop for llc gtt writes is the crucial ingredient here to make
the test fail.
While at it, also stop leaking mmap space.
v3: Fixup commit message.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Sun, 7 Apr 2013 22:31:06 +0000 (00:31 +0200)]
lib/drmtest: tune down signal handler stats
Avoids tests with a spurious WARN result in piglit.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Sat, 6 Apr 2013 16:29:37 +0000 (18:29 +0200)]
tests/kms_flip: don't leak gpu hang state
We need to clear out the error_state. While at it also make sure that
the hang was indeed detected.
Whoever writes the next test to race against gpu hangs should probably
extract these two functions into the drmtest library. Which just one
user that's not really worth it right now.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 4 Apr 2013 09:36:27 +0000 (11:36 +0200)]
tests/prime_udl: skip harder
I fail.
Daniel Vetter [Thu, 4 Apr 2013 09:06:37 +0000 (11:06 +0200)]
tests/prime_udl: proper return values
... especially skip properly if there's no udl device.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 2 Apr 2013 22:22:41 +0000 (00:22 +0200)]
lib: fixup register access on gen2/3
This wreaked havoc with intel_reg_dumper since it's been broken in
commit
c6fe31bc473a7ae44bc42bad7da5faca3c924821
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Thu Jun 21 14:31:34 2012 -0300
intel_reg_dumper: use intel_register_access_init/fini
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Wed, 27 Mar 2013 11:32:47 +0000 (11:32 +0000)]
gem_fence_thrash: Fix array allocation size for LP64 systems
Kenneth Graunke [Wed, 27 Mar 2013 05:06:39 +0000 (22:06 -0700)]
intel_perf_counters: Add support for Sandybridge.
While the Sandybridge PRM doesn't have any documentation on the GPU's
performance counters, a lot of information can be gleaned from the older
Ironlake PRM. Oddly, none of the information documented there actually
appears to apply to Ironlake. However, it apparently works just great
on Sandybridge.
Since this information has all been publicly available on the internet
for around three years, we can use it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Kenneth Graunke [Wed, 27 Mar 2013 05:06:38 +0000 (22:06 -0700)]
intel_perf_counters: Abstract out Ironlake-specific code.
We want to support this tool on more platforms. This lays the
groundwork for making that possible.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Eric Anholt [Wed, 27 Mar 2013 05:06:37 +0000 (22:06 -0700)]
intel_perf_counters: a little tool for dumping performance counters.
This reads the GPU's performance counters via MI_REPORT_PERF_COUNT and
prints them in a top-style interface. While it can be useful in and of
itself, it also documents the performance counters and lets us verify
that they're working.
Currently, it only supports Ironlake.
v2 [Ken]: Rebase on master and fix compilation failures; make it abort
on non-Ironlake platforms to avoid GPU hangs; rename from 'chaps' to
intel_perf_counters since that acronym isn't used any longer; write the
above commit message.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 27 Mar 2013 11:26:46 +0000 (12:26 +0100)]
tests/Makefile.am: gem_fence_trash has grown subtests
Need to move it to the right make target now!
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Wed, 27 Mar 2013 10:48:07 +0000 (12:48 +0200)]
tests: add write-verify test to gem_fence_thrash
Add write-verify test to gem_fence_thrash. Test will create
multiple threads per fence then verify the write into fenced region.
v2: non-threaded, non-tiled tests added. suggested by Chris Wilson.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Fri, 22 Mar 2013 17:28:24 +0000 (14:28 -0300)]
intel_reg_dumper: debug SDEISR on Haswell
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo Zanoni [Fri, 1 Mar 2013 20:32:34 +0000 (17:32 -0300)]
lib: fix HAS_PCH_SPLIT check
So HAS_PCH_SPLIT on't be true on VLV.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo Zanoni [Fri, 1 Mar 2013 20:12:29 +0000 (17:12 -0300)]
intel_reg_dumper: dump HSW watermark registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo Zanoni [Fri, 1 Mar 2013 19:55:22 +0000 (16:55 -0300)]
intel_reg_dumper: decode some useful Haswell registers
I've checked the value of these registers many many many times during
development.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo Zanoni [Fri, 1 Mar 2013 18:46:25 +0000 (15:46 -0300)]
intel_reg_dumper: make Haswell dump useful
It was previously printing ironlake_debug_regs and haswell_debug_regs.
Since ironlake_debug_regs contains a lot of registers that don't exist
on Haswell, running intel_reg_dumper on Haswell caused "unclaimed
register" messages. Now I've copied the existing registers from
ironlake_debug_regs to haswell_debug_regs, so we won't print the
registers that don't exist anymore.
Also removed DP_TP_STATUS_A since it doesn't exist.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo Zanoni [Fri, 1 Mar 2013 16:53:40 +0000 (13:53 -0300)]
intel_reg_dumper: recognize LPT
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo Zanoni [Fri, 1 Mar 2013 16:30:46 +0000 (13:30 -0300)]
lib: detect PCH_LPT and PCH_NONE
So we don't assign PCH_IBX to anything that's not PCH_CPT nor PCH_LPT.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Kees Cook [Fri, 15 Mar 2013 18:09:07 +0000 (11:09 -0700)]
tests: add gem_reloc_overflow to check wrapping
This adds a test to make sure that the execbuffer validation routine is
checking for invalid addresses, single entry overflow, and multi-entry
wrapping overflow.
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Mon, 4 Mar 2013 13:34:07 +0000 (15:34 +0200)]
kms_flip: Don't access freed data
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Mon, 4 Mar 2013 13:34:06 +0000 (15:34 +0200)]
kms_flip: Add flip-vs-bad-tiling test
flip-vs-bad-tiling tests that page flipping to a Y-tiled buffer returns
an error correctly, rather than triggering kernel BUG for instance.
Create a third fb for this purpose. After the fb has been created,
change its tiling mode to Y. When performing a flip, target this
Y-tiled fb and make sure we get the expected error value.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 15 Feb 2013 15:10:47 +0000 (17:10 +0200)]
kms_flip: Add a flip-vs-panning-vs-hang test
The flip-vs-panning-vs-hang is just like the regular flip-vs-panning
test, except it also hangs the GPU. This will test whether panning
works after a pending page flip has been cancelled by a GPU reset,
and also whether page flip events get delivered correctly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 15 Feb 2013 15:10:46 +0000 (17:10 +0200)]
kms_flip: Split the "no events" logic into a separate flag
Do not use the TEST_HANG flag to determine whether page flip events are
used. Add a new TEST_NOEVENT flag that can be used to disable the use
of events instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Thu, 21 Mar 2013 16:19:36 +0000 (16:19 +0000)]
lib: Add a comment about why we only parse long options for subtests
For thet next one wondering about that.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 4 Mar 2013 15:59:00 +0000 (15:59 +0000)]
build: Fix typo if the test setting enable_debugger
Of course, a 'x' need to be inserted there.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 4 Feb 2013 13:57:48 +0000 (13:57 +0000)]
assembler: Mark format() as PRINTFLIKE in the disassembler
So when making changes in code using that function, we get warnings
about mismatches between the format string and arguments.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 4 Feb 2013 12:23:57 +0000 (12:23 +0000)]
assembler: Fix the decoding of the destination horizontal stride
dest_horizontal_stride needs go through the horiz_stride[] indirection
to pick up the rigth stride when its value is 11b (4 elements).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 4 Feb 2013 12:12:29 +0000 (12:12 +0000)]
assembler: Group the header inclusions together
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 4 Feb 2013 12:02:18 +0000 (12:02 +0000)]
assembler: Don't use GL types
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
-e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
-e 's/GLshort/int16_t/g' assembler/*.[ch]
Drop the GL types here, they don't bring anything to the table. For
instance, GLuint has no guarantee to be 32 bits, so it does not make too
much sense to use it in structure describing hardware tables and
opcodes.
Of course, some bikeshedding can be applied to use uin32_t instead, I
figured that some of the GLuint are used without size constraints, so
a sed with uint32_t did not seem the right thing to do. On top of that
initial sed, one bothered enough could change the structures with size
constraints to actually use uint32_t.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 1 Feb 2013 14:54:46 +0000 (14:54 +0000)]
assembler: Remove trailing white space
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 1 Feb 2013 14:09:41 +0000 (14:09 +0000)]
assembler: Use defines for width
Instead of just using hardcoded numbers or resorting to ffs().
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 1 Feb 2013 13:59:32 +0000 (13:59 +0000)]
assembler: Merge declared_register's type into the reg structure
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 1 Feb 2013 13:29:48 +0000 (13:29 +0000)]
assembler: Finish importing brw_eu_*c from mesa
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 18:22:49 +0000 (18:22 +0000)]
assembler: Use set_instruction_src1() in send
No reason not to!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 14:28:00 +0000 (14:28 +0000)]
assembler: Put struct opcode_desc back in brw_context.h
I originally moved struct opcode_desc from brw_context.h to brw_eu.h on
the mesa side, but that was before the realization we needed struct
brw_context if we wanted to not touch the code too much.
So put it back there now that the mesa patch has been dropped.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 14:25:42 +0000 (14:25 +0000)]
assembler: Don't pollute the library files with gen4asm.h
gen4asm.h is assembler specific while we want the library files to be
somewhat of a proper library.
This means that we have to redefine the GL* typedefs for brw_structs.h,
not using any of thet GL typedef will be for a future commit.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 01:28:15 +0000 (01:28 +0000)]
assembler: Use brw_*() functions for 3-src instructions
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 01:27:36 +0000 (01:27 +0000)]
assembler: Add support for D and UD in 3-src instructions
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 00:53:46 +0000 (00:53 +0000)]
assembler: Expose setters for 3src operands
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 00:26:51 +0000 (00:26 +0000)]
assembler: Introduce set_instruction_saturate()
Also simplify the logic that was setting the saturate bit in the math
instruction.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 31 Jan 2013 00:18:47 +0000 (00:18 +0000)]
assembler: Introduce set_intruction_pred_cond()
This allow us to factor out the test that checks if, when using both
predicates and conditional modifiers, we are using the same flag
register.
Also get rid of of a FIXME that we are now dealing with (the warning
mentioned above).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 23:39:09 +0000 (23:39 +0000)]
assembler: Introduce set_instruction_opcode()
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 23:25:19 +0000 (23:25 +0000)]
assembler: Isolate all the options in their own structure
Like with the predicate fields before, there's no need to use the full
instruction to collect the list of options. This allows us to decouple
the list of options from a specific instruction encoding.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 23:00:26 +0000 (23:00 +0000)]
assembler: Unify adding options to the header
Right now we have duplicated code for when the option is the last in the
list or not. Put that code in a common function.
Interestingly it appears that both sides haven't been kept in sync and
that EOT and ACCWRCTRL had limitations on where they had to be in the
option list. It's fixed now!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 22:32:07 +0000 (22:32 +0000)]
assembler: Gather all predicate data in its own structure
Rather than user a full instruction for that. Also use
set_instruction_predicate() for a case that coud not be done like that
before the refactoring (because everyone now uses the same instruction
structure).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 17:09:17 +0000 (17:09 +0000)]
assembler: Move struct relocation out of relocatable instructions
Now that all instructions (relocatable or not) are struct
brw_program_instructions, this means we can move the relocation specific
information out the "relocatable instruction" structure. This will allow
us to share the relocation information between different types of
instructions.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 17:04:13 +0000 (17:04 +0000)]
assembler: Unify all instructions to be brw_program_instructions
Time to finally unify all instructions on the same structure.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 30 Jan 2013 12:31:45 +0000 (12:31 +0000)]
assembler: Renamed the instruction field to insn
This will be less typing for the refactoring to come (which is use
struct brw_program_instruction in gram.y for the type of all the
instructions).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 28 Jan 2013 15:29:26 +0000 (15:29 +0000)]
assembler: Use brw_set_src1()
Everything is now aligned to be able to use brw_set_src1() in the
opcode generation, so use it.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 28 Jan 2013 15:27:59 +0000 (15:27 +0000)]
assembler: Implement register-indirect addressing mode in brw_set_src1()
The assembler allows people to do that and that's something available
since Crestline.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sun, 27 Jan 2013 11:23:38 +0000 (11:23 +0000)]
assembler: Fix ')' placement in condition
A small typo in the condition.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sun, 27 Jan 2013 11:05:50 +0000 (11:05 +0000)]
assembler: Cleanup visibility of a few global variables/functions
Not everything has to be exported out the compilation unit. Do a small
cleanup pass.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sun, 27 Jan 2013 10:41:23 +0000 (10:41 +0000)]
assembler: Port the warning and error reporting to warn()/error()
This way we ensure to have a single place where these are handled. The
immediate benefit is that now line numbers are always printed out, which
is quite handy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sun, 27 Jan 2013 02:06:22 +0000 (02:06 +0000)]
assembler: Use brw_set_src0()
Unfortunately, it's all a walk in the park. Both, internal code in the
assembler and external shaders (libva) generate registers that trigger
assertions in brw_eu_emit.c's brw_validate().
To fix all that I took the option to be able to emit warning with the -W
flag but still make the assembler generate the same opcodes.
We can fix all this, but it requires validation, something that I cannot
do right now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sun, 27 Jan 2013 01:32:52 +0000 (01:32 +0000)]
assembler: Add the input filename to the error/warning messages
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sat, 26 Jan 2013 23:55:01 +0000 (23:55 +0000)]
assembler: Add a check for when ExecSize and width are 1
Another check (that we hit if we try to use brw_set_src0()). Again,
protect it with the -W option.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sat, 26 Jan 2013 23:09:42 +0000 (23:09 +0000)]
assembler: Add a check for when width is 1 and hstride is not 0
The list of region restrictions in bspec do say that we can't have:
width == 1 && hstrize != 0
We do have plenty of assembly code that don't respect that behaviour. So
let's hide the warning under a -W flag (for now) while we fix things.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sat, 26 Jan 2013 22:44:45 +0000 (22:44 +0000)]
assembler: Add error() and warn() shorthands and use them in set_src[01]
Now that we have locations, we can write error() and warn() functions
giving more information about where it's going wrong.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sat, 26 Jan 2013 19:51:28 +0000 (19:51 +0000)]
assembler: Add location support
Let's generate location information about the tokens we are parsing.
This can be used to give accurate location when reporting errors and
warnings.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Sat, 26 Jan 2013 18:26:03 +0000 (18:26 +0000)]
assembler: Don't warn if identical declared registers are redefined
There's no real need to warn when the same register is declared twice.
Currently the libva driver does do that and this warning makes other
errors really hide in a sea of warnings.
Redefining a register with different parameters is a real error though,
so we should not allow that and error out in that case.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 25 Jan 2013 15:48:58 +0000 (15:48 +0000)]
assembler: Store immediate values in reg.dw1.ud
Another step in pushing the parsing in struct brw_reg.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 25 Jan 2013 15:13:30 +0000 (15:13 +0000)]
assembler: Fix comparisons between reg.type and Architecture registers
Of course the assertion is there to make sure GRF and MRF have a reg.nr
< 128. To exclude ARF registers, reg.file has be checked, not reg.type
(channel type). Most likely a typo never caught.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Fri, 25 Jan 2013 15:12:12 +0000 (15:12 +0000)]
assembler: ExecSize can be as big as 32 channels
See the IVB PRM, vol4 part3 5.2.3.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 24 Jan 2013 18:32:20 +0000 (18:32 +0000)]
assembler: Factor out the source register validation
The goal is to use brw_set_src[01](), so let's start by validating the
register we have before generating the opcode.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 24 Jan 2013 16:16:35 +0000 (16:16 +0000)]
assembler: Use brw_set_dest() to encode the destination
A few notes:
I needed to introduce a brw context and compile structs. These are only
used to get which generation we are compiling code for, but eventually
we can use more of the infrastructure.
brw_set_dest() uses the destination register width to program the
instruction execution size.
The assembler can either take subnr in bytes or in number of elements,
so we need a resolve step when setting a brw_reg.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Thu, 24 Jan 2013 12:21:13 +0000 (12:21 +0000)]
assembler: Factor out the destination register validation
The goal is to use brw_set_dest(), so let's start by validating the
register we have before generating the opcode.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 22:29:23 +0000 (22:29 +0000)]
assembler: Use brw_reg in the source operand
Last refactoring step in transition to struct brw_reg.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 21:46:21 +0000 (21:46 +0000)]
assembler: Get rid of src operand's swizzle_set
swizzle_set can be derived from the value of swizzle itself, no need for
that field.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 21:35:10 +0000 (21:35 +0000)]
assembler: Consolidate the swizzling configuration on 8 bits
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 20:33:00 +0000 (20:33 +0000)]
assembler: Replace struct dst_operand by struct brw_reg
One more step on the road to replacing all register-like structures by
struct brw_reg.
Two things in this commit are worth noting:
* As we are using more and more brw_reg, a lot of the field-by-field
assignments can be replaced by 1 assignment which results is a
reduction of code
* As the destination horizontal stride is now stored on 2 bits in
brw_reg, it's not possible to defer the handling of DEFAULT_DSTREGION
(aka (int)-1) when setting the destination operand. It has to be done
when parsing the region and resolve_dst_region() is a helper for that
task.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 16:20:05 +0000 (16:20 +0000)]
assembler: Unify the direct and indirect register type
They are all struct brw_reg registers now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 16:17:28 +0000 (16:17 +0000)]
assembler: Replace struct indirect_reg by struct brw_reg
More code simplification can be layered on top of that (by using some
brw_* helpers to create registers), that'd be for another commit.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 16:06:49 +0000 (16:06 +0000)]
assembler: Replace struct direct_reg by struct brw_reg
More code simplification can be layered on top of that (by using some
brw_* helpers to create registers), that'd be for another commit.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Wed, 23 Jan 2013 15:13:55 +0000 (15:13 +0000)]
assembler: Make struct declared_register use struct brw_reg
It's time to start converting the emission code in gram.y to use libbrw
infrastructure. Let's start with using brw_reg for declared register.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 21 Jan 2013 22:17:54 +0000 (22:17 +0000)]
assembler: Don't expose functions only used in main.c
and make then static.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 21 Jan 2013 22:12:10 +0000 (22:12 +0000)]
assembler: Make sure nobody adds a field back to struct brw_instruction
Adding something there will break the library, so we might as check for
it.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Damien Lespiau [Mon, 21 Jan 2013 21:41:36 +0000 (21:41 +0000)]
assembler: Don't change the size of opcodes!
Until now, the assembler had relocation-related fields added to struct
brw_instruction. This changes the size of the structure and break code
assuming the opcode structure is really 16 bytes, for instance the
emission code in brw_eu_emit.c.
With this commit, we build on the infrastructure that slowly emerged in
the few previous commits to add a relocatable instruction with the
needed fields.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>