Dmitri Gribenko [Fri, 20 May 2022 16:08:29 +0000 (18:08 +0200)]
Adjust BUILD files for [ifs] Switch to using OptTable
Dmitri Gribenko [Fri, 20 May 2022 16:03:20 +0000 (18:03 +0200)]
Adjust BUILD files for [MLIR][GPU] Add NvGpu mma.sync path to the VectorToGPU pass
Aart Bik [Fri, 20 May 2022 02:33:33 +0000 (19:33 -0700)]
[mlir][sparse] add support for complex zero/one building
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D126039
David Goldman [Thu, 28 Apr 2022 19:13:21 +0000 (15:13 -0400)]
[clangd][ObjC] Filter ObjC method completions on the remaining selector
Previously, clangd would filter completions only on the first part of
the selector (first typed chunk) instead of all remaining selector
fragments (all typed chunks).
Differential Revision: https://reviews.llvm.org/D124637
Christopher Bate [Tue, 17 May 2022 23:54:29 +0000 (17:54 -0600)]
[MLIR][GPU] Add NvGpu mma.sync path to the VectorToGPU pass
This changes adds the option to lower to NvGpu dialect ops during the
VectorToGPU convsersion pass. Because this transformation reuses
existing VectorToGPU logic, a seperate VectorToNvGpu conversion pass is
not created. The option `use-nvgpu` is added to the VectorToGPU pass.
When this is true, the pass will attempt to convert slices rooted at
`vector.contract` operations into `nvgpu.mma.sync` ops, and
`vector.transfer_read` ops are converted to either `nvgpu.ldmatrix` or
one or more `vector.load` operations. The specific data loaded will
depend on the thread id within a subgroup (warp). These index
calculations depend on data type and shape of the MMA op
according to the downstream PTX specification. The code for supporting
these details is separated into `NvGpuSupport.cpp|h`.
Differential Revision: https://reviews.llvm.org/D122940
Alex Brachet [Fri, 20 May 2022 15:28:18 +0000 (15:28 +0000)]
[ifs] Switch to using OptTable
Differential revision: https://reviews.llvm.org/D125658
Nabeel Omer [Fri, 20 May 2022 14:24:09 +0000 (15:24 +0100)]
[X86] Add tests for FREM
Introduces basic test coverage for frem on x86.
Split off from https://reviews.llvm.org/D125988
Differential Revision: https://reviews.llvm.org/D126055
Jonas Devlieghere [Fri, 20 May 2022 15:24:42 +0000 (08:24 -0700)]
[lldb] Disable scripted_crashlog_json.test on Apple Silicon
Disable scripted_crashlog_json.test on Apple Silicon until Ismail has
bandwidth to investigate.
rdar://
93655633
Jay Foad [Fri, 20 May 2022 12:23:53 +0000 (13:23 +0100)]
[AMDGPU] Handle mandatory literals in isOperandLegal
Extend SIInstrInfo::isOperandLegal to enforce a limit on the number of
literal operands for all VALU instructions, not just VOP3. In particular
it now handles VOP2 instructions with a mandatory literal operand like
V_FMAAK_F32.
Differential Revision: https://reviews.llvm.org/D126064
Jay Foad [Fri, 20 May 2022 12:06:03 +0000 (13:06 +0100)]
[AMDGPU] Add verification for mandatory literals
Extend the literal operand checking in SIInstrInfo::verifyInstruction to
check VOP2 instructions like V_FMAAK_F32 which have a mandatory literal
operand. The rule is that src0 can also be a literal, but only if it is
the same literal value.
AMDGPUAsmParser::validateConstantBusLimitations already handles this
correctly.
Differential Revision: https://reviews.llvm.org/D126063
Dmitri Gribenko [Fri, 20 May 2022 15:11:18 +0000 (17:11 +0200)]
Fix an unused variable warning in no-asserts build mode
Nikolas Klauser [Thu, 19 May 2022 11:10:37 +0000 (13:10 +0200)]
[libc++] Use _LIBCPP_ASSERT by default for _PSTL_ASSERTions
Reviewed By: ldionne, #libc
Spies: jwakely, rodgert, libcxx-commits
Differential Revision: https://reviews.llvm.org/D125634
Guillaume Chatelet [Fri, 20 May 2022 14:37:17 +0000 (14:37 +0000)]
Revert "[libc] Apply no-builtin everywhere, remove unnecessary flags"
This reverts commit
94d6dd90576637fa0eb2c40ca92320ad4c1a6942.
Sam McCall [Fri, 20 May 2022 13:09:53 +0000 (15:09 +0200)]
[clangd] Provide links to clang-tidy and include-cleaner diagnostic docs
LSP supports Diagnostic.codeInformation since 3.16.
In VSCode, this turns the code (e.g. "unused-includes" or "bugprone-foo") into
a clickable link that opens the docs in a web browser.
Differential Revision: https://reviews.llvm.org/D126065
Tobias Hieta [Fri, 20 May 2022 14:11:02 +0000 (16:11 +0200)]
[clang-format] Don't break lines after pragma region
We have autogenerated pragma regions in our code
which where awkwardly broken up like this:
```
#pragma region foo(bar : hello)
```
becomes
```
#pragma region foo(bar \
: hello)
```
This fixes the problem by adding region as a keyword
and handling it the same way as pragma mark
Reviewed By: curdeius
Differential Revision: https://reviews.llvm.org/D125961
Balazs Benics [Fri, 20 May 2022 14:06:46 +0000 (16:06 +0200)]
[analyzer][NFC] Remove the unused LocAsInteger::getPersistentLoc()
Reviewed By: martong
Differential Revision: https://reviews.llvm.org/D125920
Stephen Long [Fri, 20 May 2022 13:41:37 +0000 (06:41 -0700)]
[clang] Honor __attribute__((no_builtin("foo"))) on functions
Support for `__attribute__((no_builtin("foo")))` was added in https://reviews.llvm.org/D68028,
but builtins were still being used even when the attribute was placed on a function.
Reviewed By: hans
Differential Revision: https://reviews.llvm.org/D124701
Louis Dionne [Wed, 18 May 2022 17:17:14 +0000 (13:17 -0400)]
[libc++] Improve error messages for disabled modes
We should not surface CMake-level options like LIBCXX_ENABLE_FILESYSTEM
to our users, since they don't know what it means. Instead, use a slightly
more general wording.
Also, add an error in <ios> to improve the quality of errors for people
trying to use <iostream> when localization is disabled.
Differential Revision: https://reviews.llvm.org/D125910
Louis Dionne [Thu, 19 May 2022 15:16:37 +0000 (11:16 -0400)]
[libunwind] Introduce a cmake-bridge.cfg.in file to reduce test config duplication
Differential Revision: https://reviews.llvm.org/D125981
Louis Dionne [Fri, 20 May 2022 13:35:44 +0000 (09:35 -0400)]
[libc++abi] Add missing XFAIL on test
Erich Keane [Fri, 20 May 2022 13:20:13 +0000 (06:20 -0700)]
Fix test from df2a4e to work with 32 bit windows targets.
32 Bit windows includes attribute 'thiscall' on member functions as a
default calling convention. This test was not written in a way that
works with that, so added wildcards so it is tolerant of it.
J. Ryan Stinnett [Mon, 9 May 2022 14:45:56 +0000 (15:45 +0100)]
[DebugInfo][NFC] Add instr-ref documentation, migration guide
This used to be D102158, but all the code it describes got re-written, so I
figured I'd take another shot at documenting the new instruction referencing
variable locations, this time from a higher level. Happily there's no longer any
need to describe LiveDebugValues in any detail seeing how it's all SSA-based
now.
Probably the most important part is the explanation of what targets need to do
to support instruction referencing. The list is small, mostly because there's
nothing especially complicated that targets need to do: just instrument their
target-specific optimisations and implement the stack spill/restore recognition
target hooks.
This is a small amount of text (which is a virtue), I'm extremely happy to
expand on anything.
Differential Revision: https://reviews.llvm.org/D113586
Co-authored-by: Jeremy Morse <jeremy.morse@sony.com>
Sanjay Patel [Fri, 20 May 2022 13:07:21 +0000 (09:07 -0400)]
[InstCombine] add use check to fold of bitwise logic with cast ops
This was shown as a potential regression in D126040.
Sanjay Patel [Fri, 20 May 2022 13:01:41 +0000 (09:01 -0400)]
[InstCombine] add casted bitwise logic tests to show missing use check; NFC
While here, update the auto-generated checks to also check
the match the function parameters - there was a potential
miscompile that would go unnoticed with the more lenient
check lines.
Alexey Bataev [Wed, 4 Aug 2021 17:58:37 +0000 (10:58 -0700)]
[SLP]Do not emit extract elements for insertelements users, replace with shuffles directly.
SLP vectorizer emits extracts for externally used vectorized scalars and
estimates the cost for each such extract. But in many cases these
scalars are input for insertelement instructions, forming buildvector,
and instead of extractelement/insertelement pair we can emit/cost
estimate shuffle(s) cost and generate series of shuffles, which can be
further optimized.
Tested using test-suite (+SPEC2017), the tests passed, SLP was able to
generate/vectorize more instructions in many cases and it allowed to reduce
number of re-vectorization attempts (where we could try to vectorize
buildector insertelements again and again).
Differential Revision: https://reviews.llvm.org/D107966
Alexey Bataev [Fri, 20 May 2022 12:31:03 +0000 (05:31 -0700)]
[SLP][NFC]Use SmallPtrSet to avoid n*m complexity, NFC.
Haojian Wu [Mon, 16 May 2022 12:46:09 +0000 (14:46 +0200)]
[clangd] Support UnresolvedUsingTypeLoc AST node in FindTarget.
to make features like hover, go-to-def work when the cursor is on the
UnresolvedUsingTypeLoc.
Differential Revision: https://reviews.llvm.org/D125684
Rahul Anand R [Fri, 20 May 2022 12:41:32 +0000 (13:41 +0100)]
[AArch64] Generate AND in place of CSEL for predicated CTTZ
This patch implements a for a target specific optimization that replaces
the cmp and csel from cttz with an and mask.
Recommitted with a fix for truncated value sizes.
Differential Revision: https://reviews.llvm.org/D123782
Fraser Cormack [Thu, 19 May 2022 10:03:36 +0000 (11:03 +0100)]
[RISCV] Fix logic for determining RVV stack padding
We must add padding when using SP or BP to access stack objects.
Checking whether we're missing FP is not sufficient as stack realignment
uses SP too. The test in D125962 explains the specific issue in more
detail.
Split from D125787.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D125964
Fraser Cormack [Thu, 19 May 2022 09:58:17 +0000 (10:58 +0100)]
[RISCV] Add a test showing overlapping stack offsets with RVV
This test (and its forthcoming fix) was split off from D125787. It shows
that the logic we use to determine when we need to add extra RVV padding
is insufficient.
In this example, we may have a situation involving dynamic stack
alignment -- but no variable-sized objects -- where we have no FP but
must still use SP to index objects. In this case we also need the
extra RVV padding, otherwise objects may overlap. Specifically, the test
shows that the RVV vector object may clobber the lowest callee-save.
|------------------------------| -- <-- Incoming SP
| 4-byte callee-save (ra) |
|------------------------------| -- <-- SP + VLENB*2 + 60
| 4-byte callee-save (s0) |
|------------------------------| -- <-- SP + VLENB*2 + 56 --
| 4-byte callee-save (s9) | |
|------------------------------| -- <-- SP + VLENB*2 + 52 | RVV object(!!)
| VLENB*2 RVV object | |
|------------------------------| -- <-- SP + 56 --
| 4-byte local object |
|------------------------------| -- <-- SP + 32
| Dead area |
|------------------------------| -- <-- InSP - 2*VLENB - 64
| Possibly-zero realignment |
|------------------------------| -- <-- SP (realigned to 32)
This diagram should help show that when SP==InSP -- e.g., when the incoming SP
is 32-byte aligned, subtracting 2*VLENB+64 may keep it that way -- the RVV
object clobbers the spill of s9.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D125962
Kristof Beyls [Fri, 20 May 2022 12:00:53 +0000 (14:00 +0200)]
Minutes for pauth sync-ups have moved to Discourse.
Jay Foad [Fri, 20 May 2022 11:19:59 +0000 (12:19 +0100)]
[AMDGPU] Add a test case for an SIFoldOperands bug
Alexey Katranov [Fri, 20 May 2022 09:03:54 +0000 (11:03 +0200)]
tsan: add lock free stack pattern test
Add a set of tests that iterate over possible combinations of
memory orders for lock free stack implementation.
Reviewed By: dvyukov
Differential Revision: https://reviews.llvm.org/D110552
Luo, Yuanke [Fri, 20 May 2022 10:26:13 +0000 (18:26 +0800)]
[X86][AMX][NFC] Refactor X86LowerAMXCast.cpp
Change static function to X86LowerAMXCast member function.
Differential Revision: https://reviews.llvm.org/D126058
Dmitry Preobrazhensky [Fri, 20 May 2022 10:58:54 +0000 (13:58 +0300)]
[AMDGPU][MC][GFX8+] Correct SMEM offset parsing
Differential Revision: https://reviews.llvm.org/D125907
Alex Zinenko [Thu, 19 May 2022 14:13:51 +0000 (16:13 +0200)]
[mlir] do not elide dialect prefix for ops with dots in the name
For the hypothetical "a.b.c" op printed within a region that declares "a" as
the default dialect, MLIR would currently elide the "a." prefix and only print
"b.c". However, this becomes ambiguous while parsing as "b.c" may be exist as
the "c" op in the "b" dialect. If it does not, the parsing currently fails. Do
not elide the default dialect if the op name contains further dots to avoid the
ambiguity.
See https://discourse.llvm.org/t/dropping-dialect-prefix-for-ops-with-multiple-dots-in-the-name/62562
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D125975
David Green [Fri, 20 May 2022 10:00:34 +0000 (11:00 +0100)]
[ARM] Cost modelling for MVE vector fptoi_sat
Building on top of D125665, this adds MVE costs for fptosi.sat and
fptoui.sat, providing MVE is available and the types are legal.
Differential Revision: https://reviews.llvm.org/D125666
Caroline Concatto [Thu, 12 May 2022 12:19:50 +0000 (13:19 +0100)]
[AArch64][SME]Tied up ZA operand for accumulate instructions
This patch updates SMEInstrFormats.td to tie up ZA operand for instructions
that accumulate their results into ZA or use part of ZA as input.
Depends on: D125534
Differential Revision: https://reviews.llvm.org/D125537
Caroline Concatto [Fri, 13 May 2022 10:04:08 +0000 (11:04 +0100)]
[AArch64][SME][NFC] Add implicit operands for SME instructions in the disassembly.
This patch simplifies the switch statement in getInstruction to add
implicit operands (register ZA and Immediate equal to zero)
in the SME operands when disassembly.
The register ZA and the zero immediate can be added by checking the operand
in MCInstDesc.
Differential Revision: https://reviews.llvm.org/D125534
Daniil Dudkin [Fri, 20 May 2022 09:11:36 +0000 (12:11 +0300)]
[flang] Fix use-associated false-positive error
For the program provided as the test case flang fired the following
error:
error: Semantic errors in main.f90
error: 'foo' is not a procedure
This change fixes the error by postponing handling of `UseErrorDetails`
from `CharacterizeProcedure` to a later stage.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D125791
Florian Hahn [Fri, 20 May 2022 08:58:40 +0000 (09:58 +0100)]
[LV] Do not LoopSimplify/LCSSA after generating main vector loop.
At the moment LV runs LoopSimplify and reconstructs LCSSA form after
generating the main vector loop and before generating the epilogue
vector loop.
In practice, this adds a new exit block for the scalar loop because the
middle block now also branches to the original exit block of the scalar
loop. It also requires adding a new LCSSA phi in the newly created exit
block.
This complicates things when modeling exit values in VPlan, because we
would need to update the VPlan for the epilogue loop to update the newly
created LCSSA phi node.
But none of that should be necessary, as all analysis requiring
loop-simplify form is already done at this point and LCSSA form of the
original loop is not broken.
Reviewed By: bmahjour
Differential Revision: https://reviews.llvm.org/D125810
Zi Xuan Wu [Fri, 20 May 2022 08:54:23 +0000 (16:54 +0800)]
[NFC][test] Fix the line num of expected-error for CSKY at builtin-alloca-with-align.c
David Green [Fri, 20 May 2022 08:31:00 +0000 (09:31 +0100)]
[AArch64] Fix the generation of BE Nops
Big endian Nops were being generated as d5 03 20 1f fnmadd s21, s30,
s0, s0, getting the bytes of the NOP in the wrong order. This switches
the bytes to not be dependant on the endianness.
Differential Revision: https://reviews.llvm.org/D125980
Jon Chesterfield [Fri, 20 May 2022 07:50:36 +0000 (08:50 +0100)]
[amdgpu] Add amdgpu_kernel calling conv attribute to clang
Allows emitting define amdgpu_kernel void @func() IR from C or C++.
This replaces the current workflow which is to write a stub in opencl that
calls an external C function implemented in C++ combined through llvm-link.
Calling the resulting function still requires a manual implementation of the
ABI from the host side. The primary application is for more rapid debugging
of the amdgpu backend by permuting a C or C++ test file instead of manually
updating an IR file.
Implementation closely follows D54425. Non-amd reviewers from there.
Reviewed By: yaxunl
Differential Revision: https://reviews.llvm.org/D125970
Serge Pavlov [Sun, 15 May 2022 15:35:46 +0000 (22:35 +0700)]
Make CompoundStmtBitfields::NumStmts not a bit-field
Number of statements in CompoundStmt is kept in a bit-field of the common
part of Stmt. The field has 24 bits for the number. To allocate a new
bit field (as attempted in https://reviews.llvm.org/D123952), this
number must be reduced, maximal number of statements in a compound
statement becomes smaller. It can result in compilation errors of some
programs.
With this change the number of statements is kept in a field of type
'unsigned int' rather than in bit-field. To make room in CompoundStmtBitfields
LBraceLoc is moved to fields of CompoundStmt.
Differential Revision: https://reviews.llvm.org/D125635
Peixin-Qiao [Fri, 20 May 2022 07:16:03 +0000 (15:16 +0800)]
[flang][OpenMP] Fix the types of worksharing-loop variables
The types of lower bound, upper bound, and step are converted into the
type of the loop variable if necessary. OpenMP runtime requires 32-bit
or 64-bit loop variables. OpenMP loop iteration variable cannot have
more than 64 bits size and will be narrowed.
This patch is part of upstreaming code from the fir-dev branch of
https://github.com/flang-compiler/f18-llvm-project. (#1256)
Co-authored-by: kiranchandramohan <kiranchandramohan@gmail.com>
Reviewed By: kiranchandramohan, shraiysh
Differential Revision: https://reviews.llvm.org/D125740
jacquesguan [Wed, 27 Apr 2022 07:20:31 +0000 (07:20 +0000)]
[RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions.
This patch adds VL patterns for vector widening floating-point fused multiply-add instructions to support fixed length vector type.
Differential Revision: https://reviews.llvm.org/D124505
eopXD [Fri, 20 May 2022 06:23:34 +0000 (23:23 -0700)]
[RISCV][NFC] Remove `*=` operator for LMULType
LMULType always manipulate on Log2LMUL, let all manipulations go
through LMULType::MulLog2LMUL.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D126042
Ivan Kosarev [Fri, 20 May 2022 04:55:36 +0000 (05:55 +0100)]
[MIR] Provide location of extra instruction operand when diagnosing it.
Also resolves misspelled FileCheck directives caught with D125604.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D125965
Jonas Devlieghere [Thu, 19 May 2022 20:38:18 +0000 (13:38 -0700)]
[lldb] Update test_software_breakpoint_set_and_remove_work for AS
On Apple Silicon the platform arch is arm64 rather than AArch64.
Jonas Devlieghere [Thu, 19 May 2022 20:07:20 +0000 (13:07 -0700)]
[lldb] Fix 'ptsname_r' is only available on macOS 10.13.4 or newer
A deployment target less than 10.13.4 causes an error saying that
'ptsname_r' is only available on macOS 10.13.4 or newer. The current
logic only checks if the symbol is available and doesn't account for the
deployment target. This patch fixes that by adding an availability
check.
Differential revision: https://reviews.llvm.org/D125995
Philip Reames [Fri, 20 May 2022 03:59:26 +0000 (20:59 -0700)]
[RISCV] Add test showing codegen for unaligned loads and stores of scalar types
Julian Lettner [Fri, 20 May 2022 00:46:42 +0000 (17:46 -0700)]
[ASan] Add sleep_before_init flag
Also do a little bit of refactoring instead of just copy&paste.
Differential Revision: https://reviews.llvm.org/D126037
Chenbing Zheng [Fri, 20 May 2022 01:56:33 +0000 (09:56 +0800)]
[InstCombine] [NFC] Use a pattern matcher for ExtractElementInst
Reviewed By: RKSimon, rampitec
Differential Revision: https://reviews.llvm.org/D125857
Vitaly Buka [Fri, 20 May 2022 02:22:02 +0000 (19:22 -0700)]
[lit] Fix setup of sanitizer environment
Not all options were propageted into tests.
Reviewed By: ychen
Differential Revision: https://reviews.llvm.org/D122869
jacquesguan [Thu, 19 May 2022 09:25:22 +0000 (09:25 +0000)]
[mlir][Arithmetic] fold overlapping negf.
This patch folds negf(negf(x)) to x.
Differential Revision: https://reviews.llvm.org/D125955
Bill Wendling [Thu, 19 May 2022 23:57:40 +0000 (16:57 -0700)]
[AArch64] Add support for -fzero-call-used-regs
Support the "-fzero-call-used-regs" option on AArch64. This involves much less
specialized code than the X86 version. Most of the checks can be done with
TableGen.
Reviewed By: nickdesaulniers, MaskRay
Differential Revision: https://reviews.llvm.org/D124836
wren romano [Thu, 19 May 2022 23:00:39 +0000 (16:00 -0700)]
[mlir][sparse] Adding x-macros for OverheadType
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D126026
Sam McCall [Thu, 19 May 2022 08:01:44 +0000 (10:01 +0200)]
[Serialization] Delta encode locations in expansion sloc entries
This is a 1.9% reduction in PCH size in my measurements.
In abbreviated records, VBR6 seems to be slightl better than VBR8 for locations
that may be delta-encoded (i.e. not the first)
Differential Revision: https://reviews.llvm.org/D125952
Alex Brachet [Thu, 19 May 2022 22:57:59 +0000 (22:57 +0000)]
[bazel][libc] Fix bazel build
Differential revision: https://reviews.llvm.org/D126028
wren romano [Thu, 19 May 2022 22:01:23 +0000 (15:01 -0700)]
[mlir][sparse] Factored out a "FATAL" macro for unrecoverable assertion failure
Depends On D126019
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D126022
Bill Wendling [Thu, 19 May 2022 20:45:43 +0000 (13:45 -0700)]
[TableGen] Add generation of argument register lists
There are cases, like with -fzero-call-used-regs, where we need to know
which registers can be used by a certain calling convention. This change
generates a list of registers used by each calling convention defined in
*CallingConv.td.
Calling conventions that use registers conditioned on Swift have those
registers placed in a separate list. This allows us to be flexible about
whether to use the Swift registers or not.
Reviewed By: nickdesaulniers
Differential Revision: https://reviews.llvm.org/D125421
Bill Wendling [Thu, 19 May 2022 22:16:08 +0000 (15:16 -0700)]
Revert "[TableGen] Add generation of argument register lists"
There are build bot failures.
This reverts commit
3fa1b6557d08a148ef853c2a761f1c43e09fef5e.
wren romano [Thu, 19 May 2022 21:04:35 +0000 (14:04 -0700)]
[mlir][sparse] Simplifying closure
By closing over the `rank` itself rather than `this`, we save a method call on each iteration. A minor optimization, but one that adds up.
Depends On D126016
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D126019
wren romano [Thu, 19 May 2022 20:47:36 +0000 (13:47 -0700)]
[mlir][sparse] Using the name "dimSizes" more consistently
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D126016
Bill Wendling [Thu, 19 May 2022 20:45:43 +0000 (13:45 -0700)]
[TableGen] Add generation of argument register lists
There are cases, like with -fzero-call-used-regs, where we need to know
which registers can be used by a certain calling convention. This change
generates a list of registers used by each calling convention defined in
*CallingConv.td.
Calling conventions that use registers conditioned on Swift have those
registers placed in a separate list. This allows us to be flexible about
whether to use the Swift registers or not.
Reviewed By: nickdesaulniers
Differential Revision: https://reviews.llvm.org/D125421
python3kgae [Tue, 17 May 2022 23:57:18 +0000 (16:57 -0700)]
[DirectX backend] When cleanup module flags only remove unused flags.
Only remove dx.valver from module flags when cleanup module flags in DXILTranslateMetadataPass.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D125842
Alex Brachet [Thu, 19 May 2022 21:47:28 +0000 (21:47 +0000)]
[libc] Add strlcat
Differential Revision: https://reviews.llvm.org/D125978
Med Ismail Bennani [Thu, 19 May 2022 21:47:04 +0000 (14:47 -0700)]
[lldb/test] Fix PExpect.launch issue when disabling color support
This patch should fix a bug in PExpect.launch that happened when color
support is not enabled.
In that case, we need to add the `--no-use-colors` flag to lldb's launch
argument list. However, previously, each character to the string was
appended separately to the `args` list. This patch solves that by adding
the whole string to the list.
This should fix the TestIOHandlerResize failure on GreenDragon.
Differential Revision: https://reviews.llvm.org/D126021
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Craig Topper [Thu, 19 May 2022 21:33:02 +0000 (14:33 -0700)]
Revert "[RISCV] Add test cases showing failure to remove mask on rotate amounts."
This reverts commit
e2f410feeab27a8bb2c015fc02bb8527702e401f.
This exposes a pre-existing bug in type legalization that is failing
expensive checks.
Craig Topper [Thu, 19 May 2022 21:32:15 +0000 (14:32 -0700)]
Revert "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates."
This reverts commit
86f7d7074a0129955aa2f5c82fe8c383eb17a35a.
The test cases added for this exposed an pre-existing bug that is failing
the expensive checks bot. Reverting so I can revert that patch.
Alexander Shaposhnikov [Thu, 19 May 2022 20:25:47 +0000 (20:25 +0000)]
[ConstantRange] Improve the implementation of binaryOr
This diff adjusts binaryOr to take advantage of the analysis
based on KnownBits.
Differential revision: https://reviews.llvm.org/D125933
Test plan:
1/ ninja check-llvm
2/ ninja check-llvm-unit
Jorge Gorbe Moya [Thu, 19 May 2022 21:17:36 +0000 (14:17 -0700)]
[bazel] Add lib/Basic/BuiltinTargetFeatures.h to clang:basic `hdrs`.
This header is included by
clang/unittests/CodeGen/CheckTargetFeaturesTest.cpp
so it needs to be exposed here to make it visible.
Kiran Chandramohan [Thu, 19 May 2022 20:23:04 +0000 (20:23 +0000)]
[Flang][OpenMP] Upstream the lowering of the parallel do combined construct
When parallel is used in a combined construct, then use a separate
function to create the parallel operation. It handles the parallel
specific clauses and leaves the rest for handling at the inner
operations.
Reviewed By: peixin, shraiysh
Differential Revision: https://reviews.llvm.org/D125465
Co-authored-by: Sourabh Singh Tomar <SourabhSingh.Tomar@amd.com>
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Valentin Clement <clementval@gmail.com>
Co-authored-by: Nimish Mishra <neelam.nimish@gmail.com>
Nicolas Capens [Thu, 19 May 2022 20:46:49 +0000 (13:46 -0700)]
Handle instrumentation of scalar single-precision (_ss) intrinsics
Instrumentation of scalar double-precision intrinsics such as
x86_sse41_round_sd was already handled by https://reviews.llvm.org/D82398,
but not their single-precision counterparts.
https://issuetracker.google.com/
172238865
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D124871
Aart Bik [Thu, 19 May 2022 19:23:52 +0000 (12:23 -0700)]
[mlir][sparse] fix unsigned comparison bug in assert
Reviewed By: bixia, wrengr
Differential Revision: https://reviews.llvm.org/D126007
Jay Foad [Thu, 19 May 2022 15:52:41 +0000 (16:52 +0100)]
[AMDGPU] Mark s_get_waveid_in_workgroup as not reading memory
It is already marked as having side effects, at least in MIR. It does
not interact with anything else that is modelled as a memory access
either in IR or MachineIR.
Differential Revision: https://reviews.llvm.org/D125985
Jay Foad [Thu, 19 May 2022 12:43:43 +0000 (13:43 +0100)]
[AMDGPU] Mark s_getreg as having side effects instead of reading memory
s_getreg does not interact with anything else that is modelled as a
memory access either in IR or MachineIR.
Differential Revision: https://reviews.llvm.org/D125968
Stella Stamenova [Thu, 19 May 2022 19:51:37 +0000 (12:51 -0700)]
[mlir] Remove unused properties from the standalone example's lit configuration
Since these are unused, I've removed them from the configuration, so that it can be easier to read and follow.
Reviewed By: stellaraccident
Differential Revision: https://reviews.llvm.org/D125132
Jennifer Yu [Tue, 17 May 2022 21:17:32 +0000 (14:17 -0700)]
[Clang][[OpenMP5.1] Initial parser/sema for default(private) clause
This implements the default(private) clause as defined in OMP5.1
Differential Revision: https://reviews.llvm.org/D125912
Florian Hahn [Thu, 19 May 2022 19:36:46 +0000 (20:36 +0100)]
[LV] Drop wrap flags for reductions using VP def-use chain.
Update clearReductionWrapFlags to use the VPlan def-use chain from the
reduction phi recipe to drop reduction wrap flags.
This addresses an existing FIXME and fixes a crash when instructions in
the reduction chain are not used and have been removed before VPlan
codegeneration.
Fixes #55540.
Nico Weber [Thu, 19 May 2022 19:18:56 +0000 (15:18 -0400)]
[gn build] (manually) port
505ddb6b7450 (remove Unit/lit.site.cfg.py)
Keith Smiley [Thu, 12 May 2022 00:12:03 +0000 (17:12 -0700)]
[lld][test] Delete empty Unit test directory
This became empty when we removed the legacy macho lld. This results in
a warning when running `check-lld`. We can revert this in the future if
we want unit tests.
Differential Revision: https://reviews.llvm.org/D125436
Nico Weber [Thu, 19 May 2022 19:05:30 +0000 (15:05 -0400)]
Revert "[ValueTracking] Added support to deduce PHI Nodes values being a power of 2"
This reverts commit
d5c130f17e503e128b8a413c2ce0e522987d2a16.
Breaks tests, see https://reviews.llvm.org/D125332#3525819
Jonathan Peyton [Thu, 19 May 2022 18:57:02 +0000 (13:57 -0500)]
[OpenMP][libomp] Fix accidental removal of else for core attributes
David Green [Thu, 19 May 2022 18:53:21 +0000 (19:53 +0100)]
[ARM] Cost modelling for scalar fptoi_sat
Similar to D124357, this adds some cost modelling for fptoi_sat for Arm
targets. Where VFP2 is available (and FP64/FP16 for the relevant types),
the operations are legal as the Arm instructions naturally saturate.
Otherwise they will need an extra smin/smax clamp, similar to AArch64.
Differential Revision: https://reviews.llvm.org/D125665
William Huang [Thu, 12 May 2022 00:32:03 +0000 (00:32 +0000)]
[InstCombine] NEW Baseline tests for InstCombine optimization to merge GEP instructions with constant indices
Splitted the merge constant-indexed GEP optimization into two smaller transformations: 1. Merging GEP of GEP if both are constant-indexed. 2. Swapping constant indexed GEP in a chain of (non-constant) GEP to the end, so that 1 can be applied repeatedly.
There is existing code to partially handle transformation 1, but it only deals with limited cases
Unit tests are breaking down into two parts for the 2 transformations.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D125438
Kristof Beyls [Thu, 19 May 2022 10:25:01 +0000 (12:25 +0200)]
[Office Hours] add initial guidance for hosts
This includes adding guidance to announce an office hours session on the
Discord channel and/or IRC, as discussed at the office hours round table at
EuroLLVM 2022, see
https://discourse.llvm.org/t/office-hours-eurollvm-round-table-summary/62480.
Fixes #55423
William Huang [Tue, 10 May 2022 19:47:10 +0000 (19:47 +0000)]
[ValueTracking] Added support to deduce PHI Nodes values being a power of 2
Add Value Tracking support to deduce induction variable being a power of 2, allowing urem optimizations
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D125332
Keith Smiley [Thu, 19 May 2022 18:29:37 +0000 (11:29 -0700)]
[llvm-dis][test] Fix error case on Windows
The `N` case in the error differs across platforms.
William Huang [Tue, 3 May 2022 22:19:01 +0000 (22:19 +0000)]
[ValueTracking] Baseline tests for Power-of-2 value tracking on PHI nodes
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D124885
Joseph Huber [Thu, 19 May 2022 18:18:51 +0000 (14:18 -0400)]
[Libomptarget] Add `leaf` attribute to `vprintf` declaration
Summary:
This patch adds the `leaf` attribute to the `vprintf` declaration in the
OpenMP runtime. This attribute allows us to determine that the `vprintf`
function will not call any functions within the translation unit,
allowing us to deduce `norecurse` attributes on the caller.
Heejin Ahn [Fri, 13 May 2022 01:46:53 +0000 (18:46 -0700)]
[WebAssembly] Fix register use-def in FixIrreducibleControlFlow
FixIrreducibleControlFlow pass adds dispatch blocks with a `br_table`
that has multiple predecessors and successors, because it serves as
something like a traffic hub for BBs. As a result of this, there can be
register uses that are not dominated by a def in every path from the
entry block. For example, suppose register %a is defined in BB1 and used
in BB2, and there is a single path from BB1 and BB2:
```
BB1 -> ... -> BB2
```
After FixIrreducibleControlFlow runs, there can be a dispatch block
between these two BBs:
```
BB1 -> ... -> Dispatch -> ... -> BB2
```
And this dispatch block has multiple predecessors, now
there is a path to BB2 that does not first visit BB1, and in that path
%a is not dominated by a def anymore.
To fix this problem, we have been adding `IMPLICIT_DEF`s to all
registers in PrepareForLiveInternals pass, and then remove unnecessary
ones in OptimizeLiveIntervals pass after computing `LiveIntervals`. But
FixIrreducibleControlFlow pass itself ends up violating register use-def
relationship, resulting in invalid code. This was OK so far because
MIR verifier apparently didn't check this in validation. But @arsenm
fixed this and it caught this bug in validation
(https://github.com/llvm/llvm-project/issues/55249).
This CL moves the `IMPLICIT_DEF` adding routine from
PrepareForLiveInternals to FixIrreducibleControlFlow. We only run it
when FixIrreducibleControlFlow changes the code. And then
PrepareForLiveInternals doesn't do anything other than setting
`TracksLiveness` property, which is a prerequisite for running
`LiveIntervals` analysis, which is required by the next pass
OptimizeLiveIntervals.
But in our backend we don't seem to do anything that invalidates this up
until OptimizeLiveIntervals, and I'm not sure why we are calling
`invalidateLiveness` in ReplacePhysRegs pass, because what that pass
does is to replace physical registers with virtual ones 1-to-1. I
deleted the `invalidateLiveness` call there and we don't need to set
that flag explicitly, which obviates all the need for
PrepareForLiveInternals.
(By the way, This 'Liveness' here is different from `LiveIntervals`
analysis. Setting this only means BBs' live-in info is correct, all uses
are dominated by defs, `kill` flag is conservatively correct, which
means if there is a `kill` flag set it should be the last use. See
https://github.com/llvm/llvm-project/blob/
2a0837aab1489c88efb03784e34c4dc9f2e28302/llvm/include/llvm/CodeGen/MachineFunction.h#L125-L134
for details.)
So this CL removes PrepareForLiveInternals pass altogether. Something
similar to this was attempted by D56091 long ago but that came short of
actually removing the pass, and I couldn't land it because
FixIrreducibleControlFlow violated use-def relationship, which this CL
fixes.
This doesn't change output in any meaningful way. All test changes
except `irreducible-cfg.mir` are register numbering.
Also this will likely to reduce compilation time, because we have been
adding `IMPLICIT_DEF` for all registers every time `-O2` is given, but
now we do that only when there is irreducible control flow, which is
rare.
Fixes https://github.com/llvm/llvm-project/issues/55249.
Reviewed By: dschuff, kripken
Differential Revision: https://reviews.llvm.org/D125515
Heejin Ahn [Fri, 13 May 2022 02:30:55 +0000 (19:30 -0700)]
[WebAssembly] Use CHECK-NEXT for irreducible-cfg.mir
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D125514
Keith Smiley [Tue, 15 Mar 2022 04:50:46 +0000 (21:50 -0700)]
[llvm-dis] Improve missing file error message
Previously the error message didn't include the failing path, which made
it hard to tell what went wrong.
Differential Revision: https://reviews.llvm.org/D121665
Keith Smiley [Wed, 23 Mar 2022 23:29:07 +0000 (16:29 -0700)]
[docs][tools] Remove old llvm-bcanalyzer options
These no longer exist. A few have been added since but I'm not enough of
an expert to provide a useful blurb on them outside of what you see with
`--help`.
Differential Revision: https://reviews.llvm.org/D122361
Keith Smiley [Wed, 4 May 2022 01:43:46 +0000 (18:43 -0700)]
[Object] Fix updating darwin archives
When creating an archive, llvm-ar looks at the host to determine the
archive format to use, on Apple platforms this means it uses the
K_DARWIN format. K_DARWIN is _virtually_ equivalent to K_BSD, expect for
some very slight differences around padding, timestamps in deterministic
mode, and 64 bit formats. When updating an archive using llvm-ar, or
llvm-objcopy, Archive would try to determine the kind, but it was not
possible to get K_DARWIN in the initialization of the archive, because
they're virtually inciting usable from K_BSD, especially since the
slight differences only apply in very specific cases. This leads to
linker failures when the alignment workaround is not applied to an
archive copied with llvm-objcopy. This change teaches Archive to infer
the K_DARWIN type in the cases where it's possible and the first object
in the archive is a macho object. This avoids using the host triple to
determine this to not affect cross compiling.
Ideally we would eliminate the separate K_DARWIN type entirely since
it's not a truly separate archive type, but then we'd have to force the
macho workarounds on the BSD format generally. This might be acceptable
but then it would be unclear how to handle this case without forcing the
K_DARWIN64 format on all BSD users:
```
if (LastOffset >= Sym64Threshold) {
if (Kind == object::Archive::K_DARWIN)
Kind = object::Archive::K_DARWIN64;
else
Kind = object::Archive::K_GNU64;
}
```
The logic used to determine if the object is macho is derived from the
logic llvm-ar uses.
Previous context:
-
111cd669e90e5b2132187d36f8b141b11a671a8b
-
23a76be5adcaa768ba538f8a4514a7afccf61988
Differential Revision: https://reviews.llvm.org/D124895
Lang Hames [Thu, 19 May 2022 02:19:57 +0000 (19:19 -0700)]
[ORC] Avoid more SymbolStringPtr copies.
Lang Hames [Thu, 19 May 2022 01:58:14 +0000 (18:58 -0700)]
[ORC] Add a FIXME.
Lang Hames [Thu, 19 May 2022 01:39:33 +0000 (18:39 -0700)]
[ORC] Add missing std::moves, pass SymbolLookupSet by value.
Avoids some unnecessary SymbolStringPtr copies.