Lionel Landwerlin [Wed, 2 May 2018 16:51:03 +0000 (17:51 +0100)]
intel: fix aubinator include
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to common/")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 2 May 2018 00:16:06 +0000 (17:16 -0700)]
i965: Reuse batch decoder infrastructure rather than open coding it.
With the new callback, Jason's newer batch decoder infrastructure
should be able to do just as well as the old open coded INTEL_DEBUG=bat
handling, with much less code. If there are any limitations, we'd like
to improve the common code rather than doing one-off hacks here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Wed, 2 May 2018 04:49:17 +0000 (21:49 -0700)]
intel: Give the batch decoder a callback to ask about state size.
Given an arbitrary batch, we don't always know what the size of certain
things are, such as how many entries are in a binding table. But it's
easy for the driver to track that information, so with a simple callback
we can calculate this correctly for INTEL_DEBUG=bat.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Wed, 2 May 2018 00:27:08 +0000 (17:27 -0700)]
intel: Move batch decoder/disassembler from tools/ to common/
Making these part of libintel_common allows us to use them in the DRI
driver. The standalone tool binaries already link against the common
library, too, so it's no harder for them.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Fri, 13 Apr 2018 22:35:56 +0000 (15:35 -0700)]
i965: Allocate shadow batches to explicitly be the BO size.
This unfortunately makes it malloc/realloc on every new batch, rather
than once at startup. But it ensures that the shadow buffer's size will
absolutely match the BO size. Otherwise, as we tune BATCH_SZ/STATE_SZ
or bufmgr cache bucket sizes, we may get a BO size that's rounded up,
and fail to allocate the shadow buffer large enough.
This doesn't fix any bugs today, as BATCH_SZ/STATE_SZ are the size of
a cache bucket, but it's better to be safe than sorry.
Reported-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Lionel Landwerlin [Tue, 1 May 2018 23:17:19 +0000 (00:17 +0100)]
intel: batch-decoder: iterate VERTEX_BUFFER_STATE fields
The gen_field_iterator only iterates the fields of a given gen_group.
If we want to iterate the fields of another gen_group contained as
field, we need to do it manually.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 23:13:39 +0000 (00:13 +0100)]
intel: decoder: fix starting dword of struct fields
Struct fields might span several dwords, but iter_dword is incremented
up to the last dword of the current field before we print out the
struct's fields. We can't use iter_dword for computing the offset into
the pointer of data to decode.
v2: Fix displayed offset number (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 21:18:11 +0000 (22:18 +0100)]
intel: decoder: document when fields should be used
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 21:14:12 +0000 (22:14 +0100)]
intel: decoder: identify groups with fixed length
<register> & <struct> elements always have fixed length. The
get_length() method implies that we're dealing with an instruction in
which the length is encoded into the variable data but the field
iterator uses it without checking what kind of gen_group it is dealing
with.
Let's make get_length() report the correct length regardless of the
gen_group (register, struct or instruction).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 21:12:56 +0000 (22:12 +0100)]
intel: decoder: make the field iterator use more natural
while (iter_next()) { ... }
instead of
do { ... } while (iter_next());
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Vlad Golovkin [Mon, 16 Apr 2018 20:50:24 +0000 (23:50 +0300)]
nv50: Extract needed value bits without shifting them before calling bitcount
This can save one instruction since bitcount doesn't care about specific
bits' positions.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Antia Puentes [Sat, 28 Apr 2018 12:09:22 +0000 (14:09 +0200)]
intel: activate the gl_BaseVertex lowering
Surplus code related to the basevertex is removed.
The Vertex Elements contain now:
* VE 1: <firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is_indexed_draw, 0, 0>
Also fixes unreachable message.
Fixes OpenGL CTS tests:
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters
Fixes Piglit tests:
* arb_shader_draw_parameters-drawid-indirect baseinstance
* arb_shader_draw_parameters-basevertex
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
Antia Puentes [Sat, 28 Apr 2018 12:09:21 +0000 (14:09 +0200)]
compiler/nir: Add conditional lowering for gl_BaseVertex
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Antia Puentes [Sat, 28 Apr 2018 12:09:20 +0000 (14:09 +0200)]
intel: emit is_indexed_draw in the same VE than gl_DrawID
The Vertex Elements are now:
* VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is-indexed-draw, 0, 0>
VE1 is it kept as it was before, VE2 additionally contains the new
system value.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Antia Puentes [Sat, 28 Apr 2018 12:09:19 +0000 (14:09 +0200)]
intel/compiler: Add uses_is_indexed_draw flag
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Antia Puentes [Sat, 28 Apr 2018 12:09:18 +0000 (14:09 +0200)]
compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsics
This VS system value contains if the draw command used to start the
rendering was an indexed draw command or a non-indexed one
(~0/0 respectively). Useful to calculate the gl_BaseVertex as:
(SYSTEM_VALUE_IS_INDEXED_DRAW & SYSTEM_VALUE_FIRST_VERTEX).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Tue, 24 Apr 2018 15:06:19 +0000 (17:06 +0200)]
radv: enable out-of-order rasterization by default
As the implementation is conservative, we can now enable it
by default. It can be disabled with RADV_DEBUG=nooutoforder.
Don't expect much more than 1% of improvements, but the gain
seems consistent.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 24 Apr 2018 15:06:18 +0000 (17:06 +0200)]
radv: only disable out-of-order rast for perfect occlusion queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Wed, 2 May 2018 06:03:00 +0000 (23:03 -0700)]
i965: Drop unused gen5 sampler default color struct.
Trivial.
Kenneth Graunke [Wed, 2 May 2018 06:02:16 +0000 (23:02 -0700)]
i965: Make brw_vs_outputs_written static.
Drop a prototype. Trivial.
Nanley Chery [Sat, 24 Feb 2018 09:26:20 +0000 (01:26 -0800)]
i965/tex_image: Avoid the ASTC LDR workaround on gen9lp
Both the internal documentation and the results of testing this in the
CI suggest that this is unnecessary. Add the fixes tag because this
reduces an internal benchmark's startup time by about 17 seconds
(reported by Eero).
Fixes:
710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values"
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 1 May 2018 20:07:21 +0000 (13:07 -0700)]
freedreno: Fix ir3_cmdline.c build.
Fixes:
6487e7a30c9e ("nir: move GL specific passes to src/compiler/glsl")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Jason Ekstrand [Tue, 1 May 2018 16:59:24 +0000 (09:59 -0700)]
anv: Allow lookup of vkEnumerateInstanceVersion without an instance
Fixes:
cbab2d1da5edfe9df27a010adf8b1aa9dbee473b
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Mon, 30 Apr 2018 22:15:37 +0000 (15:15 -0700)]
anv: Don't advertise Float64 or Int64 on HW without 64-bit types
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Samuel Pitoiset [Fri, 27 Apr 2018 08:53:13 +0000 (10:53 +0200)]
radv: compute the number of subpass attachments correctly
Only count color attachments twice if resolves are used, also
account for the depth stencil attachment if present.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Tue, 1 May 2018 02:32:02 +0000 (12:32 +1000)]
radv: set fmask_surf_index on fmask surfaces.
This is needed for gfx9 and later for all fmask surface index.
(Mentioned by Marek on irc)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Brian Paul [Tue, 1 May 2018 15:51:45 +0000 (09:51 -0600)]
gallium/i915: fix PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE typo
Fixes:
fffe5e2d14f807c ("gallium: add initial support for conservative
rasterization")
Trivial.
Rhys Perry [Sat, 7 Apr 2018 22:15:00 +0000 (16:15 -0600)]
nvc0: add conservative rasterization support
Subpixel precision bias, dilation and the post-snap mode are supported on
GM200 and newer. The pre-snap mode is supported for triangle primitives on
GP100.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rhys Perry [Fri, 27 Apr 2018 14:43:00 +0000 (08:43 -0600)]
st/mesa: add support for nvidia conservative rasterization extensions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Rhys Perry [Sat, 7 Apr 2018 22:15:00 +0000 (16:15 -0600)]
gallium: add initial support for conservative rasterization
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rhys Perry [Fri, 27 Apr 2018 17:35:00 +0000 (11:35 -0600)]
mesa: add support for nvidia conservative rasterization extensions
Although the specs are written against compatibility GL 4.3 and allows core
profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 26 Apr 2018 17:55:46 +0000 (11:55 -0600)]
glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statements
To silence warnings about unhandled switch values.
Untested otherwise.
v2: move the INT/UINT8 cases after the INT/UINT16 cases, per Eric.
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Thu, 26 Apr 2018 17:55:16 +0000 (11:55 -0600)]
tgsi: use enums instead of unsigned in ureg code
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Timothy Arceri [Mon, 30 Apr 2018 10:39:43 +0000 (20:39 +1000)]
nir: move GL specific passes to src/compiler/glsl
With this we should have no passes in src/compiler/nir with any
dependencies on headers from core GL Mesa.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Andres Rodriguez [Mon, 30 Apr 2018 22:05:49 +0000 (18:05 -0400)]
radv/winsys: fix leaking resources from bo's imported by fd
A bo's ref_count was not being initialized when imported from an fd.
Therefore, we would fail to free the resource during VkFreeMemory().
This patch fixes applications like hifi VR in threaded mode, which
perform frequent imports/releases of IPC shared memory.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Scott D Phillips [Mon, 30 Apr 2018 17:25:47 +0000 (10:25 -0700)]
i965/tiled_memcpy: ytiled_to_linear a cache line at a time
Similar to the transformation applied to linear_to_ytiled, also align
each readback from the ytiled source to a cacheline (i.e. transfer a
whole cacheline from the source before moving on to the next column).
This will allow us to utilize movntqda (_mm_stream_si128) in a
subsequent patch to obtain near WB readback performance when accessing
the uncached ytiled memory, an order of magnitude improvement.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chris Wilson [Mon, 30 Apr 2018 17:25:46 +0000 (10:25 -0700)]
i965: Record mipmap resolver for unmapping
When mapping a region of the mipmap_tree, record which complementary
method to use to unmap it afterwards. By doing so we can avoid
duplicating the decision tree used when mapping and thereby eliminate
trivial errors that can be introduced if the two if-chains become out of
sync.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:45 +0000 (10:25 -0700)]
i965: Move unmap_depthstencil before map_depthstencil
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:44 +0000 (10:25 -0700)]
i965: Move unmap_etc before map_etc
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:43 +0000 (10:25 -0700)]
i965: Move unmap_s8 before map_s8
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:42 +0000 (10:25 -0700)]
i965: Move unmap_movntdqa before map_movntdqa
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:41 +0000 (10:25 -0700)]
i965: Move unmap_blit before map_blit
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:40 +0000 (10:25 -0700)]
i965: Move unmap_gtt before map_gtt
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Mon, 30 Apr 2018 02:45:14 +0000 (12:45 +1000)]
ac/nir: expand 64-bit vec3 loads to fix shuffling.
If loading 64-bit vec3 values, a 4 component load would be followed
by a 2 component load and the resulting shuffle would fail as it
requires 2 4 components. This just expands the second results
vector out to 4 components.
This fixes 100 CTS tests:
dEQP-VK.spirv_assembly.type.vec3.*64*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Tue, 10 Apr 2018 23:01:50 +0000 (16:01 -0700)]
i965: Don't stomp initial kflags for program cache.
We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any
existing kflags. Today, there are none (as the program cache doesn't
support 48-bit addressing), but once we start using softpin, we'll
need to preserve EXEC_OBJECT_PINNED.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Tue, 10 Apr 2018 08:23:15 +0000 (01:23 -0700)]
i965: Let batchbuffers be placed anywhere in the 48-bit address space.
We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and
accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process.
There's no reason to restrict batch buffers to the lower 4GB.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Scott D Phillips [Thu, 19 Apr 2018 14:54:28 +0000 (07:54 -0700)]
intel: fix check for 48b ppgtt support
The previous logic of the supports_48b_addresses wasn't actually
checking if i915.ko was running with full_48bit_ppgtt. The ENOENT
it was checking for was actually coming from the invalid context
id provided in the test execbuffer. There is no path in the
kernel driver where the presence of
EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error.
Instead, check the default context's GTT_SIZE param for a value
greater than 4 GiB
v2 (Ken): Fix in i965 as well.
v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Leo Liu [Fri, 27 Apr 2018 12:32:41 +0000 (08:32 -0400)]
st/omx/enc: fix blit setup for YUV LoadImage
The blit here involves scaling since it's copying from I8 format to R8G8 format.
Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it
looks that GPU always uses the second half as source. Currently we use "1" as
the start point of x for R, then causing 1 source pixel of U component shift to
right. So "-1" should be the start point for U component.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Juan A. Suarez Romero [Fri, 27 Apr 2018 08:38:09 +0000 (10:38 +0200)]
autotools, meson: bump up required VA version
Due using a new VP9 config we use, required VA API 0.39
Fixes:
413c5ca3727 ("travis: update libva required version")
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Juan A. Suarez Romero [Sat, 28 Apr 2018 17:01:48 +0000 (17:01 +0000)]
docs: update calendar, add news and link release notes to 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:57:30 +0000 (16:57 +0000)]
docs: add sha256 checksums for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
b3eed3ad03fd1eb61474cd0a8a173ad40fb8a876)
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:22:11 +0000 (16:22 +0000)]
docs: add release notes for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
d38da7bd2d4387635fac8bc7f45e64f50dc43c43)
Marek Olšák [Fri, 13 Apr 2018 22:09:11 +0000 (18:09 -0400)]
radeonsi: increase the number of compiler threads depending on the CPU
The compiler queue was limited to 3 threads, so shader-db running
on a 16-thread CPU would have a bottleneck on the 3-thread queue.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 23:55:10 +0000 (19:55 -0400)]
radeonsi: avoid a crash in gallivm_dispose_target_library_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 23:23:55 +0000 (19:23 -0400)]
radeonsi: move data_layout into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 23:13:37 +0000 (19:13 -0400)]
radeonsi: move passmgr into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:43:54 +0000 (18:43 -0400)]
radeonsi: move target_library_info into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:36:58 +0000 (18:36 -0400)]
radeonsi: use si_compiler::triple in si_llvm_optimize_module
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:35:45 +0000 (18:35 -0400)]
radeonsi: add triple into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:26:05 +0000 (18:26 -0400)]
radeonsi: add struct si_compiler containing LLVMTargetMachineRef
It will contain more variables.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:53:25 +0000 (21:53 -0400)]
radeonsi: rename r600_texture::resource to buffer
r600_resource could be renamed to si_buffer.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:52:05 +0000 (21:52 -0400)]
radeonsi: use r600_resource() typecast helper
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:20:53 +0000 (21:20 -0400)]
radeonsi: remove unused atom parameter from si_atom::emit
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:12:24 +0000 (21:12 -0400)]
radeonsi: inline 2 trivial state structures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:07:29 +0000 (21:07 -0400)]
radeonsi: remove function si_init_atom
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:03:51 +0000 (21:03 -0400)]
radeonsi: remove si_atom::id
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 00:54:02 +0000 (20:54 -0400)]
radeonsi: don't use an indirect table for state atoms
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 00:26:14 +0000 (20:26 -0400)]
radeonsi: rename r600_atom -> si_atom
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 00:20:39 +0000 (20:20 -0400)]
radeonsi: remove r600_pipe_common.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 13 Apr 2018 21:15:06 +0000 (17:15 -0400)]
radeonsi/gfx9: workaround for INTERP with indirect indexing
and clean up the conditions.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Marek Olšák [Thu, 12 Apr 2018 01:21:28 +0000 (21:21 -0400)]
radeonsi: rewrite DCC format compatibility checking code
It might be better to use a slow compressed clear when clearing to 1.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Apr 2018 01:43:28 +0000 (21:43 -0400)]
radeonsi: implement DCC fast clear swizzle constraints more accurately
Reduce swizzle constraints to the ALPHA_IS_ON_MSB constraint and the clear
value of 1.
This significantly changes the DCC fast clear code, and fixes fast clear
for RGB formats without alpha.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 11 Apr 2018 15:30:58 +0000 (11:30 -0400)]
radeonsi: rename variables and document stuff around DCC fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 Apr 2018 03:40:26 +0000 (23:40 -0400)]
radeonsi: fully enable 2x DCC MSAA for array and non-array textures
The clear code is exactly the same as for 1 sample buffers -
just clear the whole thing.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 Apr 2018 04:19:50 +0000 (00:19 -0400)]
radeonsi: enable fast color clear for level 0 of mipmapped textures on <= VI
GFX9 is more complicated and needs a compute shader that we should just
copy from amdvlk.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 16 Apr 2018 20:34:56 +0000 (16:34 -0400)]
ac/surface: handle DCC subresource fast clear restriction on VI
v2: require the previous level to be clearable for determining whether
the last unaligned level is clearable
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
George Kyriazis [Tue, 24 Apr 2018 22:03:00 +0000 (17:03 -0500)]
swr/rast: No need to export GetSimdValidIndicesGfx
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 24 Apr 2018 21:44:19 +0000 (16:44 -0500)]
swr/rast: Small editorial changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 24 Apr 2018 16:13:54 +0000 (11:13 -0500)]
swr/rast: Use new processor detection mechanism
Use specific avx512 selection mechanism based on avx512er bit instead of
getHostCPUName(). LLVM 6.0.0 has a bug that reports wrong string for KNL
(fixed in 6.0.1).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 23:14:59 +0000 (18:14 -0500)]
swr/rast: Output rasterizer dir to console since it's process specific
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 23:00:10 +0000 (18:00 -0500)]
swr/rast: Add TranslateGfxAddress for shader
Also add GFX_MEM_CLIENT_SHADER
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 21:34:44 +0000 (16:34 -0500)]
swr/rast: jit PRINT improvements.
Sign-extend integer types to 32bit when specifying "%d" and add new %u
which zero-extends to 32bit. Improves printing of sub 32bit integer types
(i1 specifically).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 21:31:38 +0000 (16:31 -0500)]
swr/rast: Fix regressions.
Bump jit cache revision number to force recompile.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 16:22:50 +0000 (11:22 -0500)]
swr/rast: Cleanup old cruft.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 20 Apr 2018 18:29:39 +0000 (13:29 -0500)]
swr/rast: Package events.proto with core output
However only if the file exists in DEBUG_OUTPUT_DIR. The expectation is
that AR rasterizerLauncher will start placing it there when launching
a workload (which is in a subsequent checkin)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 19 Apr 2018 22:59:08 +0000 (17:59 -0500)]
swr/rast: Fix init in EventHandlerWorkerStats
Make sure we initialize variables.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 19 Apr 2018 18:15:31 +0000 (13:15 -0500)]
swr/rast: Fix return type of VCVTPS2PH.
expecting <8xi16> return.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 18 Apr 2018 20:17:04 +0000 (15:17 -0500)]
swr/rast: WIP Translation handling
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 17 Apr 2018 04:18:28 +0000 (23:18 -0500)]
swr/rast: Use different handing for stream masks
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 16 Apr 2018 23:54:45 +0000 (18:54 -0500)]
swr/rast: Silence warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Sun, 15 Apr 2018 16:57:47 +0000 (11:57 -0500)]
swr/rast: Add support for TexelMask evaluation
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Sat, 14 Apr 2018 08:34:44 +0000 (03:34 -0500)]
swr/rast: Internal core change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 13 Apr 2018 21:21:24 +0000 (16:21 -0500)]
swr/rast: Fix x86 lowering 64-bit float handling
- 64-bit cvt-to-float needs to be explicitly handled
- gathers need the right parameter types to work with doubles
Fixes draw-vertices piglit tests
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 13 Apr 2018 21:14:42 +0000 (16:14 -0500)]
swr/rast: Add some SIMD_T utility functors
VecEqual and VecHash
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 12 Apr 2018 18:10:05 +0000 (13:10 -0500)]
swr/rast: Fix wrong type allocation
ALLOCA pointer elements, not pointers.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 24 Apr 2018 18:29:41 +0000 (13:29 -0500)]
swr: touch generated files to update timestamp
previous change in generators necessitates this change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 10 Apr 2018 23:43:31 +0000 (18:43 -0500)]
swr/rast: Fix byte offset for non-indexed draws
for the case when USE_SIMD16_SHADERS == FALSE
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Marek Olšák [Tue, 24 Apr 2018 21:01:35 +0000 (17:01 -0400)]
util/u_queue: fix a deadlock in util_queue_finish
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dylan Baker [Thu, 26 Apr 2018 17:20:57 +0000 (10:20 -0700)]
meson: fix race condition revealed by using 0.44
Previously there was a special target that blocked for the generation of
anv_entrypoints.h, with meson 0.44 we don't need this, we can use a new
language feature instead. The problem is that previously that blocking
target would hide a race condition for the generation of another header,
anv_extensions.h. Now the build sometimes fails when anv_extensions.h is
not generated in time.
v2: - clarify the race condition in the commit message (Emil)
CC: Mark Janes <mark.a.janes@intel.com>
Fixes:
92550d9b16d2b295bdac087f31b1fd6d0f808e02
("meson: remove workaround for custom target creating .h and .c files")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Thu, 26 Apr 2018 17:44:00 +0000 (10:44 -0700)]
bin: force git show to use default pretty setting
I have pretty default to short, which breaks this script.
v2: - Fix both places that don't define a --pretty (Emil)
cc: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>