John McCall [Mon, 12 Oct 2020 05:09:25 +0000 (01:09 -0400)]
Revert "[SYCL] Implement __builtin_unique_stable_name."
This reverts commit
b5a034e771d0e4d7d8e71fc545b230d98e5a1f42.
This feature was added without following the proper process.
Fangrui Song [Sun, 11 Oct 2020 22:51:55 +0000 (15:51 -0700)]
[SchedDAGInstrs] Delete redundant contains(). NFC
Jonas Devlieghere [Mon, 12 Oct 2020 03:14:00 +0000 (20:14 -0700)]
Revert "PR47792: Include the type of a pointer or reference non-type template"
This reverts commit
849c60541b630ddf8cabf9179fa771b3f4207ec8 because it
results in a stage 2 build failure:
llvm-project/clang/include/clang/AST/ExternalASTSource.h:409:20: error:
definition with same mangled name
'_ZN5clang25LazyGenerationalUpdatePtrIPKNS_4DeclEPS1_XadL_ZNS_17ExternalASTSource19CompleteRedeclChainES3_EEE9makeValueERKNS_10ASTContextES4_'
as another definition
static ValueType makeValue(const ASTContext &Ctx, T Value);
Qiu Chaofan [Mon, 12 Oct 2020 02:40:19 +0000 (10:40 +0800)]
[NFC] Move PPC strict-fp MIR test to dedicated file
fp-strict-conv-f128.ll is generated by script, but some manual MIR tests
exist in it. Move them to another file to satisfy script when updating.
Valentin Clement [Mon, 12 Oct 2020 01:26:54 +0000 (21:26 -0400)]
[mlir][openacc] Introduce acc.enter_data operation
This patch introduces the acc.enter_data operation that represents an OpenACC Enter Data directive.
Operands and attributes are dervied from clauses in the spec 2.6.6.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D88941
Richard Smith [Sun, 11 Oct 2020 22:57:52 +0000 (15:57 -0700)]
PR47792: Include the type of a pointer or reference non-type template
parameter in its notion of template argument identity.
We already did this for all the other kinds of non-type template
argument. We're still missing the type from the mangling, so we continue
to be able to see collisions at link time; that's an open ABI issue.
Craig Topper [Sun, 11 Oct 2020 20:31:15 +0000 (13:31 -0700)]
[ValueTracking] Use KnownBits::countMaxLeadingZeros/countMaxTrailingZeros to make code more readable. NFC
Richard Smith [Sun, 11 Oct 2020 21:20:01 +0000 (14:20 -0700)]
Fix arc lint's clang-format rule: only format the file we were asked to format.
This avoids diffs being applied in the work tree to files that are
supposed to be excluded (clang tests), allows arc to properly provide
interactive feedback for the formatting fixes, and reduces the number of
files that we format, in a change affecting N files, from N^2 to N.
Christian Iversen [Sun, 11 Oct 2020 21:19:25 +0000 (14:19 -0700)]
[ELF] Fix broken bitstream linking with lld when e_machine > 255
In ELF/InputFiles.cpp, getBitcodeMachineKind() is limited to uint8_t return
type. This works as long as EM_xxx is < 256, which is true for common
architectures, but not for some newly assigned or unofficial EM_* values.
The corresponding ELF field (e_machine) can hold uint16_t.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D89185
Tres Popp [Fri, 9 Oct 2020 14:45:50 +0000 (16:45 +0200)]
[mlir] Type erase inputs to select statements in shape.broadcast lowering.
This is required or broadcasting with operands of different ranks will lead to
failures as the select op requires both possible outputs and its output type to
be the same.
Differential Revision: https://reviews.llvm.org/D89134
Nathan Ridge [Sat, 5 Sep 2020 23:22:59 +0000 (19:22 -0400)]
[clangd] Avoid relations being overwritten in a header shard
Fixes https://github.com/clangd/clangd/issues/510
Differential Revision: https://reviews.llvm.org/D87256
Roman Lebedev [Sun, 11 Oct 2020 17:17:09 +0000 (20:17 +0300)]
[InstCombine] combineLoadToOperationType(): don't fold int<->ptr cast into load
And another step towards transforms not introducing inttoptr and/or
ptrtoint casts that weren't there already.
As we've been establishing (see D88788/D88789), if there is a int<->ptr cast,
it basically must stay as-is, we can't do much with it.
I've looked, and the most source of new such casts being introduces,
as far as i can tell, is this transform, which, ironically,
tries to reduce count of casts..
On vanilla llvm test-suite + RawSpeed, @ `-O3`, this results in
-33.58% less `IntToPtr`s (19014 -> 12629)
and +76.20% more `PtrToInt`s (18589 -> 32753),
which is an increase of +20.69% in total.
However just on RawSpeed, where i know there are basically
none `IntToPtr` in the original source code,
this results in -99.27% less `IntToPtr`s (2724 -> 20)
and +82.92% more `PtrToInt`s (4513 -> 8255).
which is again an increase of 14.34% in total.
To me this does seem like the step in the right direction,
we end up with strictly less `IntToPtr`, but strictly more `PtrToInt`,
which seems like a reasonable trade-off.
See https://reviews.llvm.org/D88860 / https://reviews.llvm.org/D88995
for some more discussion on the subject.
(Eventually, `CastInst::isNoopCast()`/`CastInst::isEliminableCastPair`
should be taught about this, yes)
Reviewed By: nlopes, nikic
Differential Revision: https://reviews.llvm.org/D88979
Fangrui Song [Sun, 11 Oct 2020 05:21:47 +0000 (22:21 -0700)]
[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode
GCC 11 will define this macro.
In LLVM, the feature flag only applies to 64-bit mode and we always define the
macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can
suppress the macro. The discrepancy can unlikely cause trouble.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D89198
David Green [Sun, 11 Oct 2020 15:58:34 +0000 (16:58 +0100)]
[LV] Tail folded inloop reductions.
This expands upon the inloop reductions added in
e9761688e41cb9e976,
allowing them to be inserted into tail folded loops. Reductions are
generates with the form:
x = select(mask, vecop, zero)
v = vecreduce.add(x)
c = add chain, v
Where zero here is chosen as the identity value for add reductions. The
backend is then expected to fold the select and the vecreduce into a
single predicated instruction.
Most of the code is fairly straight forward, except for the creation of
blockmasks which need to ensure they are created in dominance order. The
order they are added is altered to be after any phis, keeping the
requirements for the underlying IR.
Differential Revision: https://reviews.llvm.org/D84451
Zinovy Nis [Sat, 10 Oct 2020 18:32:51 +0000 (21:32 +0300)]
[clang-tidy] Fix crash in readability-function-cognitive-complexity on weak refs
Fix for https://bugs.llvm.org/show_bug.cgi?id=47779
Differential Revision: https://reviews.llvm.org/D89194
Nikita Popov [Sun, 11 Oct 2020 15:07:28 +0000 (17:07 +0200)]
[MemCpyOpt] Add lifetime may alias test (NFC)
Test the case where a lifetime intrinsic may alias the memcpy
source. Other cases test must or no alias.
David Green [Sun, 11 Oct 2020 14:06:21 +0000 (15:06 +0100)]
[LV] Extra predicated inloop reduction tests. NFC
Nikita Popov [Sun, 11 Oct 2020 13:21:49 +0000 (15:21 +0200)]
[MemCpyOpt] Add additional byval tests (NFC)
Test read/write clobbers and the the non-local case.
Sanjay Patel [Sat, 10 Oct 2020 15:08:50 +0000 (11:08 -0400)]
[InstCombine] allow vector splats for add+xor --> shifts
Sanjay Patel [Sat, 10 Oct 2020 14:35:18 +0000 (10:35 -0400)]
[InstCombine] add one-use check to add+xor transform
As shown in the affected test, we could increase instruction
count without this limitation. There's another test with extra
use that shows we still convert directly to a real "sext" if
possible.
Sanjay Patel [Sat, 10 Oct 2020 14:24:15 +0000 (10:24 -0400)]
[InstCombine] add tests with extra uses for add+xor transform; NFC
Sanjay Patel [Sat, 10 Oct 2020 13:50:34 +0000 (09:50 -0400)]
[InstCombine] add/adjust tests for add+xor -> shifts; NFC
Kazushi (Jam) Marukawa [Sun, 11 Oct 2020 10:34:12 +0000 (19:34 +0900)]
[VE][NFC] Clean VEISelLowering.cpp
Clean the order of setOperationActions and others.
Differential Revision: https://reviews.llvm.org/D89203
Simon Pilgrim [Sun, 11 Oct 2020 10:25:22 +0000 (11:25 +0100)]
Fix Wdocumentation warning. NFCI.
Add a space after /param names before any commas otherwise the doxygen parsers get confused.
Simon Pilgrim [Sun, 11 Oct 2020 10:21:23 +0000 (11:21 +0100)]
[X86][SSE2] Use smarter instruction patterns for lowering UMIN/UMAX with v8i16.
This is my first LLVM patch, so please tell me if there are any process issues.
The main observation for this patch is that we can lower UMIN/UMAX with v8i16 by using unsigned saturated subtractions in a clever way. Previously this operation was lowered by turning the signbit of both inputs and the output which turns the unsigned minimum/maximum into a signed one.
We could use this trick in reverse for lowering SMIN/SMAX with v16i8 instead. In terms of latency/throughput this is the needs one large move instruction. It's just that the sign bit turning has an increased chance of being optimized further. This is particularly apparent in the "reduce" test cases. However due to the slight regression in the single use case, this patch no longer proposes this.
Unfortunately this argument also applies in reverse to the new lowering of UMIN/UMAX with v8i16 which regresses the "horizontal-reduce-umax", "horizontal-reduce-umin", "vector-reduce-umin" and "vector-reduce-umax" test cases a bit with this patch. Maybe some extra casework would be possible to avoid this. However independent of that I believe that the benefits in the common case of just 1 to 3 chained min/max instructions outweighs the downsides in that specific case.
Patch By: @TomHender (Tom Hender) ActuallyaDeviloper
Differential Revision: https://reviews.llvm.org/D87236
Simon Pilgrim [Sun, 11 Oct 2020 09:39:51 +0000 (10:39 +0100)]
[InstCombine] Remove accidental unnecessary ConstantExpr qualification added in rGb752daa26b64155
MSVC didn't complain but everything else did....
Simon Pilgrim [Sun, 11 Oct 2020 09:37:20 +0000 (10:37 +0100)]
[InstCombine] matchFunnelShift - fold or(shl(a,x),lshr(b,sub(bw,x))) -> fshl(a,b,x) iff x < bw
If value tracking can confirm that a shift value is less than the type bitwidth then we can more confidently fold general or(shl(a,x),lshr(b,sub(bw,x))) patterns to a funnel/rotate intrinsic pattern without causing bad codegen regressions in the backend (see D89139).
Differential Revision: https://reviews.llvm.org/D88783
Simon Pilgrim [Sun, 11 Oct 2020 09:31:17 +0000 (10:31 +0100)]
[InstCombine] Replace getLogBase2 internal helper with ConstantExpr::getExactLogBase2. NFCI.
This exposes the helper for other power-of-2 instcombine folds that I'm intending to add vector support to.
The helper only operated on power-of-2 constants so getExactLogBase2 is a more accurate name.
Tobias Gysi [Sun, 11 Oct 2020 08:40:28 +0000 (10:40 +0200)]
[mlir] add scf.if op canonicalization pattern that removes unused results
The patch adds a canonicalization pattern that removes the unused results of scf.if operation. As a result, cse may remove unused computations in the then and else regions of the scf.if operation.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D89029
Xun Li [Sun, 11 Oct 2020 05:21:34 +0000 (22:21 -0700)]
[Coroutines] Refactor/Rewrite Spill and Alloca processing
This patch is a refactoring of how we process spills and allocas during CoroSplit.
In the previous implementation, everything that needs to go to the heap is put into Spills, including all the values defined by allocas.
And the way to identify a Spill, is to check whether there exists a use-def relationship that crosses suspension points.
This approach is fundamentally confusing, and unfortunately, incorrect.
First of all, allocas are always process differently than spills, hence it's quite confusing to put them together. It's a much cleaner to separate them and process them separately.
Doing so simplify lots of code and makes the logic more clear and easier to reason about.
Secondly, use-def relationship is insufficient to decide whether a value defined by AllocaInst needs to go to the heap.
There are many cases where a value defined by AllocaInst can implicitly be used across suspension points without a direct use-def relationship.
For example, you can store the address of an alloca into the heap, and load that address after suspension. Or you can escape the address into an object through a function call.
Or you can have a PHINode that takes two allocas, and this PHINode is used across suspension point (when this happens, the existing implementation will spill the PHINode, a.k.a a stack adddress to the heap!).
All these issues suggest that we need to separate spill and alloca in order to properly implement this.
This patch does not yet fix these bugs, however it sets up the code in a better shape so that we can start fixing them in the next patch.
The core idea of this patch is to add a new struct called FrameDataInfo, which contains all Spills, all Allocas, and a map from each definition to its layout index in the frame (FieldIndexMap).
Spills and Allocas are identified, stored and processed independently. When they are initially added to the frame, we record their field index through FieldIndexMap. When the frame layout is finalized, we update each index into their final layout index.
In doing so, I also cleaned up a few things and also discovered a few other bugs.
Cleanups:
1. Found out that PromiseFieldId is not used, delete it.
2. Previously, SpillInfo is a vector, which is strange because every def can have multiple users. This patch cleans it up by turning it into a map from def to users.
3. Previously, a frame Field struct contains a list of Spills that field corresponds to. This isn't necessary since we only need the layout index for each given definition. This patch removes that list. Instead, we connect each field and definition using the FieldIndexMap.
4. All the loops that process Spills are simplified now because we use a map instead of a vector.
Bugs:
It seems that we are only keeping llvm.dbg.declare intrinsics in the .resume part of the function. The ramp function will no longer has it. This means we are dropping some debug information in the ramp function.
The next step is to start fixing the bugs where the implementation fails to identify some allocas that should live on the frame.
Differential Revision: https://reviews.llvm.org/D88872
Craig Topper [Sun, 11 Oct 2020 04:34:37 +0000 (21:34 -0700)]
[X86] Redefine X86ISD::PEXTRB/W and X86ISD::PINSRB/PINSRW to use a i8 TargetConstant for the immediate instead of a ptr constant.
This is more consistent with other target specific ISD opcodes that
require immediates.
Craig Topper [Sun, 11 Oct 2020 03:11:26 +0000 (20:11 -0700)]
[X86] AMX intrinsics should have ImmArg for the register numbers and use timm in isel patterns.
Craig Topper [Sun, 11 Oct 2020 02:18:02 +0000 (19:18 -0700)]
[X86] Add a X86ISD::BEXTRI to distinquish the case where the control must be a constant.
The bextri intrinsic has a ImmArg attribute which will be converted
in SelectionDAG using TargetConstant. We previously converted this
to a plain Constant to allow X86ISD::BEXTR to call SimplifyDemandedBits
on it.
But while trying to decide if D89178 was safe, I realized that
this conversion of TargetConstant to Constant would be one case
where that would break.
So this patch adds a new opcode specifically for the immediate case.
And then teaches computeKnownBits and SimplifyDemandedBits to also
handle it, but not try to SimplifyDemandedBits on it. To make up
for that, I immediately masked the constant to 16 bits when
converting from the intrinsic node to the X86ISD node.
Krzysztof Parzyszek [Sat, 10 Oct 2020 01:17:50 +0000 (20:17 -0500)]
[Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR
This removes VSPLAT and VZERO. VZERO is now SPLAT_VECTOR of (i32 0).
Included is also a testcase for the previous (target-independent)
commit.
Krzysztof Parzyszek [Sat, 10 Oct 2020 20:37:32 +0000 (15:37 -0500)]
[SDAG] Remember to set UndefElts in isSplatValue for SPLAT_VECTOR
Fangrui Song [Sat, 10 Oct 2020 21:05:48 +0000 (14:05 -0700)]
[X86] Delete redundant 'static' from namespace scope 'static constexpr'. NFC
This decreases 7 lines as the result of packing more bits on one line.
Simon Pilgrim [Sat, 10 Oct 2020 19:28:50 +0000 (20:28 +0100)]
[InstCombine] getLogBase2(undef) -> 0.
Move the undef element handling into the getLogBase2 helper instead of pre-empting with replaceUndefsWith.
Alex Denisov [Sat, 10 Oct 2020 19:22:40 +0000 (21:22 +0200)]
Fix CMake configuration error when run with -Werror/-Wall
The following code doesn't compile
uint64_t i = x.load(std::memory_order_relaxed);
return 0;
when CMAKE_C_FLAGS set to -Werror -Wall, thus incorrectly
breaking the CMake configuration step:
-- Looking for __atomic_load_8 in atomic
-- Looking for __atomic_load_8 in atomic - not found
CMake Error at cmake/modules/CheckAtomic.cmake:79 (message):
Host compiler appears to require libatomic for 64-bit operations, but
cannot find it.
Call Stack (most recent call first):
cmake/config-ix.cmake:360 (include)
CMakeLists.txt:671 (include)
Simon Pilgrim [Sat, 10 Oct 2020 19:09:55 +0000 (20:09 +0100)]
[InstCombine] getLogBase2 - no need to specify Type. NFCI.
In all the getLogBase2 uses, the specified Type is always the same as the constant being folded.
Simon Pilgrim [Sat, 10 Oct 2020 18:13:01 +0000 (19:13 +0100)]
Remove %tmp variables from test cases to appease update_test_checks.py
Simon Pilgrim [Sat, 10 Oct 2020 18:09:58 +0000 (19:09 +0100)]
[PowerPC] ReplaceNodeResults - bail on funnel shifts and let generic legalizers deal with it
Fixes regression raised on D88834 for 32-bit triple + 64-bit cpu cases (which apparently is a thing).
Krzysztof Parzyszek [Sat, 10 Oct 2020 01:16:09 +0000 (20:16 -0500)]
Define splat_vector for ISD::SPLAT_VECTOR in TargetSelectionDAG.td
Martin Storsjö [Sat, 10 Oct 2020 11:33:10 +0000 (14:33 +0300)]
[lldb] [Windows] Remove unused functions. NFC.
These became unused in
51117e3c51754f3732e.
Martin Storsjö [Sat, 10 Oct 2020 11:26:32 +0000 (14:26 +0300)]
[lldb] [Windows] Add missing 'override', silencing warnings. NFC.
Also remove superfluous 'virtual' in overridden methods.
Simon Pilgrim [Sat, 10 Oct 2020 17:18:57 +0000 (18:18 +0100)]
[PowerPC] Add ppc32 funnel shift test coverage
Simon Pilgrim [Sat, 10 Oct 2020 15:28:59 +0000 (16:28 +0100)]
[InstCombine] Add test case showing rotate intrinsic being split by SimplifyDemandedBits
Noticed while triaging regression report on D88834
Michał Górny [Sat, 10 Oct 2020 16:54:52 +0000 (18:54 +0200)]
[lldb] [Process/FreeBSDRemote] Fix double semicolon
Michał Górny [Sat, 10 Oct 2020 07:36:57 +0000 (09:36 +0200)]
[lldb] [Process/FreeBSDRemote] Kill process via PT_KILL
Use PT_KILL to kill the stopped process. This ensures that the process
termination is reported properly and fixes delay/error on killing it.
Differential Revision: https://reviews.llvm.org/D89182
Michał Górny [Sat, 10 Oct 2020 07:23:15 +0000 (09:23 +0200)]
[lldb] [Process/FreeBSD] Mark methods override in RegisterContext*
Differential Revision: https://reviews.llvm.org/D89181
Philip Reames [Sat, 10 Oct 2020 16:48:02 +0000 (09:48 -0700)]
Step down from security group
Resigning from security group as Azul representative as I have left Azul. Previously communicated via email with security group.
Differential Revision: https://reviews.llvm.org/D88933
Tim Renouf [Tue, 6 Oct 2020 17:23:59 +0000 (18:23 +0100)]
[AMDGPU] Add gfx602, gfx705, gfx805 targets
At AMD, in an internal audit of our code, we found some corner cases
where we were not quite differentiating targets enough for some old
hardware. This commit is part of fixing that by adding three new
targets:
* The "Oland" and "Hainan" variants of gfx601 are now split out into
gfx602. LLPC (in the GPUOpen driver) and other front-ends could use
that to avoid using the shaderZExport workaround on gfx602.
* One variant of gfx703 is now split out into gfx705. LLPC and other
front-ends could use that to avoid using the
shaderSpiCsRegAllocFragmentation workaround on gfx705.
* The "TongaPro" variant of gfx802 is now split out into gfx805.
TongaPro has a faster 64-bit shift than its former friends in gfx802,
and a subtarget feature could be set up for that to take advantage of
it. This commit does not make that change; it just adds the target.
V2: Add clang changes. Put TargetParser list in order.
V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order,
so fix the GPUKind order.
Differential Revision: https://reviews.llvm.org/D88916
Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
Florian Hahn [Sat, 10 Oct 2020 15:39:48 +0000 (16:39 +0100)]
[SCEV] Add test cases where the max BTC is imprecise, due to step != 1.
Add a test case where we fail to compute a tight max backedge taken
count, due to the step being != 1.
This is part of the issue with PR40961.
Florian Hahn [Sat, 10 Oct 2020 15:20:37 +0000 (16:20 +0100)]
[SCEV] Handle ULE in applyLoopGuards.
Handle ULE predicate in similar fashion to ULT predicate in
applyLoopGuards.
Florian Hahn [Sat, 10 Oct 2020 11:26:01 +0000 (12:26 +0100)]
[SCEV] Add a test case with ULE loop guard.
Nikita Popov [Sat, 10 Oct 2020 14:09:15 +0000 (16:09 +0200)]
[MemCpyOpt] Add test for incorrect memset DSE (NFC)
We can't shorten the memset if there's a throwing call in between
and the destination is non-local.
David Green [Sat, 10 Oct 2020 13:50:25 +0000 (14:50 +0100)]
[ARM] Attempt to make Tail predication / RDA more resilient to empty blocks
There are a number of places in RDA where we assume the block will not
be empty. This isn't necessarily true for tail predicated loops where we
have removed instructions. This attempt to make the pass more resilient
to empty blocks, not casting pointers to machine instructions where they
would be invalid.
The test contains a case that was previously failing, but recently been
hidden on trunk. It contains an empty block to begin with to show a
similar error.
Differential Revision: https://reviews.llvm.org/D88926
Alok Kumar Sharma [Sat, 10 Oct 2020 12:18:35 +0000 (17:48 +0530)]
[DebugInfo] Support for DWARF attribute DW_AT_rank
This patch adds support for DWARF attribute DW_AT_rank.
Summary:
Fortran assumed rank arrays have dynamic rank. DWARF attribute
DW_AT_rank is needed to support that.
Testing:
unit test cases added (hand-written)
check llvm
check debug-info
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D89141
Benjamin Kramer [Sat, 10 Oct 2020 12:13:42 +0000 (14:13 +0200)]
[clangd] Map bits/stdint-intn.h and bits/stdint-uintn.h to cstdint.
These are private glibc headers containing parts of the implementation
of stdint.h.
David Green [Sat, 10 Oct 2020 09:15:43 +0000 (10:15 +0100)]
[AArch64][LV] Move vectorizer test to Transforms/LoopVectorize/AArch64. NFC
David Green [Sat, 10 Oct 2020 09:04:28 +0000 (10:04 +0100)]
[TblGen][Scheduling] Fix debug output. NFC
This just moves some newlines to the expected places.
Tatiana Shpeisman [Sat, 10 Oct 2020 08:45:05 +0000 (14:15 +0530)]
[mlir][scf] Fix a bug in scf::ForOp loop unroll with an epilogue
Fixes a bug in formation and simplification of an epilogue loop generated
during loop unroll of scf::ForOp (https://bugs.llvm.org/show_bug.cgi?id=46689)
Differential Revision: https://reviews.llvm.org/D87583
Nikita Popov [Fri, 9 Oct 2020 19:09:16 +0000 (21:09 +0200)]
[MemCpyOpt] Don't hoist store that's not guaranteed to execute
MemCpyOpt can hoist stores while load+store pairs into memcpy.
This hoisting can currently result in stores being executed that
weren't guaranteed to execute in the original problem.
Differential Revision: https://reviews.llvm.org/D89154
Denis Antrushin [Wed, 7 Oct 2020 18:32:50 +0000 (01:32 +0700)]
[Statepoints] Allow deopt GC pointer on VReg if gc-live bundle is empty.
Currently we allow passing pointers from deopt bundle on VReg only if
they were seen in list of gc-live pointers passed on VRegs.
This means that for the case of empty gc-live bundle we spill deopt
bundle's pointers. This change allows lowering deopt pointers to VRegs
in case of empty gc-live bundle. In case of non-empty gc-live bundle,
behavior does not change.
Reviewed By: skatkov
Differential Revision: https://reviews.llvm.org/D88999
Zi Xuan Wu [Tue, 29 Sep 2020 04:31:36 +0000 (12:31 +0800)]
[CSKY 1/n] Add basic stub or infra of csky backend
This patch introduce files that just enough for lib/Target/CSKY to compile.
Notably a basic CSKYTargetMachine and CSKYTargetInfo.
Differential Revision: https://reviews.llvm.org/D88466
Fangrui Song [Sat, 10 Oct 2020 01:28:31 +0000 (18:28 -0700)]
[PowerPC] Fix signed overflow in decomposeMulByConstant after D88201
Caught by multipliers LONG_MAX (after +1) and LONG_MIN (after -1) in CodeGen/PowerPC/mul-const-i64.ll
Xiang1 Zhang [Sat, 10 Oct 2020 00:59:27 +0000 (08:59 +0800)]
[X86] Add CET test, NFC
Valentin Clement [Sat, 10 Oct 2020 01:02:29 +0000 (21:02 -0400)]
[mlir][openacc] Introduce acc.exit_data operation
This patch introduces the acc.exit_data operation that represents an OpenACC Exit Data directive.
Operands and attributes are derived from clauses in the spec 2.6.6.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D88969
Sean Silva [Sat, 10 Oct 2020 00:31:42 +0000 (17:31 -0700)]
[mlir] Rename BufferPlacement.h to Bufferize.h
Context: https://llvm.discourse.group/t/what-is-the-strategy-for-tensor-memref-conversion-bufferization/1938/14
Differential Revision: https://reviews.llvm.org/D89174
Walter Erquinigo [Sat, 3 Oct 2020 19:23:12 +0000 (12:23 -0700)]
[intel pt] Refactor parsing
With the feedback I was getting in different diffs, I realized that splitting the parsing logic into two classes was not easy to deal with. I do see value in doing that, but I'd rather leave that as a refactor after most of the intel-pt logic is in place. Thus, I'm merging the common parser into the intel pt one, having thus only one that is fully aware of Intel PT during parsing and object creation.
Besides, based on the feedback in https://reviews.llvm.org/D88769, I'm creating a ThreadIntelPT class that will be able to orchestrate decoding of its own trace and can handle the stop events correctly.
This leaves the TraceIntelPT class as an initialization class that glues together different components. Right now it can initialize a trace session from a json file, and in the future will be able to initialize a trace session from a live process.
Besides, I'm renaming SettingsParser to SessionParser, which I think is a better name, as the json object represents a trace session of possibly many processes.
With the current set of targets, we have the following
- Trace: main interface for dealing with trace sessions
- TraceIntelPT: plugin Trace for dealing with intel pt sessions
- TraceIntelPTSessionParser: a parser of a json trace session file that can create a corresponding TraceIntelPT instance along with Targets, ProcessTraces (to be created in https://reviews.llvm.org/D88769), and ThreadIntelPT threads.
- ProcessTrace: (to be created in https://reviews.llvm.org/D88769) can handle the correct state of the traces as the user traverses the trace. I don't think there'll be a need an intel-pt specific implementation of this class.
- ThreadIntelPT: a thread implementation that can handle the decoding of its own trace file, along with keeping track of the current position the user is looking at when doing reverse debugging.
Differential Revision: https://reviews.llvm.org/D88841
Aart Bik [Fri, 9 Oct 2020 23:56:11 +0000 (16:56 -0700)]
[mlir] [standard] fixed typo in comment
There is an atomic_rmw and a generic_atomic_rmw operation.
The doc of the latter incorrectly referred to former though.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D89172
Fangrui Song [Fri, 9 Oct 2020 23:38:12 +0000 (16:38 -0700)]
[bugpoint] Delete -safe-llc and make -run-llc work like -run-llc -safe-run-llc
Stella Stamenova [Fri, 9 Oct 2020 23:27:50 +0000 (16:27 -0700)]
[mlir, win] Mark several MLRI tests as unsupported on system-windows
They are currently marked as unsupported when windows is part of the triple, but they actually fail when they are run on Windows, so they are unsupported on system-windows
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D89169
Changpeng Fang [Fri, 9 Oct 2020 23:20:26 +0000 (16:20 -0700)]
Sink: Handle instruction sink when a user is dead
Summary:
The current instruction sink pass uses findNearestCommonDominator of all users to find block to sink the instruction to.
However, a user may be in a dead block, which will result in unexpected behavior.
This patch handles such cases by skipping dead blocks. This patch fixes:
https://bugs.llvm.org/show_bug.cgi?id=47415
Reviewers:
MaskRay, arsenm
Differential Revision:
https://reviews.llvm.org/D89166
Joao Moreira [Fri, 9 Oct 2020 22:25:24 +0000 (15:25 -0700)]
[X86] Check if call is indirect before emitting NT_CALL
The notrack prefix is a relaxation of CET policies which makes it possible to indirectly call targets which do not have an ENDBR instruction in the landing address. To emit a call with this prefix, the special attribute "nocf_check" is used. When used as a function attribute, a CallInst targeting the respective function will return true for the method "doesNoCfCheck()", no matter if it is a direct call (and such should remain like this, as the information that the to-be-called function won't perform control-flow checks is useful in other contexts). Yet, when emitting an X86ISD::NT_CALL, the respective CallInst should be verified for its indirection, allowing that the prefixed calls are only emitted in the right situations.
Update the respective testing unit to also verify for direct calls to functions with ''nocf_check'' attributes.
The bug can also be reproduced through compiling the following C code using the -fcf-protection=full flag.
int __attribute__((nocf_check)) foo(int a) {};
int main() {
foo(42);
}
Differential Revision: https://reviews.llvm.org/D87320
Fangrui Song [Fri, 9 Oct 2020 21:51:45 +0000 (14:51 -0700)]
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset
Add a test for a bug (uncovered by D88808) fixed by
f34bb06935aa3bab353d70d515b767fdd2f5625c.
Also delete cmpxchg16b.ll which is covered by atomic128.ll
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D89163
Eli Friedman [Thu, 8 Oct 2020 23:04:28 +0000 (16:04 -0700)]
[SCCP] Reduce the number of times ResolvedUndefsIn is called for large modules.
If a module has many values that need to be resolved by
ResolvedUndefsIn, compilation takes quadratic time overall. Solve should
do a small amount of work, since not much is added to the worklists each
time markOverdefined is called. But ResolvedUndefsIn is linear over the
length of the function/module, so resolving one undef at a time is
quadratic in general.
To solve this, make ResolvedUndefsIn resolve every undef value at once,
instead of resolving them one at a time. This loses a little
optimization power, but can be a lot faster.
We still need a loop around ResolvedUndefsIn because markOverdefined
could change the set of blocks that are live. That should be uncommon,
hopefully. We could optimize it by tracking which blocks transition from
dead to live, instead of iterating over the whole module to find them.
But I'll leave that for later. (The whole function will become a lot
simpler once we start pruning branches on undef.)
The regression test changes seem minor. The specific cases in question
could probably be optimized with a bit more work, but they seem like
edge cases that don't really matter.
Fixes an "infinite" compile issue my team found on an internal workoad.
Differential Revision: https://reviews.llvm.org/D89080
Steven Wu [Fri, 9 Oct 2020 22:17:16 +0000 (15:17 -0700)]
[IRMover] Add missing open quote in the warning message
Fix the missing single quotation mark in the warning message for
target triple mismatch.
Jordan Rupprecht [Fri, 9 Oct 2020 21:36:20 +0000 (14:36 -0700)]
Temporarily revert "[ThinLTO] Re-order modules for optimal multi-threaded processing"
This reverts commit
6537004913f3009d896bc30856698e7d22199ba7. This is causing test failures internally, and while a few of the cases turned out to be bad user code (relying on a specific order of static initialization across translation units), some cases are less clear. Temporarily reverting for now, and Teresa is going to follow up with more details.
Thomas Lively [Fri, 9 Oct 2020 21:17:53 +0000 (21:17 +0000)]
[WebAssembly] Prototype i16x8.q15mulr_sat_s
This saturating, rounding, Q-format multiplication instruction is proposed in
https://github.com/WebAssembly/simd/pull/365.
Differential Revision: https://reviews.llvm.org/D88968
Louis Dionne [Fri, 9 Oct 2020 19:06:04 +0000 (15:06 -0400)]
[libc++] Remove code to prevent overwriting the system libc++ on Darwin
The system partition is read-only since Catalina.
Louis Dionne [Fri, 9 Oct 2020 19:04:12 +0000 (15:04 -0400)]
[libc++] Remove redundant if(LIBCXX_INSTALL_LIBRARY)
The individual LIBCXX_INSTALL_(SHARED|STATIC)_LIBRARY are already
dependent on whether LIBCXX_INSTALL_LIBRARY is ON or OFF.
Saleem Abdulrasool [Thu, 1 Oct 2020 05:42:17 +0000 (22:42 -0700)]
DirectoryWatcher: add an implementation for Windows
This implements the directory watcher on Windows. It does the most
naive thing for simplicity. ReadDirectoryChangesW is used to monitor
the changes. However, in order to support interruption, we must use
overlapped IO, which allows us to use the blocking, synchronous
mechanism. We create a thread to post the notification to the consumer
to allow the monitoring to continue. The two threads communicate via a
locked queue.
Differential Revision: https://reviews.llvm.org/D88666
Reviewed By: Adrian McCarthy
Mircea Trofin [Fri, 9 Oct 2020 20:35:56 +0000 (13:35 -0700)]
[NFC][Regalloc] VirtRegAuxInfo::Hint does not need to be a field
It is only used in weightCalcHelper, and cleared upon its finishing its
job there.
The patch further cleans up style guide discrepancies, and simplifies
CopyHint by removing duplicate 'IsPhys' information (it's what the Reg
field would report).
Krzysztof Parzyszek [Thu, 8 Oct 2020 22:20:31 +0000 (17:20 -0500)]
[Hexagon] Remove ISD node VSPLATW, use VSPLAT instead
This is a step towards improving HVX codegen for splat.
Krzysztof Parzyszek [Thu, 8 Oct 2020 22:12:32 +0000 (17:12 -0500)]
[Hexagon] Generalize handling of SDNodes created during ISel
The selection of HVX shuffles can produce more nodes in the DAG,
which need special handling, or otherwise they would be left
unselected by the main selection code. Make the handling of such
nodes more general.
Christian Sigg [Thu, 8 Oct 2020 11:43:18 +0000 (13:43 +0200)]
Add GPU async op interface and token type.
See https://llvm.discourse.group/t/rfc-new-dialect-for-modelling-asynchronous-execution-at-a-higher-level/1345
Reviewed By: herhut
Differential Revision: https://reviews.llvm.org/D88954
Nicolas Vasilache [Fri, 9 Oct 2020 19:15:16 +0000 (19:15 +0000)]
[mlir][Linalg] NFC - Cleanup explicitly instantiated paterns 2/n - Loops.cpp
This revision belongs to a series of patches that reduce reliance of Linalg transformations on templated rewrite and conversion patterns.
Instead, this uses a MatchAnyTag pattern for the vast majority of cases and dispatches internally.
Differential revision: https://reviews.llvm.org/D89133
Nicolas Vasilache [Fri, 9 Oct 2020 14:31:52 +0000 (14:31 +0000)]
[mlir][Linalg] NFC - Cleanup explicitly instantiated paterns 1/n - LinalgToStandard.cpp
This revision belongs to a series of patches that reduce reliance of Linalg transformations on templated rewrite and conversion patterns.
Instead, this uses a MatchAnyTag pattern for the vast majority of cases and dispatches internally.
Differential Revision: https://reviews.llvm.org/D89133
Nicolas Vasilache [Fri, 9 Oct 2020 10:45:59 +0000 (10:45 +0000)]
Revert "Give attributes C++ namespaces."
This reverts commit
0a34492f36d77f043d371cc91f359b2d65e86475.
This change turned out to be very intrusive wrt some internal projects.
Reverting until this can be sorted out.
Arthur Eubanks [Fri, 9 Oct 2020 19:35:23 +0000 (12:35 -0700)]
[Reg2Mem][NewPM] Pin test to legacy PM
This pass hasn't been touched in a long time and isn't used in tree.
Vy Nguyen [Mon, 21 Sep 2020 21:41:48 +0000 (17:41 -0400)]
Enable LSAN for Android
Make use of the newly added thread-properties API (available since 31).
Differential Revision: https://reviews.llvm.org/D85927
Mircea Trofin [Fri, 9 Oct 2020 19:18:52 +0000 (12:18 -0700)]
[NFC][Regalloc] Fix coding style in CalcSpillWeights
Stella Laurenzo [Fri, 9 Oct 2020 19:16:45 +0000 (12:16 -0700)]
NFC: Address post-commit doc/formatting comments on TypeID.h.
Stella Laurenzo [Fri, 9 Oct 2020 18:49:38 +0000 (11:49 -0700)]
[mlir] Fix TypeID for shared libraries built with -fvisibility=hidden.
* Isolates the visibility controlled parts of its implementation to a detail namespace.
* Applies a struct level visibility attribute which applies to the static local within the get() functions.
* The prior version was not emitting a symbol for the static local "instance" fields when the user TU was compiled with -fvisibility=hidden.
Differential Revision: https://reviews.llvm.org/D89153
Scott Linder [Fri, 9 Oct 2020 19:02:53 +0000 (19:02 +0000)]
[clang] Add a test for CGDebugInfo treatment of blocks
There doesn't seem to be a direct test of this, and I'm planning to make
future changes which will affect it.
I'm not particularly familiar with the blocks extension, so suggestions
for better tests are welcome.
Differential Revision: https://reviews.llvm.org/D88754
Craig Topper [Fri, 9 Oct 2020 18:48:10 +0000 (11:48 -0700)]
[X86] When expanding LCMPXCHG16B_NO_RBX in EmitInstrWithCustomInserter, directly copy address operands instead of going through X86AddressMode.
I suspect getAddressFromInstr and addFullAddress are not handling
all addresses cases properly based on a report from MaskRay.
So just copy the operands directly. This should be more efficient
anyway.
Craig Topper [Fri, 9 Oct 2020 17:26:50 +0000 (10:26 -0700)]
[X86] Don't copy kill flag when expanding LCMPXCHG16B_SAVE_RBX
The expansion code creates a copy to RBX before the real LCMPXCHG16B.
It's possible this copy uses a register that is also used by the
real LCMPXCHG16B. If we set the kill flag on the use in the copy,
then we'll fail the machine verifier on the use on the LCMPXCHG16B.
Differential Revision: https://reviews.llvm.org/D89151
Nikita Popov [Fri, 9 Oct 2020 18:52:08 +0000 (20:52 +0200)]
[MemCpyOpt] Add test for incorrectly hoisted store (NFC)
Louis Dionne [Fri, 9 Oct 2020 18:40:47 +0000 (14:40 -0400)]
[libc++] Fixup a missing occurrence of LIBCXX_ENABLE_DEBUG_MODE
Louis Dionne [Fri, 9 Oct 2020 18:39:20 +0000 (14:39 -0400)]
[libc++] Rename LIBCXX_ENABLE_DEBUG_MODE to LIBCXX_ENABLE_DEBUG_MODE_SUPPORT
To make it clearer this is about whether the library supports the debug
mode at all, not whether the debug mode is enabled. Per comment by Nico
Weber on IRC.