Samuel Pitoiset [Wed, 3 May 2023 07:18:54 +0000 (09:18 +0200)]
radv: remove ac_surf_info from radv_image
Introduce a helper to convert vk_image info to ac_surf_info instead.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
Samuel Pitoiset [Wed, 3 May 2023 06:36:54 +0000 (08:36 +0200)]
radv: use vk_image::extent instead of radv_image::info::{width,height,depth}
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
Samuel Pitoiset [Wed, 3 May 2023 06:28:44 +0000 (08:28 +0200)]
radv: use vk_image::samples instead of radv_image::info::samples
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
Samuel Pitoiset [Wed, 3 May 2023 06:25:02 +0000 (08:25 +0200)]
radv: use vk_image::samples instead of radv_image::info::storage_samples
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
Samuel Pitoiset [Wed, 3 May 2023 06:21:04 +0000 (08:21 +0200)]
radv: use vk_image::array_layers instead of radv_image::info::array_size
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
Samuel Pitoiset [Wed, 3 May 2023 06:17:06 +0000 (08:17 +0200)]
radv: use vk_image::mip_levels instead of radv_image::info::levels
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
Samuel Pitoiset [Thu, 4 May 2023 09:52:58 +0000 (11:52 +0200)]
radv: disable RB+ blend optimizations on GFX11 when a2c is enabled
Closes: #8222
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21313>
Christopher Snowhill [Sat, 6 May 2023 04:45:45 +0000 (21:45 -0700)]
Corrects log print to produce hexadecimal base output
Matching the original %016lx, and the "0x" prefix which is still
in the format string.
Fixes:
53b77a8102cd ("anv: remove 48bit address space checks")
Signed-off-by: Christopher Snowhill <kode54@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22882>
Lionel Landwerlin [Fri, 5 May 2023 10:12:25 +0000 (13:12 +0300)]
intel/fs: reduce register usage for relocated constants
Commit
bb8e31b7ed ("anv: avoid hardcoding instruction VA constant in
shaders") had a slight negative impact on shaders (Red Dead Redemption
2 in particular). Dropping a few shaders from SIMD32 to SIMD16.
With this change, it brings back all the dropped SIMD32 shaders.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22872>
Asahi Lina [Wed, 3 May 2023 06:41:37 +0000 (15:41 +0900)]
asahi: Fix batch writer_syncobj cleanup
When an ACTIVE batch takes over the active writer role from a SUBMITTED
batch, the written BO has the syncobj from the latter even though the
writer is the former. This is correct and an intended state, but it
means that then we can't gate the syncobj cleanup in agx_batch_cleanup
on being the active writer, since the SUBMITTED batch won't be.
Fixes: asahi/mesa#18
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Wed, 3 May 2023 06:40:33 +0000 (15:40 +0900)]
asahi: Assert that freed BOs have no pending writers
This is just a sanity check, I haven't actually hit this case but if we
ever do something is very broken (e.g. BO refcounting bug).
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Wed, 26 Apr 2023 19:26:37 +0000 (15:26 -0400)]
asahi: Fix depth load/store flags
If depth_writemask is set, we need to write depth regardless of whether we run
the depth test, to write out the fixed-function fragment depth. This will matter
when we start honouring these flags.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Wed, 3 May 2023 12:48:21 +0000 (21:48 +0900)]
asahi: Clear batch->resolve on agx_batch_init
This has been broken forever, but it was only noticed with the ZS
load/store optimizations in the subsequent commits.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Mon, 20 Mar 2023 02:12:09 +0000 (22:12 -0400)]
asahi: Implement transform feedback
This code was originally based on the Panfrost implementation, but has been
improved in a number of ways.
1. Transform feedback programs are dispatched generically with Gallium calls,
rather than emitting something hardware-specific. This is cleaner and
portable to future GPUs.
2. Transform feedback with indexed draws is now fixed, by lowering to an index
buffer pull.
3. Transform feedback with buffer overflows is now fixed, by correctly
bounds checking in transform feedback programs.
4. Transform feedback with strips/fans/loops are fixed, by correctly
tessellating to the underlying primitives as required by OpenGL.
5. Transform feedback with QUADS is fixed, by tessellating to triangles as
required by OpenGL.
That said, the code is still not in its final form.
1. It still does not support indirect draws. This will require a substantial
overhaul to do tracking on the GPU instead of the CPU. Currently we force
unroll indirect draws (slow but kosher in GL, treif in Vulkan). This isn't
hard to solve but I'm not going to duplicate the code until the algorithms
are otherwise complete because it's a lot easier to hack on the CPU versions
than the GPU versions.
2. It still does not support primitive restart. This has especially nasty
interactions with transform feedback. Again we force unroll to non-primitive
restart forms, again slow but kosher in GL but treif in Vulkan. This is a lot
harder to deal with. I sketched out something really nasty in my notebook
(hinging on efficient GPU prefix sums) but I'm not in a hurry to type this
out.
3. There will be interactions with geometry and tessellation shaders and I don't
think I can get the core code here future-proofed without actually bringing
up the new shader stages.
As such, this is a hard fork of the panfrost code for now, I'm not trying to
share the code (although it *would* clear out almost all of panfrost's transform
feedback related piglit failures).
Passes dEQP-GLES3.functional.transform_feedback.* and most of the relevant
piglits.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Thu, 27 Apr 2023 18:41:17 +0000 (14:41 -0400)]
asahi: Bump MAX_PUSH_RANGES to the worst-case
This shortcuts all headaches about how big this should be. It does increase
memory usage a bit if there are lots of shader variants compiled, but this
should be tolerable, and can be optimized later if so required. Thanks to the
previous commit, the disk cache size should be unaffected.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Thu, 27 Apr 2023 19:24:32 +0000 (15:24 -0400)]
asahi: Shrink disk cache size of push ranges
Only store the push ranges we actually need, not all of them. This should save
some disk space, while insulating us to MAX_PUSH_RANGES changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Thu, 22 Dec 2022 02:46:06 +0000 (21:46 -0500)]
agx: Lower I/O to scalar later
This lets us preserve vectorized stores for transform feedback shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sat, 15 Apr 2023 13:39:28 +0000 (09:39 -0400)]
agx: Validate that collect sources are the same size
RA asserts this, but by then if you've messed it up, the failure is inscrutable.
Let's check it in the validator for more pleasant debugging.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 23 Apr 2023 21:50:52 +0000 (17:50 -0400)]
agx: Rework z/s emit
We were being sloppy with the sizes before. It mostly worked out, but there were
some corner cases where we would end up with mixed sized collects and that won't
end well for us. Let's rework the logic to make all the sizes explicit in NIR --
32-bit for depth and 16-bit stencil -- and then do the needed promotions to make
it happen in the AGX IR side.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 23 Apr 2023 21:38:40 +0000 (17:38 -0400)]
agx: Ensure load_frag_coord has the right sizes
In case .x isn't read, it'll be null which has the wrong size and will fail
the validation added later in this series. We fix this by padding with sized
undefs (something that exists of defined size but undefined value) rather than
nothingness (of undefined size).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Thu, 27 Apr 2023 16:00:12 +0000 (12:00 -0400)]
agx/lower_address: Match multiplies, not only shifts
Sometimes a shader might index with a non-power-of-two stride. For example, if
it's indexing into an array of structures where the structure size is not a
power of two, we'll get a multiply with a constant as opposed to a shift. We
want to handle these cases, too. To do so, we generalize our pattern matching to
look for any kind of multiply (with our new helper), rather than hardcoding
logic for ishl. This eliminates right-shifts in a pile of compute shaders, which
makes me happy from a "I read lots of shader assembly when debugging"
perspective.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Thu, 27 Apr 2023 15:59:17 +0000 (11:59 -0400)]
agx/lower_address: Add helper to match multiplies
Currently, we hardcode logic in the addressing chasing code to look for ishl
instructions that shift by constants. We can generalize this to looking for
integer multiplies by constants to optimize more addressing patterns. Add a
helper to do so.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Wed, 26 Apr 2023 14:20:45 +0000 (10:20 -0400)]
asahi: Bind staging resources as RENDER_TARGET
This doesn't matter in practice (at least with mesa/st), but it's more correct
technically.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Wed, 26 Apr 2023 03:20:25 +0000 (23:20 -0400)]
agx: Don't wait at the end of the shader
This is totally pointless. This saves some waits at the ends of compute kernels
(waiting for stores to complete before terminating the thread). I don't know
how much this would matter for performance, since the hardware may have to do
these waits internally, but it makes the generated code less silly which is
always nice.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sat, 11 Mar 2023 22:37:19 +0000 (17:37 -0500)]
asahi: Copy resources if needed to shadow
This lets us shadow textures updated in the middle of rendering in Quake3.
They're big memcpys, but as long as the texture memory is cached it's ok. We use
a heuristic to avoid too many memcpys from uncached memory, which would cause
slideshow performance in quake.
We need to be careful to avoid shadowing shared resources, though, that's
invalid and would break WSI pretty hard.
It would be better to blit on the GPU for large shadowing, but that's more
involved and left for future work.
Reduces stuttering in Quake3.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Fri, 14 Apr 2023 23:57:20 +0000 (19:57 -0400)]
asahi: Rename no colour output to tag write disable
Comparison with PowerVR's XML shows that this is the actual name... And it needs
to be set a bit more carefully than "no colour output" in order to get correct
behaviour for depth-only passes that use sample mask / discard. Fix the name
first, the extra conditions will come when they're needed for multisampling.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Tue, 25 Apr 2023 17:51:46 +0000 (13:51 -0400)]
agx: Fix packing for iadd with shift
Wrong bit pattern was packed, oops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Mon, 24 Apr 2023 02:24:27 +0000 (22:24 -0400)]
asahi: Use device_load shift for VBO loads
When possible. Only occassionally possible because the loads are pretty limited
in the addressing arithmetic. This probably doesn't matter for performance but
it saves some noise in dEQP tests which makes for nicer debugging, plenty of
optimizations end up worth it for that alone.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Mon, 24 Apr 2023 03:13:08 +0000 (23:13 -0400)]
agx: Defeature fsub
All has_fsub does is fuse fsubs (they're unfused otherwise), no point doing that
if we're going to just going to lower.
shader-db is mostly noise.
total instructions in shared programs: 1487217 -> 1487035 (-0.01%)
instructions in affected programs: 22658 -> 22476 (-0.80%)
helped: 85
HURT: 2
helped stats (abs) min: 1.0 max: 12.0 x̄: 2.19 x̃: 1
helped stats (rel) min: 0.38% max: 2.46% x̄: 0.87% x̃: 0.65%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.58% max: 1.08% x̄: 0.83% x̃: 0.83%
95% mean confidence interval for instructions value: -2.51 -1.67
95% mean confidence interval for instructions %-change: -0.97% -0.70%
Instructions are helped.
total bytes in shared programs:
10189996 ->
10189288 (<.01%)
bytes in affected programs: 158132 -> 157424 (-0.45%)
helped: 85
HURT: 2
helped stats (abs) min: 4.0 max: 48.0 x̄: 8.75 x̃: 4
helped stats (rel) min: 0.22% max: 1.44% x̄: 0.51% x̃: 0.38%
HURT stats (abs) min: 6.0 max: 30.0 x̄: 18.00 x̃: 18
HURT stats (rel) min: 0.90% max: 0.91% x̄: 0.91% x̃: 0.91%
95% mean confidence interval for bytes value: -9.98 -6.30
95% mean confidence interval for bytes %-change: -0.56% -0.39%
Bytes are helped.
total halfregs in shared programs: 462536 -> 462556 (<.01%)
halfregs in affected programs: 131 -> 151 (15.27%)
helped: 1
HURT: 4
helped stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 28.57% max: 28.57% x̄: 28.57% x̃: 28.57%
HURT stats (abs) min: 4.0 max: 8.0 x̄: 5.50 x̃: 5
HURT stats (rel) min: 12.77% max: 36.36% x̄: 25.01% x̃: 25.45%
95% mean confidence interval for halfregs value: -0.65 8.65
95% mean confidence interval for halfregs %-change: -18.64% 47.23%
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Wed, 26 Apr 2023 14:48:08 +0000 (14:48 +0000)]
asahi: Use u_default_get_sample_position
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 9 Apr 2023 03:05:49 +0000 (23:05 -0400)]
agx: Remove bogus assert
I->mask isn't even valid for iter instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sat, 18 Mar 2023 22:16:40 +0000 (18:16 -0400)]
asahi: Compress more texture targets
They should already work, we just need it enabled. The comment here claimed
(incorrectly) that there is no hardware support for linear 2D arrays. In fact,
there is support, it's just not advertised in the public Metal API. With some
awful tricks, I managed to reverse-engineer the hardware interface and hooked it
up, so we can take advantage of it now.
In fact, we can stop checking the target explicitly at all. The only case where
we can't compress is 1D/buffer textures, which are necessarily less than 16
height so will be dropped in the next check.
When I originally wrote this cuhange, dolphin's MeltyMoltenGalaxy trace with
specialized shaders at 4K was helped from 28fps to 43fps, which is massive :-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 9 Apr 2023 18:16:53 +0000 (14:16 -0400)]
asahi: Use 2D array staging resources for cube/3D
Staging resources need to be linear for efficient CPU side mapping. This is a
problem for access to 3D and cube textures, since we don't have linear 3D
textures or linear cube textures. But we do have linear 2D array textures, which
can be reshaped to the same effect. So use a 2D array staging resource even for
3D textures and cube maps.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 9 Apr 2023 17:07:51 +0000 (13:07 -0400)]
asahi: Explicitly ban MSAA, compression with linear
These get asserted later. It doesn't really matter but this makes our queries
more accurate. This came up when experimenting a debug option that forces linear
textures to be used as much as possible.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 9 Apr 2023 17:59:13 +0000 (13:59 -0400)]
agx: Handle linear 2D array textureSize()
We handle linear 2D arrays internally for blit shaders, so we need textureSize
to work for these. That requires some special casing, because there's a line
stride where the layer count would otherwise be. But it's not too bad.
Fixes
dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray_*
when forcing linear textures.
Since we clamp array access to the maximum layer, we need textureSize() to work
for even the most basic array texturing. So this should fix blits from linear 2D
arrays as well, which finally unlocks support for compressed arrays/cubes/3D
textures.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sat, 8 Apr 2023 21:25:12 +0000 (17:25 -0400)]
agx/lower_zs_emit: Fix progress returning
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sat, 8 Apr 2023 21:52:52 +0000 (17:52 -0400)]
agx: Fix abs/neg propagation into fcmpsel
The first two sources are floats, the latter two sources and destination (and
hence the opcode) are not. Reflect that when packing and optimizing. Noticed
while debugging a silly dEQP test.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 9 Apr 2023 13:42:33 +0000 (09:42 -0400)]
agx: Handle splits of uniforms
This is straightforward, and can happen with certain u2u16 patterns.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sun, 9 Apr 2023 16:50:46 +0000 (12:50 -0400)]
asahi: Track write to separate stencil
From the commit message of
94f7c011d6e ("v3d: Track write reference to the
separate stencil buffer."), anholt says:
Otherwise, a blit from separate stencil may fail to flush the job that
initialized it, or new drawing could fail to flush a blit reading from
stencil.
Fixes
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Sat, 8 Apr 2023 17:21:51 +0000 (13:21 -0400)]
asahi: Identify XML for barycentric coordinates
Reading them from a fragment shader, not interpolating at custom ones.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Fri, 7 Apr 2023 20:36:46 +0000 (16:36 -0400)]
asahi: Don't use depth/stencil staging blits
Our staging resources need to be LINEAR, however we don't support LINEAR with
DEPTH_STENCIL. The APIs don't actually require this, we just need to make sure
we don't generate internal staging blits to linear depth/stencil resources. For
uploading to compressed depth/stencil textures, we could use a depth/stencil
staging (since we can read from linear depth/stencil). However, for downloading
from compressed depth/stencil, we can't use a depth/stencil staging (since we
can't write linear depth/stencil). So, to handle both cases in a unified way,
just use colour blits for depth/stencil resources, using a compatible colour
format. This wouldn't be ok for an application to do itself, but within the
driver we know that it's safe, since there's no difference in memory between
depth/stencil and colour on AGX. In particular, Z16 is compressed exactly the
same as R16, Z8 as R8, and so on.
Fixes depth/stencil compression.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Fri, 7 Apr 2023 19:02:32 +0000 (15:02 -0400)]
asahi: Minify width/height in create_surface
Otherwise framebuffer->width ends up being wrong with u_blitter, this is what
other drivers do. If we needed to render to depth/stencil with u_blitter, this
would cause us trouble.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Alyssa Rosenzweig [Mon, 24 Apr 2023 02:10:34 +0000 (22:10 -0400)]
asahi: Fix disk cache disable with AGX_MESA_DEBUG
We go to initialize the disk cache before we've compiled any shaders so
agx_compiler_debug is 0 at this point. Don't try to read it, instead go through
sa safe getter that will do the right thing.
Fixes:
5e9538c12e0 ("agx: isolate compiler debug flags")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Wed, 5 Apr 2023 10:05:00 +0000 (19:05 +0900)]
asahi: Fix batch writer tracking for null batches
When an empty batch is submitted, nothing happens. However, this batch
may have taken over writer status for some BOs which still have a
pending submitted batch that hasn't finished yet. If we drop writer
status at this point, two bad things happen:
- We spuriously clear bo->writer_syncobj, which breaks syncing on
post-facto BO exports
- We break agx_sync_writer(), since we no longer know about the old
writer to properly block on it.
To fix this (hopefully rare) case, take advantage of bo->writer_syncobj
to find the currently submitted writer batch again, and revert the
writer to it. If this turns out to be common and a performance issue
iterating through submitted batches for each written BO, we could
implement it with two writer batch arrays instead, one for active
writers and one for submitted writers... but hopefully that isn't
necessary.
This splits the cleanup path in agx_batch_cleanup() depending on whether
the cleanup is for a reset or proper completion. Since this is only used
within agx_batch.c, drop the public prototype while we're at it.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Wed, 5 Apr 2023 09:03:02 +0000 (18:03 +0900)]
asahi: Add batch state debugging
I've had to reimplement this more than once, let's just make a flag for
it.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Janne Grunau [Wed, 12 Apr 2023 09:01:07 +0000 (11:01 +0200)]
asahi: Free low VA BOs correctly
These need the shader_base added to them. Fixes GEM_BIND errors after
usc_head provides VA without the VM_SHADER_START offset from returned
low VA.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Janne Grunau [Fri, 7 Apr 2023 18:27:00 +0000 (20:27 +0200)]
asahi: Fix typo in debug/error message helper macro
The typo is in the !__GLIBC__ case and was observed while building on
Alpine.
Fixes:
0a132b06406d ("asahi: Add a helper macro for debug/error messages")
Reported-by: mps
Tested-by: mps
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Fri, 7 Apr 2023 14:17:13 +0000 (23:17 +0900)]
asahi: Enable 2xMSAA (for deqp)
This also just works, let's enable it (still gated on deqp).
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Fri, 7 Apr 2023 14:09:45 +0000 (23:09 +0900)]
asahi: Broadcast Z for all components on texture fetch
Gallium expects this.
Related commit:
6cac9c748e
Co-authored-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Asahi Lina [Fri, 7 Apr 2023 14:08:50 +0000 (23:08 +0900)]
asahi: Identify ZS resolve bits (tentative)
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>
Konstantin Seurer [Tue, 2 May 2023 17:56:44 +0000 (19:56 +0200)]
nir/lower_fp16_casts: Fix SSA dominance
Fixes: 01dfd65 ("nir: port fp16 casting code from dxil")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22804>
David Heidelberg [Fri, 5 May 2023 12:57:01 +0000 (14:57 +0200)]
ci: uprev kernel to 6.3.1 with fixed patch for Adreno SMMU
Going from release candidate to stable kernel hopefully also improve
overall stability.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22873>
Rob Clark [Fri, 3 Mar 2023 21:45:34 +0000 (13:45 -0800)]
freedreno/a6xx+: Use template to handle a6xx vs a7xx differences
This doesn't enable support for a7xx yet, but uses the new register pack
builders for registers that differ between a7xx and a6xx.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22837>
Rob Clark [Sat, 4 Mar 2023 20:01:31 +0000 (12:01 -0800)]
freedreno/a6xx: Rework set_bin_size()
The open-coded flag param for "all the other bits" won't work once we
have register variants in play.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22837>
Gert Wollny [Sat, 6 May 2023 07:24:42 +0000 (09:24 +0200)]
r600/sfn: fix cube to array lowering for LOD
Makes piglits related to texturequerylod and samplercubearray pass.
Fixes:
79ca456b4837 ("r600/sfn: rewrite NIR backend")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22883>
Gert Wollny [Sat, 6 May 2023 07:20:55 +0000 (09:20 +0200)]
r600/sfn: Ass support for image_samples
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8971
Fixes:
79ca456b4837 ("r600/sfn: rewrite NIR backend")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22883>
Erik Faye-Lund [Tue, 14 Mar 2023 09:39:46 +0000 (10:39 +0100)]
docs/tgsi: use \ll and \gg for left and right shift
This renders a bit cleaner.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Tue, 14 Mar 2023 09:35:17 +0000 (10:35 +0100)]
docs/tgsi: fixup latex for TEX and TEX2
We need to excape the underscores for shadow_ref, as well as escape
non-math symbols.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Tue, 14 Mar 2023 09:23:43 +0000 (10:23 +0100)]
docs/tgsi: do not use math-block for non-latex
This block isn't valid latex, so let's just use a pseudocode-block like
we do elsewhere here.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Tue, 14 Mar 2023 09:09:02 +0000 (10:09 +0100)]
docs/tgsi: use math-notations for conditionals
These are math-blocks, which is supposed to use math-notation for
conditionals. So let's change it to math notation.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Mon, 13 Mar 2023 15:28:39 +0000 (16:28 +0100)]
docs/tgsi: wrap overly long lines
While we're at it, use some alignment so the equations still reads
reasonably.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Tue, 14 Mar 2023 08:49:02 +0000 (09:49 +0100)]
docs/tgsi: fixup bad latex
It's better to split these two equations in two than to try to write
extra text that needs lots of escaping. This fixes the LaTeX rendering
to be somewhat readable.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Tue, 14 Mar 2023 08:45:47 +0000 (09:45 +0100)]
docs/tgsi: fix bad latex
We need empty spaces here, otherwise LaTeX thinks it's one equation, and
puts it all back onto one line.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Erik Faye-Lund [Mon, 13 Mar 2023 15:23:38 +0000 (16:23 +0100)]
docs/tgsi: fix up indent
There's a mixture of indent styles here, with either two or three
spaces. We have standardized on three spaces for .rst-files in the
editorconfig, so let's apply that.
While we're at it, make sure math-blocks are indented into their
opcode-block. While the result might look the same most of the time,
this matters when we have textual explaination following math-blocks,
like we have in a few caess. If we don't indent the math there, we
end up with having to unindent the text following the math-block for it
not to count as a part of the math block, which looks very confusing
when reading the source code.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>
Eric Engestrom [Fri, 5 May 2023 16:49:12 +0000 (17:49 +0100)]
dzn: fix pointer type mismatch
../src/microsoft/vulkan/dzn_image.c: In function ‘dzn_GetImageMemoryRequirements2’:
../src/microsoft/vulkan/dzn_image.c:918:91: error: passing argument 6 of ‘dzn_ID3D12Device12_GetResourceAllocationInfo3’ from incompatible pointer type [-Werror=incompatible-pointer-types]
918 | &image->castable_format_count, &image->castable_formats,
| ^~~~~~~~~~~~~~~~~~~~~~~~
| |
| DXGI_FORMAT **
In file included from ../src/microsoft/vulkan/dzn_private.h:67,
from ../src/microsoft/vulkan/dzn_image.c:24:
../src/microsoft/vulkan/dzn_abi_helper.h:64:107: note: expected ‘const DXGI_FORMAT * const*’ but argument is of type ‘DXGI_FORMAT **’
64 | const UINT *num_castable_formats, const DXGI_FORMAT *const *castable_formats,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
Fixes:
71dbb3120a9d0fb0de32 ("dzn: Use GetResourceAllocationInfo3 for castable formats")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22877>
Emma Anholt [Thu, 4 May 2023 21:43:15 +0000 (14:43 -0700)]
ci/turnip: Drop the IUB bug fallout flakes.
They haven't been seen since my fix landed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
Emma Anholt [Thu, 4 May 2023 21:01:58 +0000 (14:01 -0700)]
ci/turnip: Drop an xfail from the full run for a recent fix.
Fixes:
2cbc24b9da01 ("turnip: fix buffer markers using wrong addresses")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
Emma Anholt [Thu, 4 May 2023 20:53:00 +0000 (13:53 -0700)]
ci/radv: Disable flaky heaven d3d9 trace.
10 flakes this month, starting with the noted job.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
Emma Anholt [Thu, 4 May 2023 20:52:41 +0000 (13:52 -0700)]
ci/radeonsi: Mark glx-make-current as flaky.
It no longer 100% crashes, but instead sometimes fails.
Fixes:
91b06ea8b254 ("Uprev Piglit to
2391a83d1639a7ab7bbea02853b922878687b0e5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
Marcin Ślusarz [Fri, 5 May 2023 12:55:37 +0000 (14:55 +0200)]
intel/tools: decode ACTHD printed by newer kernels
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22874>
Ruijing Dong [Thu, 4 May 2023 01:20:51 +0000 (21:20 -0400)]
radeonsi/vcn: fix decoding bs buffer alignement issue.
reason:
in some cases, bs buffer size could cause assertion,
and some bitstreams of certain resolutions could
not be decoded.
solution:
to align the bs buffer to 128.
fixes:
4f1646d73fa8bac82ff2195f06a5f6011853f647
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22844>
Mike Blumenkrantz [Thu, 4 May 2023 14:11:02 +0000 (10:11 -0400)]
zink: add ZINK_DEBUG=optimal_keys
it's otherwise very annoying to figure out why this may or may not be
available
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
Mike Blumenkrantz [Thu, 4 May 2023 13:46:45 +0000 (09:46 -0400)]
zink: disable EXT_shader_object if !optimal_keys
this has the same requirements as GPL and then some
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
Mike Blumenkrantz [Thu, 4 May 2023 13:46:07 +0000 (09:46 -0400)]
zink: break out optimal key handling into separate function
this is growing to be much larger than the original conditional
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
Mike Blumenkrantz [Thu, 4 May 2023 13:43:26 +0000 (09:43 -0400)]
zink: move EXT_shader_object check to another place
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
Lionel Landwerlin [Thu, 4 May 2023 07:58:34 +0000 (10:58 +0300)]
anv: increase instruction heap to 2Gb
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8917
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
Lionel Landwerlin [Thu, 23 Feb 2023 07:59:45 +0000 (09:59 +0200)]
anv: make internal address space allocation more dynamic
We're about to manipulate these pools and dealing with the fix address
ranges is painful.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
Lionel Landwerlin [Tue, 6 Dec 2022 14:32:49 +0000 (16:32 +0200)]
anv: link anv_bo to its VMA heap
We want to add more heaps in the future and so not having to do
address checks to find out in what heap to release a BO is convinient.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
Lionel Landwerlin [Thu, 23 Feb 2023 07:50:02 +0000 (09:50 +0200)]
anv: avoid hardcoding instruction VA constant in shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
Lionel Landwerlin [Thu, 23 Feb 2023 07:16:40 +0000 (09:16 +0200)]
anv: remove 48bit address space checks
All the supported platforms should have 36+ bits of virtual address
space.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
Tapani Pälli [Thu, 4 May 2023 10:39:41 +0000 (13:39 +0300)]
isl: fix layout for comparing surf and view properties
These asserts were checking isl_format_layout against itself, change
to compare surface format layout against view format layout.
Fixes:
628bfaf1c6f ("intel/isl: Add some sanity checks for compressed surfaces")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22790>
Lionel Landwerlin [Mon, 3 Apr 2023 11:52:59 +0000 (14:52 +0300)]
intel/fs: fix scheduling of HALT instructions
With the following test :
dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.no_out_of_bounds_load
There is a :
shader_start:
... <- no control flow
g0 = some_alu
g1 = fbl
g2 = broadcast g3, g1
g4 = get_buffer_size g2
... <- no control flow
halt <- on some lanes
g5 = send <surface>, g4
eliminate_find_live_channel will remove the fbl/broadcast because it
assumes lane0 is active at get_buffer_size :
shader_start:
... <- no control flow
g0 = some_alu
g4 = get_buffer_size g0
... <- no control flow
halt <- on some lanes
g5 = send <surface>, g4
But then the instruction scheduler will move the get_buffer_size after
the halt :
shader_start:
... <- no control flow
halt <- on some lanes
g0 = some_alu
g4 = get_buffer_size g0
g5 = send <surface>, g4
get_buffer_size pulls the surface index from lane0 in g0 which could
have been turned off by the halt and we end up accessing an invalid
surface handle.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20765>
Timur Kristóf [Tue, 25 Apr 2023 16:40:18 +0000 (18:40 +0200)]
amd: Cleanup old GS intrinsics code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Tue, 25 Apr 2023 16:20:57 +0000 (18:20 +0200)]
ac/nir/ngg: Use sendmsg in NGG lowering.
There is no need to use alloc_vertices_and_primitives anymore,
because it will be compiled to sendmsg anyway.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Tue, 25 Apr 2023 16:38:12 +0000 (18:38 +0200)]
ac/nir: Emit legacy GS DONE signal in NIR.
Legacy GS needs to emit a DONE signal at the end. Do this in NIR
instead of in the backends.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Tue, 25 Apr 2023 16:15:03 +0000 (18:15 +0200)]
ac/nir: Use sendmsg in legacy GS lowering.
Remove the GS intrinsics completely and emit the sendmsg here
instead of in the backend. This is done to simplify backend code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Tue, 25 Apr 2023 15:57:05 +0000 (17:57 +0200)]
ac/llvm: Clarify arguments of ac_build_sendmsg.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Tue, 25 Apr 2023 16:23:02 +0000 (18:23 +0200)]
amd: Move sendmsg defines to ac_shader_util.
Will be used by ac/nir legacy and NGG lowerings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Wed, 26 Apr 2023 12:27:10 +0000 (14:27 +0200)]
amd: Add and implement gs_wave_id sysval.
Contains a global wave ID of legacy GS waves.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Tue, 25 Apr 2023 15:56:50 +0000 (17:56 +0200)]
amd: Add and implement sendmsg_amd intrinsic.
This intrinsic is going to be used for simplifying GS code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Timur Kristóf [Wed, 3 May 2023 16:58:36 +0000 (18:58 +0200)]
aco: Disallow constant propagation on SOPP and fixed operands.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Rhys Perry [Thu, 27 Apr 2023 15:22:52 +0000 (16:22 +0100)]
aco/ra: create M0-affinities for s_sendmsg
v2 by Timur Kristóf:
Do not add the affinity for instructions that can't write m0
reliably, such as readlane-like instructions on GFX8.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
Kenneth Graunke [Wed, 3 May 2023 09:05:16 +0000 (02:05 -0700)]
intel/compiler: UNDEF SubgroupInvocation's register
This value takes a few instructions to create, involving expanding
V-immediates, adding 8 for SIMD16, and so on. We can mark it UNDEF
so that it's clear that although these are partial writes, we are
actually defining the entire value.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
Kenneth Graunke [Wed, 3 May 2023 08:49:56 +0000 (01:49 -0700)]
intel/compiler: UNDEF comparisons with smaller than 32-bit
Comparisons which produce 32-bit boolean results (0 or 0xFFFFFFFF)
but operate on 16-bit types would first generate a CMP instruction
with W or HF types, before expanding it out. This CMP is a partial
write, which leads us to think the register may contain some prior
contents still. When placed in a loop, this causes its live range
to extend beyond its real life time.
Mark the register with UNDEF first so that we know that no prior
contents exist and need to be preserved.
This affects:
flt32, fge32, feq32, fneu32, ilt32, ult32, ige32, uge32, ieq32, ine32
On one of Cyberpunk 2077's most complex compute shaders, this reduces
the maximum live registers from 696 to 537 (22.8%). Together with the
next patch, Cyberpunk's spills and fills are cut by 10.23% and 9.19%,
respectively.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
Faith Ekstrand [Thu, 4 May 2023 04:11:35 +0000 (23:11 -0500)]
vulkan: Document vk_physical_device::supported_features
While we're here, move it to after supported extensions to stay
consistent with the vk_physical_device_init parameters.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Constantine Shablya <constantine.shablya@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22845>
antonino [Thu, 4 May 2023 14:54:03 +0000 (16:54 +0200)]
zink: take location_frac into account in pv emulation
The pv mode emulation code was not taking into account the location_frac
of variables, they where beeing stored in a 1D array leading to
collisions.
Fixes:
5a4083349f3 ("zink: add provoking vertex mode lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22856>
Illia Polishchuk [Fri, 21 Apr 2023 07:45:47 +0000 (10:45 +0300)]
nir: switch to a normal sampler for ARB program with not depth textures
It is undefined behavior when an ARB assembly or shadow2d GLSL func
uses SHADOW2D target with a texture in not depth format.
In this case AMD and NVIDIA automatically replaces SHADOW sampler
with a normal sampler and some games like Penumbra Overture which abuses
this UB works fine but breaks with mesa.
Replace the shadow sampler with a normal one here by recompiling
the ARB program variant
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>
Illia Polishchuk [Mon, 27 Mar 2023 17:11:15 +0000 (20:11 +0300)]
drirc: add allow_sampled_tex_copy option
From OpenGL spec 8.6
"An INVALID_OPERATION error is generated if the object bound to
READ_FRAMEBUFFER_BINDING is framebuffer complete and its effective
value of SAMPLE_BUFFERS (see section 9.2.3.1) is one"
But some games might do this
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>
Collabora's Gfx CI Team [Wed, 3 May 2023 06:16:46 +0000 (06:16 +0000)]
Uprev Piglit to
79a084c56b6dd79f7c3a97b57a72963121ebb1e6
https://gitlab.freedesktop.org/mesa/piglit/-/compare/
355ad6bcb2cb3d9e030b7c6eef2b076b0dfb4d63...
79a084c56b6dd79f7c3a97b57a72963121ebb1e6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22548>
Donald Robson [Wed, 3 May 2023 13:50:36 +0000 (14:50 +0100)]
pvr: Move heap initialisation out of pvr_winsys_helper.
This code will not be used by the new KMD, so it is being moved out of
this shared code area.
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22826>