Joseph Huber [Wed, 19 Jul 2023 23:03:02 +0000 (18:03 -0500)]
[libc] Remove global constructors on File type
The `File` interface currently has a destructor to delete the buffer if
it is owned by the file. This is problematic for the globally allocated
`stdout`, `stdin`, and `stderr` files. This causes the file interface to
have global constructors to initialize the destructors to use these.
However, these never use the destructors because they don't own the
buffer. This patch removes the destructor and calls in manually in the
close implementation. The platform close should never need to access the
buffer and it needs to be done before clearing the whole thing, so this
should work.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D155762
Alex Bradbury [Thu, 20 Jul 2023 13:05:17 +0000 (14:05 +0100)]
[RISCV][NFC] Use templated getSubtarget in RISCVExpandPseudo::runOnMachineFunction
This avoids a static_cast.
Alexander Belyaev [Thu, 20 Jul 2023 13:08:19 +0000 (15:08 +0200)]
[mlir] Add UBDialect to BUILD.bazel.
Markus Böck [Wed, 19 Jul 2023 14:35:54 +0000 (16:35 +0200)]
[mlir][LLVM] Convert `noalias` parameters into alias scopes during inlining
Currently, inlining a function with a `noalias` parameter leads to a large loss of optimization potential as the `noalias` parameter, an important hint for alias analysis, is lost completely.
This patch fixes this with the same approach as LLVM by annotating all users of the `noalias` parameter with appropriate alias and noalias scope lists.
The implementation done here is not as sophisticated as LLVMs, which has more infrastructure related to escaping and captured pointers, but should work in the majority of important cases.
Any deficiency can be addressed in future patches.
Related LLVM code: https://github.com/llvm/llvm-project/blob/
27ade4b554774187d2c0afcf64cd16fa6d5f619d/llvm/lib/Transforms/Utils/InlineFunction.cpp#L1090
Differential Revision: https://reviews.llvm.org/D155712
Danila Malyutin [Thu, 20 Jul 2023 07:10:26 +0000 (10:10 +0300)]
[Statepoint] Use correct RegisterClass for spilling
Copy propagation might have changed the register class of the register
Differential Revision: https://reviews.llvm.org/D155792
Timm Bäder [Wed, 19 Jul 2023 11:55:43 +0000 (13:55 +0200)]
[clang][Interp][NFC] Add InterpStack::dump()
Simon Pilgrim [Thu, 20 Jul 2023 12:48:56 +0000 (13:48 +0100)]
[X86] LowerTRUNCATE - use LowerTruncateVecPackWithSignBits for prefer-256 bit AVX512 cases during type legalization
If the AVX512 target will split the 512-bit vector truncation then try to use PACKSS/PACKUS first.
David Green [Thu, 20 Jul 2023 12:53:18 +0000 (13:53 +0100)]
[AArch64] Update bswap cost test. NFC
See D155806
Martin Braenne [Thu, 20 Jul 2023 07:12:50 +0000 (07:12 +0000)]
[clang][dataflow] Add an `operator<<` for `OptionalTypeIdentifier`.
When tests fail in UncheckedOptionalAccessModelTest.cpp, this prints the name of the optional type instead of a blob of hex.
Reviewed By: ymandel
Differential Revision: https://reviews.llvm.org/D155788
Nikita Popov [Thu, 20 Jul 2023 12:49:08 +0000 (14:49 +0200)]
[LVI] Check ConstantFoldCompareInstOperands() failure (NFCI)
I don't believe this can happen right now (because we're only
working on icmps and as such can't hit the current fcmp null
paths), but this will be possible in the future when icmp
constant expressions are removed.
Nikita Popov [Thu, 20 Jul 2023 12:47:50 +0000 (14:47 +0200)]
[ConstantFolding] Update failure behavior documentation (NFC)
These functions may return null or a constant expression on failure,
depending on whether such a constant expression is still supported.
wanglei [Mon, 17 Jul 2023 23:03:03 +0000 (07:03 +0800)]
[LoongArch] Fix instruction definitions that were incorrectly specified input/output operands
This has no impact on the current assembly functionality but will affect
the patches for the subsequent code generation.
Alex Bradbury [Thu, 20 Jul 2023 12:48:15 +0000 (13:48 +0100)]
[RISCV] Don't include X1 in the X0_PD register pair
Zdinx on RV32 defines the D instructions as taking even register pairs,
and specifies that if using X0 when as a destination then X1 won't be
written, and if using X0 as a source then the value is still all 0s
(i.e. X1 isn't read). Therefore, it's incorrect to model X0_PD as having
X1 as a subregister. This will also be the case for register pairs in
Zacas and the P extension (and this patch takes the same approach as
D95588 does).
This patch introduces a dummy register that is solely used as a subreg
alongside X0 in X0_PD. An earlier version of the patch had a minor
effect on register allocation in some tests, which is now avoided by:
1) Adding RISCV::DUMMY_REG_PAIR_WITH_X0 to RISCVRegisterInfo::getReservedRegs
2) Defining a new register class that includes DUMMY_REG_PAIR_WITH_X0
Differential Revision: https://reviews.llvm.org/D153974
Jon Chesterfield [Thu, 20 Jul 2023 12:43:17 +0000 (13:43 +0100)]
[libc][amdgpu] Tolerate different install directories for hsa.h
HSA headers might be under a hsa/ directory or might not.
This scheme matches the one used by the openmp amdgpu plugin.
Reviewed By: jhuber6, jplehr
Differential Revision: https://reviews.llvm.org/D155812
Martin Braenne [Thu, 20 Jul 2023 08:53:41 +0000 (08:53 +0000)]
[clang][dataflow] Print the source line if we saw unexpected diagnostics in tests.
This makes it easier to determine which line the unexpected happened on; previously, we would only get the line number.
Reviewed By: ymandel
Differential Revision: https://reviews.llvm.org/D155802
Weining Lu [Thu, 20 Jul 2023 11:35:37 +0000 (19:35 +0800)]
[LoongArch][NFC] Remove incorrect notes in clang tests
The assertions in these two tests were not auto-generated by update_cc_test_checks.py. Remove them.
Nikita Popov [Thu, 20 Jul 2023 12:17:07 +0000 (14:17 +0200)]
[InstCombine] Avoid ConstantExpr::getAnd() (NFCI)
In preparation for removing and constant expressions.
LLVM GN Syncbot [Thu, 20 Jul 2023 12:08:42 +0000 (12:08 +0000)]
[gn build] Port
a2160dd34d56
Timm Bäder [Thu, 20 Jul 2023 08:51:29 +0000 (10:51 +0200)]
[clang][Interp][NFC] Add a debugging assertion
We will probably have to remove this at some point, but until then, make
sure we're not running into much-harder-to-debug problems later on.
yrong [Thu, 20 Jul 2023 12:00:10 +0000 (20:00 +0800)]
[libc++][ranges] Implement P2474R2(`views::repeat`).
- Implement https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2022/p2474r2.html
- Implement LWG3875(https://cplusplus.github.io/LWG/issue3875).
Depends on D151629
Reviewed By: #libc, Mordante, philnik, var-const
Differential Revision: https://reviews.llvm.org/D141699
Guray Ozen [Thu, 20 Jul 2023 10:26:35 +0000 (12:26 +0200)]
[mlir][nvgpu] Add `mbarrier.arrive.expect_tx` and `mbarrier.try_wait.parity`
This work adds two Ops:
`mbarrier.arrive.expect_tx` performs expect_tx `mbarrier.barrier` returns `mbarrier.barrier.token`
`mbarrier.try_wait.parity` waits on `mbarrier.barrier` and `mbarrier.barrier.token`
`mbarrier.arrive.expect_tx` is one of the requirement to enable H100 TMA support.
Depends on D154074 D154076 D154059 D154060
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D154094
Thorsten Schütt [Fri, 14 Jul 2023 08:48:25 +0000 (10:48 +0200)]
[GIsel][AArch64] extend legalization of G_INSERT_VECTOR_ELT
Fixes https://github.com/llvm/llvm-project/issues/63826
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D155274
Ilya Leoshkevich [Thu, 20 Jul 2023 11:28:28 +0000 (13:28 +0200)]
[TableGen][CodeEmitterGen] Avoid empty OpNum switches in getOperandBitOffset()
getOperandBitOffset() causes the following warning on MSVC:
E:\llvm\ninja\lib\Target\SystemZ\SystemZGenMCCodeEmitter.inc(15414): warning C4060: switch statement contains no 'case' or 'default' labels
Do not emit empty OpNum switches.
Reviewed By: RKSimon, uweigand
Differential Revision: https://reviews.llvm.org/D155805
Simon Pilgrim [Thu, 20 Jul 2023 11:11:48 +0000 (12:11 +0100)]
[DAG] ShrinkDemandedConstant - early-out for empty DemandedBits/Elts
Leave this to constant folding in SimplifyDemandedBits
Fixes #63975
Tobias Gysi [Thu, 20 Jul 2023 08:13:17 +0000 (08:13 +0000)]
[mlir][llvm] Add branch weight op interface
This revision adds a branch weight op interface for the call / branch
operations that support branch weights. It can be used in the LLVM IR
import and export to simplify the branch weight conversion. An
additional mapping between call operations and instructions ensures
the actual conversion can be done in the module translation itself,
rather than in the dialect translation interface. It also has the
benefit that downstream users can amend custom metadata to the call
operation during the export to LLVM IR.
Reviewed By: zero9178, definelicht
Differential Revision: https://reviews.llvm.org/D155702
Michael Halkenhaeuser [Tue, 18 Jul 2023 16:56:12 +0000 (12:56 -0400)]
[clang][OpenMP] Add interop support for multiple depend clauses
This patch removes the constraint of the `interop` directive where only a single
`depend` clause was allowed.
Differential Revision: https://reviews.llvm.org/D155692
Bryan Chan [Thu, 20 Jul 2023 10:04:29 +0000 (06:04 -0400)]
[Clang][AArch64][SME] Generate target features from +(no)sme.* options
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D142702
Bryan Chan [Thu, 20 Jul 2023 10:04:14 +0000 (06:04 -0400)]
[Clang][AArch64][SME] Add outer product intrinsics
This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):
- svmopa_za32[_bf16]_m // also for s8, u8, f16, f32
- svmops_za32[_bf16]_m // also for s8, u8, f16, f32
- svsumopa_za32[_s8]_m
- svsumops_za32[_s8]_m
- svusmopa_za32[_u8]_m
- svusmops_za32[_u8]_m
When the sme-f64f64 feature is enabled, the following intrinsics are supported:
- svmopa_za64_f64_m
- svmops_za64_f64_m
When the sme-i16i64 feature is enabled, the following intrinsics are supported:
- svmopa_za64[_s16]_m // also for u16
- svmops_za64[_s16]_m // also for u16
- svsumopa_za64[_s16]_m
- svsumops_za64[_s16]_m
- svusmopa_za64[_u16]_m
- svusmops_za64[_u16]_m
Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D134681
Bryan Chan [Thu, 20 Jul 2023 10:03:55 +0000 (06:03 -0400)]
[Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile
This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):
- svaddha_za32[_u32]_m // also for s32
- svaddva_za32[_u32]_m // also for s32
- svaddha_za64[_u64]_m // also for s64
- svaddva_za64[_u64]_m // also for s64
The _za64 versions are available only when the sme-i16i64 feature is enabled.
Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D134680
Bryan Chan [Thu, 20 Jul 2023 09:58:45 +0000 (05:58 -0400)]
[Clang][AArch64][SME] Add intrinsics for reading streaming vector length
This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):
- svcntsb
- svcntsh
- svcntsw
- svcntsd
Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D134679
Bryan Chan [Thu, 20 Jul 2023 09:51:19 +0000 (05:51 -0400)]
[Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)
This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):
- svldr_vnum_za
- svstr_vnum_za
Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D134678
Bryan Chan [Thu, 20 Jul 2023 09:50:46 +0000 (05:50 -0400)]
[Clang][AArch64][SME] Add ZA zeroing intrinsics
This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):
- svzero_mask_za
- svzero_za
Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D134677
Bryan Chan [Thu, 20 Jul 2023 09:50:16 +0000 (05:50 -0400)]
[Clang][AArch64][SME] Add vector read/write (mova) intrinsics
This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):
- svread_hor_za8[_s8]_m // also for u8
- svread_hor_za16[_s16]_m // also for u16, f16, bf16
- svread_hor_za32[_s32]_m // also for u32, f32
- svread_hor_za64[_s64]_m // also for u64, f64
- svread_hor_za128[_s8]_m // also for s16, s32, s64, u8, u16, u32, u64, bf16, f16, f32, f64
- svread_ver_za8[_s8]_m // also for u8
- svread_ver_za16[_s16]_m // also for u16, f16, bf16
- svread_ver_za32[_s32]_m // also for u32, f32
- svread_ver_za64[_s64]_m // also for u64, f64
- svread_ver_za128[_s8]_m // also for s16, s32, s64, u8, u16, u32, u64, bf16, f16, f32, f64
- svwrite_hor_za8[_s8]_m // also for u8
- svwrite_hor_za16[_s16]_m // also for u16, f16, bf16
- svwrite_hor_za32[_s32]_m // also for u32, f32
- svwrite_hor_za64[_s64]_m // also for u64, f64
- svwrite_hor_za128[_s8]_m // also for s16, s32, s64, u8, u16, u32, u64, bf16, f16, f32, f64
- svwrite_ver_za8[_s8]_m // also for u8
- svwrite_ver_za16[_s16]_m // also for u16, f16, bf16
- svwrite_ver_za32[_s32]_m // also for u32, f32
- svwrite_ver_za64[_s64]_m // also for u64, f64
- svwrite_ver_za128[_s8]_m // also for s16, s32, s64, u8, u16, u32, u64, bf16, f16, f32, f64
Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen, kmclaughlin
Differential Revision: https://reviews.llvm.org/D128648
Simon Pilgrim [Thu, 20 Jul 2023 09:35:44 +0000 (10:35 +0100)]
[DAG] hoistLogicOpWithSameOpcodeHands - ensure SIGN_EXTEND_INREG nodes have the same extension value type
Fix bug in the check for matching SIGN_EXTEND_INREG types
Simon Pilgrim [Thu, 20 Jul 2023 09:25:40 +0000 (10:25 +0100)]
[X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i2) fold
David Green [Thu, 20 Jul 2023 09:34:05 +0000 (10:34 +0100)]
[LV][AArch64] Fix reductions costs in strict-fadd-cost.ll. NFC
These tests were originally added in
0aff1798b5721d5f95d16f465b99d, where they
were measuring the cost of fadd and fmuladd reductions, which should be fairly
high cost. For some reason, due to the forced vector factors, the debug costs
of each instruction are printed twice by the vectorizer. Once as if the
instruction is a simple fadd/fmuladd, and later with the correct reduction
cost.
In
d827865e9f778f5b27edb2afe003c2a the costs were updated to match the first
print statements, where they would be better to match the second to test the
cost of the reduction.
This patch returns them to testing the original reduction costs.
Ivan Butygin [Fri, 30 Jun 2023 18:51:20 +0000 (20:51 +0200)]
[mlir] Add `ub` dialect and `poison` op.
Add new dialect boilerplate and `poison` op definition.
Discussion: https://discourse.llvm.org/t/rfc-poison-semantics-for-mlir/66245/24
Differential Revision: https://reviews.llvm.org/D154248
wangpc [Thu, 20 Jul 2023 09:16:05 +0000 (17:16 +0800)]
[NFC][RISCV] Rewrite TableGen files using named arguments
To simplify code and show the usage of named arguments.
Reviewed By: michaelmaitland, MaskRay
Differential Revision: https://reviews.llvm.org/D154067
LLVM GN Syncbot [Thu, 20 Jul 2023 08:55:09 +0000 (08:55 +0000)]
[gn build] Port
1c154bd75515
LLVM GN Syncbot [Thu, 20 Jul 2023 08:55:08 +0000 (08:55 +0000)]
[gn build] Port
049d6a3f428e
Sylvestre Ledru [Thu, 20 Jul 2023 08:54:54 +0000 (10:54 +0200)]
Revert "[CUDA][HIP] Use the same default language std as C++"
This reverts commit
2d1d07152bd26b001dedec3400b4b01d3bb11622.
Markus Böck [Thu, 20 Jul 2023 07:53:38 +0000 (09:53 +0200)]
[mlir][LLVM] Handle access groups during inlining
Handling access groups is luckily rather trivial: Any access groups from the call instruction are simply appended to any memory operations.
This is similar to one of the steps when handling alias scopes.
This patch nevertheless implements it as a separate function purely for readability purposes as it uses a different interface than alias scopes.
Differential Revision: https://reviews.llvm.org/D155795
Matthias Springer [Thu, 20 Jul 2023 08:20:36 +0000 (10:20 +0200)]
[mlir] Remove some code duplication between `Builders.cpp` and `FoldUtils.cpp`
Also update the documentation of `Operation::fold`, which did not take into account in-place foldings.
Differential Revision: https://reviews.llvm.org/D155691
Weining Lu [Thu, 20 Jul 2023 08:09:34 +0000 (16:09 +0800)]
[LoongArch][NFC] Revise preprocessor test init-loongarch.c
- Add `--match-full-lines` to FileCheck invocations.
- Remove useless `grep __loongarch_`s.
Matthias Springer [Thu, 20 Jul 2023 08:11:44 +0000 (10:11 +0200)]
[mlir][IR] Implement proper folder for `IsCommutative` trait
Commutative ops were previously folded with a special rule in `OperationFolder`. This change turns the folding into a proper `OpTrait` folder.
Differential Revision: https://reviews.llvm.org/D155687
Advenam Tacet [Tue, 18 Jul 2023 19:15:13 +0000 (21:15 +0200)]
[ASan][libc++] Annotating std::deque with all allocators
This patch is part of our efforts to support container annotations with (almost) every allocator.
Annotating std::deque with default allocator is implemented in D132092.
Support in ASan API exests since rG1c5ad6d2c01294a0decde43a88e9c27d7437d157.
The motivation for a research and those changes was a bug, found by Trail of Bits, in a real code where an out-of-bounds read could happen as two strings were compared via a `std::equals` function that took `iter1_begin`, `iter1_end`, `iter2_begin` iterators (with a custom comparison function).
When object `iter1` was longer than `iter2`, read out-of-bounds on `iter2` could happen. Container sanitization would detect it.
If you have any questions, please email:
- advenam.tacet@trailofbits.com
- disconnect3d@trailofbits.com
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D146815
Edoardo Sanguineti [Thu, 20 Jul 2023 08:14:07 +0000 (08:14 +0000)]
[libc++] Fix tests for the runtime assertions in <barrier>
As @ldionne pointed out to me in a newer revision, there is a //REQUIRE comment in both files edited by this patch that prevents the test to run on some platforms where it should actually run.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D155755
David Green [Thu, 20 Jul 2023 08:12:05 +0000 (09:12 +0100)]
[DAG][AArch64] Fix truncated vscale constant types
It appears that vscale values truncated to i1 causes mismatches in the constant
types when created in getNode. https://godbolt.org/z/TaaTo86ne.
Differential Revision: https://reviews.llvm.org/D155626
Ilya Leoshkevich [Thu, 20 Jul 2023 08:10:16 +0000 (10:10 +0200)]
[TableGen][CodeEmitterGen] Add support for querying operand bit offsets
In order to generate relocations or to apply fixups after the layout
has been computed, the targets need to know the offsets of the
respective operands. There are indirect ways to figure them out in some
cases, for example, on SystemZ, the first memory operand is always at
offset 2, and the second one is always at offset 4. But there are no
such tricks for the immediate operands on SystemZ, so one has to refer
to individual instruction encodings.
This information, however, is available to TableGen. Generate
the getOperandBitOffset() method to access it, and use it to simplify
getting memory operand offsets on SystemZ. This also paves the way for
implementing symbolic immediates on this platform.
For the multi-lit operands, getOperandBitOffset() returns the offset of
the first lit.
An alternative way to obtain offsets would be to pass them to the
encoder methods, but this would require reworking all targets. Also,
VarLenCodeEmitter already does this, but adopting it requires
reworking the respective targets without other significant benefits.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D155329
Rik Huijzer [Thu, 20 Jul 2023 08:09:34 +0000 (10:09 +0200)]
[MLIR][Tensor] Avoid crash on negative dimensions
In https://reviews.llvm.org/D151611, a check was added to the tensor verifier to
emit an error on negative tensor dimensions. This check allowed for dynamic
dimensions, hence negative dimensions were still able to get through the verifier.
This is a problem in situations such as #60558, where the dynamic dimension is
converted to a static (and possibly negative) dimension by another pass in the
compiler. This patch fixes that by doing another check during the
`StaticTensorGenerate` conversion, and return a failure if the dimension is
negative.
As a side-note, I have to admit that I do not know why returning a failure in
`StaticTensorGenerate` gives a nice "tensor dimensions must be non-negative"
error. I suspect that the verifier runs again when `return failure()` is called,
but I am not sure.
Fixes #60558.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D155728
wangpc [Thu, 20 Jul 2023 08:02:03 +0000 (16:02 +0800)]
[TableGen] Support named arguments
We provide a way to specify arguments in the form of `name=value`
so that we don't have to specify all optional arguments before the
one we'd like to change. Required arguments can alse be specified
in this way.
Note that the argument can only be specified once regardless of
the way (named or positional) to specify and positional arguments
should be put before named arguments.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D152998
Fangrui Song [Thu, 20 Jul 2023 07:42:38 +0000 (00:42 -0700)]
[llvm-readobj] Print <null> for relocation target with an empty name
For a relocation, we don't differentiate the two cases:
* the symbol index is 0
* the symbol index is non zero, the type is not STT_SECTION, and the name is empty. Clang generates such local symbols for RISC-V linker relaxation.
So we may print
```
Offset Info Type Symbol's Value Symbol's Name + Addend
000000000000001c 0000000100000039 R_RISCV_32_PCREL
0000000000000000 0
// llvm-readobj
0x1C R_RISCV_32_PCREL - 0x0
```
while GNU readelf prints "<null>", which is clearer. Let's match the GNU behavior.
Related to https://reviews.llvm.org/D81842
```
000000000000001c 0000000100000039 R_RISCV_32_PCREL
0000000000000000 <null> + 0
// llvm-readobj
0x1C R_RISCV_32_PCREL <null> 0x0
```
Reviewed By: jhenderson, kito-cheng
Differential Revision: https://reviews.llvm.org/D155353
Fangrui Song [Thu, 20 Jul 2023 07:39:01 +0000 (00:39 -0700)]
[llvm-readobj][test] Pre-commit an empty symbol name test for D155353
wangpc [Thu, 20 Jul 2023 07:16:21 +0000 (15:16 +0800)]
[TableGen][NFC] Remove unreachable code
The removed code assumed that we can define classes inside a multiclass,
so the name of outer multiclass is concatenated to the qualified name.
But for current TableGen grammar, we can't define classes in multiclass,
so it is unnecessary.
This commit is requested in D152998.
Corentin Jabot [Thu, 20 Jul 2023 07:17:56 +0000 (09:17 +0200)]
[clang-tools-extra] the message in a static_assert is not always a string literal
Fixes build failure introduce by 47ccfd7.
Nuno Lopes [Thu, 20 Jul 2023 07:14:43 +0000 (08:14 +0100)]
[InstCombineVectorOps] Use poison instead of undef as placeholder [NFC]
Undef was being used to populate unused vector lanes.
While at it, switch extractelement to use poison as the OOB value (per LangRef)
Craig Topper [Thu, 20 Jul 2023 07:03:44 +0000 (00:03 -0700)]
[RISCV] Sink more common code from RVInst/RVInst16 into RVInstCommon. NFC
Reviewed By: wangpc
Differential Revision: https://reviews.llvm.org/D155787
Fangrui Song [Thu, 20 Jul 2023 07:06:47 +0000 (00:06 -0700)]
[WebAssembly] Use MapVector to stabilize iteration order after D150803
StringMap iteration order is not guaranteed to be deterministic
(https://llvm.org/docs/ProgrammersManual.html#llvm-adt-stringmap-h).
Fangrui Song [Thu, 20 Jul 2023 07:02:06 +0000 (00:02 -0700)]
[WebAssembly] Use SetVector to stabilize iteration order after D120365
StringMap iteration order is not guaranteed to be deterministic
(https://llvm.org/docs/ProgrammersManual.html#llvm-adt-stringmap-h).
Corentin Jabot [Tue, 1 Nov 2022 12:37:12 +0000 (13:37 +0100)]
[Clang] Implement P2741R3 - user-generated static_assert messages
Reviewed By: #clang-language-wg, aaron.ballman
Differential Revision: https://reviews.llvm.org/D154290
Freddy Ye [Thu, 20 Jul 2023 06:30:46 +0000 (14:30 +0800)]
[X86] Add AVX-VNNI-INT16 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei, skan
Differential Revision: https://reviews.llvm.org/D155145
Fangrui Song [Thu, 20 Jul 2023 06:30:30 +0000 (23:30 -0700)]
.debug_gnu_pub{names,types}: Stabilize iteration order
StringMap iteration order is not guaranteed to be deterministic
(https://llvm.org/docs/ProgrammersManual.html#llvm-adt-stringmap-h).
Sort by DIE offset (which looks like a pre-order traversal order).
Danila Malyutin [Wed, 19 Jul 2023 16:32:59 +0000 (19:32 +0300)]
[X86] Recognize standalone `(1 << nbits) - 1` pattern as bzhi
This can be thought as a subcase of `x & ((1 << nbits) - 1)` where x == -1
Differential Revision: https://reviews.llvm.org/D155622
Danila Malyutin [Wed, 19 Jul 2023 18:00:08 +0000 (21:00 +0300)]
[X86][AArch64] Add additional extract_lowbits test
Check that vreg_width-1 mask is only removed for shifts
Differential Revision: https://reviews.llvm.org/D155734
Timm Bäder [Wed, 19 Jul 2023 13:58:40 +0000 (15:58 +0200)]
[clang][Interp][NFC] Add another assertion to InterpStack::peek()
Timm Bäder [Wed, 19 Jul 2023 11:53:18 +0000 (13:53 +0200)]
[clang][Interp][NFC] Fix a doc comment mixup
Timm Bäder [Wed, 19 Jul 2023 11:51:42 +0000 (13:51 +0200)]
[clang][Interp][NFC] Clear InterpStack::ItemTypes in clear()
Craig Topper [Thu, 20 Jul 2023 05:36:16 +0000 (22:36 -0700)]
[RISCV] Use the opcodestr and argstr arguments of Pseudo to simplify tablegen code. NFC
We can replace several "let AsmString =".
Freddy Ye [Thu, 20 Jul 2023 05:34:47 +0000 (13:34 +0800)]
[X86] Add SM4 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei, skan
Differential Revision: https://reviews.llvm.org/D155148
Fangrui Song [Thu, 20 Jul 2023 05:25:40 +0000 (22:25 -0700)]
[VirtualFileSystem] Use map to stabilize iteration order
StringMap iteration order is not guaranteed to be deterministic
(https://llvm.org/docs/ProgrammersManual.html#llvm-adt-stringmap-h).
Tested by `TEST_F(InMemoryFileSystemTest, DirectoryIteration)`.
Craig Topper [Thu, 20 Jul 2023 04:39:26 +0000 (21:39 -0700)]
[RISCV] Introduce a common tablegen base class for RVInst and RVInst16.
This gives us a common place to put the TSFlags and the Namespace.
Removes TSFlags declaration duplication for D155690.
Reviewed By: wangpc
Differential Revision: https://reviews.llvm.org/D155744
Fangrui Song [Thu, 20 Jul 2023 04:21:26 +0000 (21:21 -0700)]
[TableGen][GlobalISel] Use MapVector to stabilize iteration order after D153757
StringMap iteration order is not guaranteed to be deterministic
(https://llvm.org/docs/ProgrammersManual.html#llvm-adt-stringmap-h).
Fangrui Song [Thu, 20 Jul 2023 04:02:01 +0000 (21:02 -0700)]
[dsymutil] Sort entries in YamlDMO to stabilize print order
Similar to the llvm::sort call in DebugMapObject::print.
Fangrui Song [Thu, 20 Jul 2023 04:00:35 +0000 (21:00 -0700)]
[dsymutil] Remove unused function. NFC
Yaxun (Sam) Liu [Mon, 17 Jul 2023 21:50:12 +0000 (17:50 -0400)]
[CUDA][HIP] Use the same default language std as C++
Currently CUDA/HIP defines their own language standards in
LanguageStandards.def but they are redundant. They are the same as stdc++14.
The fact that CUDA/HIP uses c++* in option -std= indicates that they have the
same language standards as C++. The CUDA/HIP specific language features are
conveyed through language options, not language standards features. It makes
sense to let CUDA/HIP uses the same default language standard as C++.
Reviewed by: Siu Chi Chan, Artem Belevich
Differential Revision: https://reviews.llvm.org/D155539
Fixes: SWDEV-407685
Paul Kirth [Thu, 20 Jul 2023 03:33:36 +0000 (03:33 +0000)]
Revert "[lld] Preliminary fat-lto-object support"
This reverts commit
c9953d9891a6067549a78e7d07ca8eb6a7596792 and a
forward fix in
3a45b843dec1bca195884aa1c5bc56bd0e6755b4.
D14677 causes some failure on windows bots that the forward fix did not
address. Thus I'm reverting until the underlying cause can me triaged.
Kai Luo [Thu, 20 Jul 2023 03:18:05 +0000 (03:18 +0000)]
[RuntimeDyldChecker][NFC] Add `section_addr` to BNF in the comment.
Mel Chen [Tue, 27 Jun 2023 09:06:00 +0000 (02:06 -0700)]
[LV] Add tests for select-cmp reduction pattern. (NFC)
The test cases for selecting increasing integer induction variable.
Reviewed By: fhahn, shiva0217
Differential Revision: https://reviews.llvm.org/D153936
Fangrui Song [Thu, 20 Jul 2023 02:59:13 +0000 (19:59 -0700)]
AppleAcceleratorTable: Use MapVector to stabilize iteration order after D153066
Use a MapVector to stabilize the order and simplify future changes like
D142862 that change the StringMap hash function.
Fangrui Song [Thu, 20 Jul 2023 02:50:36 +0000 (19:50 -0700)]
AccelTable: Use MapVector to stabilize iteration order
Entries of the same DJB hash are in the hash lookup table/name table are
ordered by the iteration order of `Entries` (a StringMap). Change
`Entries` to a MapVector to stabilize the order and simplify future
changes like D142862 that change the StringMap hash function.
LLVM GN Syncbot [Thu, 20 Jul 2023 02:44:21 +0000 (02:44 +0000)]
[gn build] Port
c6f66de21af0
Kelvin Li [Tue, 11 Jul 2023 20:15:50 +0000 (16:15 -0400)]
[flang] Add PowerPC vec_convert, vec_ctf and vec_cvf intrinsic
Co-authored-by: Paul Scoropan <1paulscoropan@gmail.com>
Differential Revision: https://reviews.llvm.org/D155235
Freddy Ye [Thu, 20 Jul 2023 02:23:52 +0000 (10:23 +0800)]
[X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D155147
Lang Hames [Thu, 20 Jul 2023 02:16:21 +0000 (19:16 -0700)]
[llvm-jitlink] Generalize statistics gathering / reporting.
Moves the llvm-jitlink tool statistics out of the Session struct and into a new
LLVMJITLinkStatistics class.
Also removes the `-show-sizes` option. Each statistic added will now have its
own option. The two previous stats (total size of all blocks before pruning and
after fixups) are now available as -pre-prune-total-block-size and
-post-fixup-total-block-size.
This change should make it easier to add new statistics.
LLVM GN Syncbot [Thu, 20 Jul 2023 01:45:27 +0000 (01:45 +0000)]
[gn build] Port
fc3b7874b6c9
Freddy Ye [Thu, 20 Jul 2023 01:44:21 +0000 (09:44 +0800)]
[X86] Add SHA512 instructions.
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D155146
Fangrui Song [Thu, 20 Jul 2023 01:17:46 +0000 (18:17 -0700)]
[ELF][test] Add REQUIRES: x86 after D146778
Fangrui Song [Thu, 20 Jul 2023 00:24:36 +0000 (17:24 -0700)]
[lld-macho] Use fixed chunk size for UUID
Chunk size decided by the thread count makes the UUID less deterministic
(e.g. across machines with different core counts.)
Follow ELF and just use a fixed chunksize.
Fixes: https://github.com/llvm/llvm-project/issues/63961
Reviewed By: #lld-macho, keith
Differential Revision: https://reviews.llvm.org/D155761
Fangrui Song [Thu, 20 Jul 2023 00:21:57 +0000 (17:21 -0700)]
[llvm-libtool-darwin] Use MapVector to avoid relying on StringMap iteration order
Simplify future changes like D142862 that change the hash function.
Chris Bieneman [Thu, 20 Jul 2023 00:06:53 +0000 (19:06 -0500)]
Fix PPCBE
For real this time.
Chris Bieneman [Wed, 19 Jul 2023 23:52:52 +0000 (18:52 -0500)]
Fix big endian bot
I have yet again broken ppcbe. This should fix it.
Haowei Wu [Wed, 19 Jul 2023 23:22:29 +0000 (16:22 -0700)]
[libcxx] Fix copy_move.pass test
When LLVM is built under MSVC and libcxx ABI is set to 2, the
'copy_move.pass' test will unexpectedly pass. This patch mitigate
this issue by setting this test will only expecting FAIL when libcxx
ABI version is set to 1.
This is a re-land of
be9f55f4fff47badcdca17be5bcc0a4a15894739
Differential Revision: https://reviews.llvm.org/D155760
Fixes: https://github.com/llvm/llvm-project/issues/63442
Amara Emerson [Wed, 19 Jul 2023 23:47:38 +0000 (16:47 -0700)]
[AArch64][GlobalISel] Widen (<2 x s16> = G_BUILD_VECTOR) to <2 x s32>.
We don't support this as a argument or return type, it's always promoted to <2 x s32>.
Performing the widening prevents us from having selection failures due to unsupported
extends.
Fixes https://github.com/llvm/llvm-project/issues/58274
Keith Smiley [Wed, 19 Jul 2023 18:07:57 +0000 (11:07 -0700)]
[lld-macho] Implement -no_uuid
Since UUID generation in lld is fast this is rarely used but it can be
helpful to avoid temporary issues like https://github.com/llvm/llvm-project/issues/63961
Differential Revision: https://reviews.llvm.org/D155735
Louis Dionne [Wed, 19 Jul 2023 23:10:27 +0000 (19:10 -0400)]
[libc++] Revert "[libcxx] Fix copy_move.pass test"
This reverts commit
be9f55f4fff47badcdca17be5bcc0a4a15894739.
The commit was both not approved by the libc++ review group, and also
the only change it contained was incorrect.
Paul Kirth [Tue, 13 Jun 2023 21:39:14 +0000 (21:39 +0000)]
[gold] Add preliminary FatLTO support to the Gold plugin
This changes the definition if `isSectionBitcode` to only be valid for the
`.llvm.lto` section, since this API is only called from LTO, and the
`.llvmbc` section was not intended to be used for LTO. This allows the
gold plugin to keep its existing behavior without introducing any
significant changes.
Depends on D146778
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D152973
Paul Kirth [Fri, 24 Mar 2023 00:14:48 +0000 (00:14 +0000)]
[lld] Preliminary fat-lto-object support
This patch adds support to lld for --fat-lto-objects. We add a new
--fat-lto-objects flag to LLD, and slightly change how it chooses input
files in the driver when the flag is set.
Fat LTO objects contain both LTO compatible IR, as well as generated object
code. This allows users to defer the choice of whether to use LTO or not to
link-time. This is a feature available in GCC for some time, and makes the
existing -ffat-lto-objects flag functional in the same way as GCC's.
If the --fat-lto-objects option is passed to LLD and the input files are fat
object files, then the linker will chose the LTO compatible bitcode sections
embedded within the fat object and link them together using LTO. Otherwise,
standard object file linking is done using the assembly section in the object
files.
Original RFC: https://discourse.llvm.org/t/rfc-ffat-lto-objects-support/63977
Depends on D146777
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D146778
Chris Bieneman [Tue, 18 Jul 2023 00:33:16 +0000 (19:33 -0500)]
[DX] Fix PSV resource serialization
When writing this initially I missed including the resource stride.
This change adds the resources stride to the serialized value.
I've also extended the testing and error reporting around parsing PSV
information. This adds tests to verify that the reader produces
meaningful error messages for malformed DXContainer files, and a test
that verifies the resource stride is respected in the reader even if
the stride isn't an expected or known value (as would happen if the
format changes in the future).
This is part of #59479.
Reviewed By: bogner, bob80905
Differential Revision: https://reviews.llvm.org/D155143
Alex Voicu [Wed, 19 Jul 2023 22:57:12 +0000 (23:57 +0100)]
[Clang][CodeGen] Follow-up for `vtable`, `typeinfo` et al. are globals
https://reviews.llvm.org/rG8acdcf4016876d122733991561be706b64026e73 didn't include handling for the fact that `throw`'s implementation takes a pointer to a type's `typeinfo` struct, which implies that its signature needs to change as well. This corrects that and adds a test.
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D155759
Haowei Wu [Wed, 19 Jul 2023 22:37:40 +0000 (15:37 -0700)]
[libcxx] Fix copy_move.pass test
When LLVM is built under MSVC and libcxx ABI is set to 2, the
'copy_move.pass' test will unexpectedly pass. This patch mitigate this
issue by setting this test will only expecting FAIL when libcxx ABI
version is set to 1.
Differential Revision: https://reviews.llvm.org/D155760
Fixes: https://github.com/llvm/llvm-project/issues/63442