Baruch Siach [Tue, 2 May 2023 04:47:30 +0000 (07:47 +0300)]
doc: signature: describe how to enable ECDSA
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Baruch Siach [Tue, 2 May 2023 04:47:29 +0000 (07:47 +0300)]
doc: signature: update algorithm addition description
U-Boot now uses the U_BOOT_CRYPTO_ALGO() macro.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Baruch Siach [Tue, 2 May 2023 04:47:28 +0000 (07:47 +0300)]
doc: signature: update algorithms support description
U-Boot supports more hash and verification algorithms these days.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 11 May 2023 12:40:33 +0000 (08:40 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Various fixes for Google chromebooks
- Various minor enhancements for coreboot
Simon Glass [Thu, 4 May 2023 22:51:01 +0000 (16:51 -0600)]
x86: samus: Adjust TPL start and pre-reloc memory size
Move the TPL up a little to make room for the refcode binary blob. Also
increase the pre-relocation memory to make space for recent additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:51:00 +0000 (16:51 -0600)]
x86: samus: Don't include audio and SATA in TPL
These are not used in TPL so disable the drivers to save space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:59 +0000 (16:50 -0600)]
x86: Simplify cpu_jump_to_64bit_uboot()
This copies the cpu_call64() function to memory address and then jumps to
it. This seems to work correctly even when called from SPL, which is
running from SPI flash.
Drop the copy as it is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:58 +0000 (16:50 -0600)]
spl: Commit MTRRs only in board_init_f_r()
We don't need to commit the SPI-flash MTRR change immediately, since it is
now done in the board_init_f_r(). Also this causes chromebook_link64 to
hang, presumably since we are still running from CAR (Cache-as-RAM) in
SPL. Coral handles this OK, perhaps since it is running from a different
memory area, but it has no effect on Coral anyway.
Drop the extra mtrr_commit() in the SPL implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:57 +0000 (16:50 -0600)]
x86: spl: Avoid using init_cache_f_r() from SPL
This function is used by U-Boot proper. It does not set up MTRRs when SPL
is enabled, but we do want this done when it is called from SPL. In fact
it is confusing to use the same function from SPL, since there are quite
a few conditions there.
All init_cache_f_r() really does is commit the MTRRs and set up the cache.
Do this in the SPL's version of this function instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:55 +0000 (16:50 -0600)]
x86: Tidy up address for loading U-Boot from SPL
Use the binman symbols for this, to avoid hard-coding the value. We could
use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to
obtain the offset and size through the same mechanism.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 9 May 2023 10:13:47 +0000 (18:13 +0800)]
x86: sysreset: Set up LPC only after relocation
Probing LPC can cause PCI enumeration to take place, which significantly
increases pre-relocation memory usage. Also, LPC is somtimes enabled
directly by SPL.
Adjust the logic to probe the LPC only after relocation. This allows
chromebook_link64 to start up without a much larger
CONFIG_SYS_MALLOC_F_LEN value.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:54 +0000 (16:50 -0600)]
x86: spl: Show debugging for BSS
Show the area of memory cleared for BSS, when debugging is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:53 +0000 (16:50 -0600)]
x86: mrc: Correct SPL debug message
SPL printf() does not normally support %#x so just use %x instead. Hex is
expected in U-Boot anyway.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:52 +0000 (16:50 -0600)]
x86: Tidy up availability of string functions
For now, just enable the fast-but-large string functions in 32-boot
U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit
builds since we only have 32-bit assembly.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 4 May 2023 22:50:51 +0000 (16:50 -0600)]
x86: Support debug UART in 64-bit mode
The debug UART is already set up in SPL, so there is no need to do
anything here. We must provide the (empty) function though.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:50 +0000 (16:50 -0600)]
x86: samus: Drop EFI_LOADER
This adds a lot of code so that it cannot be built with the binary
blobs. It is not used on this board. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:49 +0000 (16:50 -0600)]
x86: ivybridge: Ensure LPC is available for GPIO base
The bd82x6x_get_gpio_base() does not work if the LPC is not set up.
Probe it early to avoid this problem.
In chromebook_link64 this problem shows up as an inability to read
the GPIO straps for the memory type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:48 +0000 (16:50 -0600)]
sf: Rename spi-nor-tiny functions
The 'tiny' SPI nor functions have the same name as their big brothers,
which can be confusing. Use different names so it is clear which
version is in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:47 +0000 (16:50 -0600)]
sf: Guard against zero erasesize
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero
error. Check for this and return a proper error instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:46 +0000 (16:50 -0600)]
binman: Support writing symbols for ucode etypes
Allow symbol writing in these cases so that U-Boot can find the position
and size of U-Boot at runtime.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:45 +0000 (16:50 -0600)]
dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes:
7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:09 +0000 (16:55 -0600)]
coreboot: Enable ms command
This is useful when looking for tables in memory. Enable it for coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:08 +0000 (16:55 -0600)]
x86: nvme: coreboot: Enable NVMe
Enable support for NVMe storage devices. Update the driver to enable the
bus master bit, since coreboot does not do that automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:07 +0000 (16:55 -0600)]
nvme: Enable PCI bus mastering
U-Boot sets up devices ready for use, but coreboot does not. Enable this
so that NVMe works OK from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:06 +0000 (16:55 -0600)]
x86: coreboot: Show unimplemented sysinfo tags
Sometimes coreboot adds new tags that U-Boot does not know about. These
are silently ignored, but it is useful to at least know what we are
missing.
Add a way to collect this information. For Brya it shows:
Unimpl. 38 41 37 34 42 40
These are:
LB_TAG_PLATFORM_BLOB_VERSION
LB_TAG_ACPI_CNVS
LB_TAG_FMAP
LB_TAG_VBOOT_WORKBUF
LB_TAG_TYPE_C_INFO
LB_TAG_BOARD_CONFIG
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:05 +0000 (16:55 -0600)]
x86: coreboot: Log function names and line numbers
Turn these options on to make it easier to debug things.
Also enable dhrystone so we can get some measure of performance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:04 +0000 (16:55 -0600)]
x86: coreboot: Scan PCI after relocation
Enable this so that PCI devices can be used correctly without needing
to do a manual scan.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:03 +0000 (16:55 -0600)]
x86: coreboot: Document how to enable the debug UART
This is not obvious so add a little note about how it works.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:02 +0000 (16:55 -0600)]
x86: coreboot: Use a memory-mapped UART
This is much more common on modern hardware, so default to using it.
This does not affect the normal UART, but does allow the debug UART to
work, since it uses serial_out_shift(), etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:01 +0000 (16:55 -0600)]
pci: coreboot: Don't read regions when booting
When U-Boot is the second-stage bootloader, PCI is already set up. We
cannot read the regions from the device tree. There is no point anyway,
since PCI devices have already been allocated according to the regions
and it is not safe for U-Boot to make any changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes:
f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()")
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:00 +0000 (16:55 -0600)]
x86: Allow locating the UART from ACPI tables
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.
Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.
Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.
For now this only supports a memory-mapped 16550-style UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:59 +0000 (16:54 -0600)]
x86: coreboot: Collect the address of the ACPI tables
At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.
Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.
Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:58 +0000 (16:54 -0600)]
acpi: Move the table-finding functions into the libary
This is useful for other features. Move the function into library code
so it can be used outside just the 'acpi' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:57 +0000 (16:54 -0600)]
acpi: Create a new Kconfig for ACPI
We have several Kconfig options for ACPI, but all relate to specific
functions, such as generating tables and AML code.
Add a new option which controls including basic ACPI library code,
including the lib/acpi directory. This will allow us to add functions
which are available even if table generation is not supported.
Adjust the command to avoid a build error when ACPIGEN is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:56 +0000 (16:54 -0600)]
input: Flush the keyboard buffer before resetting it
If U-Boot is not the first-stage bootloader the keyboard may already be
set up. Make sure to flush any data before trying to reset it. This
avoids a long timeout / hang.
Add some comments and a log category while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:55 +0000 (16:54 -0600)]
x86: Adjust search range for sysinfo table
Avoid searching starting at 0 since this memory may not be available,
e.g. if protection against NULL-pointer access is enabled. The table
cannot be there anyway, since the first 1KB of memory was originally
used for the interrupt table and coreboot avoids it.
Start at 0x400 instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:54 +0000 (16:54 -0600)]
mtrr: Don't show an invalid CPU number
When U-Boot did not do the MP init, we don't get an actual CPU number
here. Skip printing it in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 9 May 2023 16:45:49 +0000 (12:45 -0400)]
Merge tag 'u-boot-rockchip-
20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
Eugen Hristev [Thu, 13 Apr 2023 11:36:45 +0000 (14:36 +0300)]
clk: rockchip: rk3588: add hardcoded assigned clocks values
The CRU is being probed with a default set of assigned clocks, which
are not implemented in the driver at all.
Hence, when clk_set_defaults is called, it fails with ENOENT.
This would not be a problem, as the CRU still handles all the required
clocks, and the assigned clocks are default configs which are preprogrammed
or not required for Uboot operations.
However, the rockchip reset driver is being bound by the same DT node
as CRU, as the reset driver has no DT node.
But, when probing the reset node, it will call again the clk_set_defaults
for the CRU node, and failing because of missing those specific clocks
in the rk3588 clock driver.
To avoid this, simply implement a basic set/get that will just return
success and the default corresponding rate for the required assigned clocks.
As those clocks were not supported in Uboot, not required for Uboot
operations, there is no need to do any different kind of initialization.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Wed, 12 Apr 2023 11:52:53 +0000 (12:52 +0100)]
rockchip: handle peripheral as well as otg dr_mode
The OTG port is identified by inspecting the "dr_mode" property which is
expected to be "otg" for this port. But it will work just as well as a
device controller when dr_mode is set to "peripheral", which may be
required if the mode detection pin is not set up correctly and the
device controller needs to be programmed to override this.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Wed, 12 Apr 2023 11:52:52 +0000 (12:52 +0100)]
rockchip: use standard dr_mode parsing function
Instead of duplicating the string values here, use usb_get_dr_mode() to
handle the property lookup and converting the values to an enum.
This is implemented with a switch in preparation for the next patch
which adds extra handling for peripheral mode.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Thu, 20 Apr 2023 09:42:30 +0000 (09:42 +0000)]
arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-order
use common one defined in rk356x-u-boot.dtsi.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Sat, 8 Apr 2023 09:33:42 +0000 (09:33 +0000)]
arm: dts: rk356x: Makefile: sort
sort alphanumerically.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Wed, 26 Apr 2023 02:23:56 +0000 (02:23 +0000)]
doc: rockchip: update list of Radxa ROCK (Pi) 4 boards
add Radxa ROCK (Pi) 4 variants.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Wed, 26 Apr 2023 02:23:55 +0000 (02:23 +0000)]
configs: rockchip: add Radxa ROCK 4C+
add defconfig for Radxa ROCK 4C+.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Wed, 26 Apr 2023 02:23:54 +0000 (02:23 +0000)]
arm: dts: rockchip: add Radxa ROCK 4C+
Linux commit
246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+
Add support for Radxa ROCK 4C+ SBC.
Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec
Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Wed, 26 Apr 2023 02:23:53 +0000 (02:23 +0000)]
configs: rockchip: rock-pi-4: use dtb for ROCK Pi 4A instead of 4B
rk3399-rock-pi-4a.dtb is enough for Radxa ROCK Pi 4A/B/A+/B+ and ROCK 4SE.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Wed, 26 Apr 2023 02:23:52 +0000 (02:23 +0000)]
arm: dts: rockchip: rock-pi-4: sync with Linux 6.3
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.
because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tianling Shen [Tue, 11 Apr 2023 10:14:49 +0000 (18:14 +0800)]
rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
The device tree is taken from the kernel linux-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=
004589ff9df5b75672a78b6c3c4cba93202b14c9
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Tue, 11 Apr 2023 07:20:40 +0000 (10:20 +0300)]
reset: reset-rockchip: fix trivial line spacing alignment
Fix line spacing aligment in bind function
Fixes:
760188c1aa5b ("rockchip: reset: support a (common) rockchip reset drivers")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Tue, 11 Apr 2023 07:17:56 +0000 (10:17 +0300)]
clk: rockchip: correct trivial typo in debug message
s/faile/failed in debug message
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Thu, 13 Apr 2023 14:11:03 +0000 (17:11 +0300)]
pci: pcie_dw_rockchip: release resources on failing probe
Implement a resource release mechanism on failing probe.
Without this, a strange situation can happen e.g. when init port fails,
or attempting to get the PHY fails, because the gpios have been
requested first, and if the user tries to do 'pci enum' again, the
driver will fail with 'can't find reset gpios' even if the gpios are
there, just because they were blocked by a previous probe attempt.
It is only natural to release the acquired resources if the probe fails,
just for consistency if nothing else.
This way on subsequent probe attempts, the user will get the same error
message, and not something different that doesn't make sense.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Mon, 8 May 2023 18:16:32 +0000 (14:16 -0400)]
Prepare v2023.07-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 8 May 2023 17:43:35 +0000 (13:43 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Judith Mendez [Thu, 6 Apr 2023 06:19:01 +0000 (11:49 +0530)]
board: ti: am64x: Add support for AM64B SK
The AM64x SR2.0 SK board uses "AM64B-SKEVM" as the EEPROM identifier.
This board is similar to the AM64x SKEVM except that it has a new
PMIC that will be enabled in the future and consequently could use a
different device tree file in the future.
For now we treat the board same as an AM64x SK.
Signed-off-by: Judith Mendez <jm@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nikhil M Jain [Mon, 10 Apr 2023 08:49:13 +0000 (14:19 +0530)]
common: spl: spl: Remove video driver before u-boot proper
Add method to remove video driver before loading u-boot proper. When
bootstage changes from SPL to u-boot proper, noo method is called to
remove video driver, and at u-boot proper if video driver is not
enabled, the video driver starts displaying garbage on the screen,
because there is no reserved space for video and the frame buffer gets
u-boot proper data written.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Nikhil M Jain [Mon, 10 Apr 2023 08:49:12 +0000 (14:19 +0530)]
board: ti: am62x: evm: Add necessary functions to call splash screen
To enable splash screen on AM62x at a53 SPL setup DRAM, set page table,
enable cache to allow copying of bmp image to frame buffer and display
it using splash_display.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Nikhil M Jain [Mon, 10 Apr 2023 08:49:11 +0000 (14:19 +0530)]
board: ti: am62x: am62x: Change splashimage and splashsource
Change splashimage which is bmp image loadaddr to 0x80200000 since stack
is situated at 0x80477660 as splash framework requires bmp image to be
present above stack.
Change splashsource to sf to support loading bmp image from ospi flash
memory.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Nikhil M Jain [Mon, 10 Apr 2023 08:49:10 +0000 (14:19 +0530)]
configs: am62x_evm_a53_defconfig: Changes in memory to support SPL splash screen
To enable splash at A53 SPL, need to do memory map changes which
involves locate stack above malloc and have enough space to load bmp
image above stack. To load a 1920X1200 image a minimum of 8.8MB space is
needed, to support it move malloc down to 0x80b80000 from 0x80480000 and
bss to 0x80c80000 to have 1MB buffer between malloc and BSS.
Observed SPL size 195KB, CONFIG_SPL_SIZE_LIMIT set to 256KB.
Observed stack size 1904Bytes, CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK set
to 2KB.
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE config sets stack above the malloc
and reports for stack overflow.
Memory map at A53 SPL before splash screen
0x80000000+---------------------+
| Empty 512 KB |
| |
0x80080000+---------------------+
| Text Base |
| 352 KB |
| |
0x800D8000+---------------------+
| |
| |
| Empty 3.6MB |
| |
| |
0x80477660+---------------------+
| Stack 2 KB |
0x80477e60+---------------------+
| GD 416 Bytes |
0x80478000+---------------------+
| Malloc 352 KB |
| |
0x80480000+---------------------+
| |
| |
| |
| |
| Empty 5.5 MB |
| |
| |
| |
| |
0x80a00000+---------------------+
| |
| BSS 512 KB |
| |
0x80a80000+---------------------+
| |
| |
| |
| |
| Empty 5.5 MB |
| |
| |
| |
| |
0x81000000+---------------------+FIT Image load address
New memory map with splash screen at SPL
0x80000000+---------------------+
| Empty 512 KB |
| |
0x80080000+---------------------+
| Text Base |
| 352 KB |
| |
0x800D8000+---------------------+
| Empty 1.1MB |
| |
0x80200000+---------------------+
| |
| |
| |
| BMP Image Load |
| |
| 9.4 MB |
| |
| |
| |
| |
| |
| |
0x80b77660+---------------------+
| Stack 2KB |
0x80b77e60+---------------------+
| GD 416 Bytes |
0x80b78000+---------------------+
| |
| Malloc 352KB |
0x80b80000+---------------------+
| |
| Empty 1 MB |
| |
0x80c80000+---------------------+
| BSS 512 KB |
| |
0x80d00000+---------------------+
| |
| |
| Empty 3.0 MB |
| |
| |
| |
0x81000000+---------------------+FIT Image load addressi
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Dominique Martinet [Tue, 18 Apr 2023 06:41:55 +0000 (15:41 +0900)]
btrfs: fix offset when reading compressed extents
btrfs_read_extent_reg correctly computed the extent offset in the
BTRFS_COMPRESS_NONE case, but did not account for the 'offset - key.offset'
part correctly in the compressed case, making the function read
incorrect data.
In the case I examined, the last 4k of a file was corrupted and
contained data from a few blocks prior, e.g. reading a 10k file with a
single extent:
btrfs_file_read()
-> btrfs_read_extent_reg
(aligned part loop, until 8k)
-> read_and_truncate_page
-> btrfs_read_extent_reg
(re-reads the last extent from 8k to the end,
incorrectly reading the first 2k of data)
This can be reproduced as follow:
$ truncate -s 200M btr
$ mount btr -o compress /mnt
$ pat() { dd if=/dev/zero bs=1M count=$1 iflag=count_bytes status=none | tr '\0' "\\$2"; }
$ { pat 4K 1; pat 4K 2; pat 2K 3; } > /mnt/file
$ sync
$ filefrag -v /mnt/file
File size of /mnt/file is 10240 (3 blocks of 4096 bytes)
ext: logical_offset: physical_offset: length: expected: flags:
0: 0.. 2: 3328.. 3330: 3: last,encoded,eof
$ umount /mnt
Then in u-boot:
=> load scsi 0 2000000 file
10240 bytes read in 3 ms (3.3 MiB/s)
=> md 2001ff0
02001ff0:
02020202 02020202 02020202 02020202 ................
02002000:
01010101 01010101 01010101 01010101 ................
02002010:
01010101 01010101 01010101 01010101 ................
(
02002000 onwards should contain '03' pattern but went back to 01,
start of the extent)
After patch, data is read properly:
=> md 2001ff0
02001ff0:
02020202 02020202 02020202 02020202 ................
02002000:
03030303 03030303 03030303 03030303 ................
02002010:
03030303 03030303 03030303 03030303 ................
Note that the code previously (before commit
e3427184f38a ("fs: btrfs:
Implement btrfs_file_read()")) did not split that read in two, so
this is a regression even if the previous code might not have been
handling offsets correctly either (something that booted now fails to
boot)
Fixes:
a26a6bedafcf ("fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()")
Signed-off-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Reviewed-by: Qu Wenruo <wqu@suse.com>
Tom Rini [Mon, 8 May 2023 13:10:39 +0000 (09:10 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- cmd: tlv_eeprom: Misc cleanups & improvements (Josua)
Josua Mayer [Fri, 5 May 2023 08:20:49 +0000 (11:20 +0300)]
cmd: tlv_eeprom: enable 'dev' subcommand before 'read'
Move the handler for "tlv_eeprom dev X" command to the beginning of
do_tlv_eeprom, to allow using it before issuing a "read" command for
currently selected eeprom.
Also remove the check if eeprom exists, since that can only work after
the first execution of read_eeprom triggered device lookup.
Instead accept values up to the defined array size (MAX_TLV_DEVICES).
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Josua Mayer [Fri, 5 May 2023 08:20:48 +0000 (11:20 +0300)]
cmd: tlv_eeprom: handle -ENODEV error from read_eeprom function
When tlv eeprom does not exist, return error code instead of quietly
making up tlv structure in memory.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Josua Mayer [Fri, 5 May 2023 08:20:47 +0000 (11:20 +0300)]
cmd: tlv_eeprom: remove use of global variable has_been_read
has_been_read is only used as an optimization for do_tlv_eeprom.
Explicitly use and set inside this function, thus making read_eeprom
stateless.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Josua Mayer [Fri, 5 May 2023 08:20:46 +0000 (11:20 +0300)]
cmd: tlv_eeprom: remove use of global variable current_dev
Make tlv_eeprom command device selection an explicit parameter of all
function calls.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Sun, 7 May 2023 13:44:27 +0000 (09:44 -0400)]
Merge branch 'for-2023.07-2' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
This pull request adds misc fixes for cssi boards and activates
CPM relocation in order to enable the use of SCC4 in
QMC (QUICC Multi-Channel) mode.
Tom Rini [Sat, 6 May 2023 14:34:34 +0000 (10:34 -0400)]
Merge branch '2023-05-05-networking-updates'
- Cleanup NFS support, add NFSv1 support, assorted IPv6 improvements,
PHY cleanups and improvements, ksz9477, ldpaa and rtl8169
improvements, overall network performance improvements.
Chris Morgan [Fri, 21 Apr 2023 15:59:19 +0000 (10:59 -0500)]
board: rockchip: add Anbernic RGXX3 Series Devices
The Anbernic RGxx3 is a "pseudo-device" that encompasses the following
devices:
- Anbernic RG353M
- Anbernic RG353P
- Anbernic RG353V
- Anbernic RG353VS
- Anbernic RG503
The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.
Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.
The common specifications for each device are:
- Rockchip RK3566 SoC
- 2 external SDMMC slots
- 1 USB-C host port, 1 USB-C peripheral port
- 1 mini-HDMI output
- MIPI-DSI based display panel
- ADC controlled joysticks with a GPIO mux
- GPIO buttons
- A PWM controlled vibrator
- An ADC controlled button
All of the common features are defined in the devicetree synced from
upstream Linux.
TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Christian Kohlschütter [Tue, 27 Sep 2022 15:05:21 +0000 (15:05 +0000)]
rk3399: r4s: Derive local MAC address if EEPROM is missing
Some RK3399 boards, such as newer revisions of NanoPi R4S, do not
provide an EEPROM chip containing a globally unique MAC address.
Currently, this means that a randomly generated temporary MAC address
may be generated each time the device is rebooted, leading to ARP cache
issues and other confusing bugs.
Since RK3399 CPUs provide a built-in unique serial number, we can
reliably derive a locally MAC address from it by reading the
corresponding bits from the non-secure efuse block.
Enable configuration options that allow deriving a local MAC address
from the CPU serial number.
Johan Jonker [Mon, 13 Mar 2023 00:33:23 +0000 (01:33 +0100)]
include: fdtdec: decouple fdt_addr_t and phys_addr_t size
The DT specification supports CPUs with both 32-bit and 64-bit addressing
capabilities. In U-boot the fdt_addr_t and phys_addr_t size are coupled
by a typedef. The MTD NAND drivers for 32-bit CPU's can describe partitions
with a 64-bit reg property. These partitions synced from Linux end up with
the wrong offset and sizes when only the lower 32-bit is passed.
Decouple the fdt_addr_t and phys_addr_t size as they don't necessary
match.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Mon, 13 Mar 2023 00:33:09 +0000 (01:33 +0100)]
arm: stm32mp: spl: fix function with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:32:57 +0000 (01:32 +0100)]
drivers: fix debug string with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:32:44 +0000 (01:32 +0100)]
drivers: use devfdt_get_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:32:31 +0000 (01:32 +0100)]
drivers: use devfdt_get_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:32:18 +0000 (01:32 +0100)]
drivers: use devfdt_get_addr_size_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:32:04 +0000 (01:32 +0100)]
drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:31:49 +0000 (01:31 +0100)]
drivers: use dev_read_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:31:36 +0000 (01:31 +0100)]
spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes. As we are there also streamline the error
response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Johan Jonker [Mon, 13 Mar 2023 00:31:25 +0000 (01:31 +0100)]
core: read: add dev_read_addr_index_ptr function
Add dev_read_addr_index_ptr function with the
same functionality as dev_read_addr_index,
but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Make same fix for dev_read_addr_ptr() function.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Fri, 21 Apr 2023 15:33:58 +0000 (17:33 +0200)]
core: fdtaddr: add devfdt_get_addr_size_index_ptr function
Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.
Suggested-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:30:57 +0000 (01:30 +0100)]
rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
The Rockchip SoC rk3288 has 2 types of device trees floating around.
A 64bit reg size when synced from Linux and a 32bit for U-boot.
A pre-probe function in the syscon class driver assumes only 32bit.
For other odd reg structures the regmap must be defined in the individual
syscon driver. Store rk3288 platdata in a regmap before pre-probe
during bind.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:30:46 +0000 (01:30 +0100)]
core: remap: fix regmap_init_mem_plat() reg size handeling
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:30:33 +0000 (01:30 +0100)]
include: dm: ofnode: fix headers
When fdt_addr_t and phys_addr_t are split it turns out that
the header don't match the functions, so fix the headers.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Mon, 13 Mar 2023 00:30:20 +0000 (01:30 +0100)]
rockchip: spi: rk_spi: use base variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_spi.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:30:02 +0000 (01:30 +0100)]
rockchip: pwm: rk_pwm: use base variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_pwm.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:29:47 +0000 (01:29 +0100)]
rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Mon, 13 Mar 2023 00:29:35 +0000 (01:29 +0100)]
rockchip: adc: rockchip-saradc: use dev_read_addr_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Mon, 13 Mar 2023 00:29:19 +0000 (01:29 +0100)]
mtd: nand: add support for the Sandisk SDTNQGAMA chip
Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Johan Jonker [Mon, 13 Mar 2023 00:29:05 +0000 (01:29 +0100)]
mtd: nand: raw: rockchip_nfc: fix oobfree offset and description
The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4 positions before
ECC. Update the description for U-boot.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Mon, 13 Mar 2023 00:28:53 +0000 (01:28 +0100)]
mtd: nand: raw: rockchip_nfc: add flash_node to chip structure
Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Johan Jonker [Mon, 13 Mar 2023 00:28:39 +0000 (01:28 +0100)]
mtd: nand: raw: rockchip_nfc: add layout structure
The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Johan Jonker [Mon, 13 Mar 2023 00:28:19 +0000 (01:28 +0100)]
mtd: nand: raw: rockchip_nfc: remove the compatible string "rockchip,rk3308-nfc"
The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Johan Jonker [Mon, 13 Mar 2023 00:28:06 +0000 (01:28 +0100)]
mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Stefan Herbrechtsmeier [Tue, 2 May 2023 12:50:43 +0000 (14:50 +0200)]
net: phy: Request rgmii-id phy reset gpio as output
Request the reset gpio of the rgmii-id phy as output to be consistent
with the eth-phy-uclass driver.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Eugen Hristev [Tue, 25 Apr 2023 13:06:58 +0000 (16:06 +0300)]
net: rtl8169: add minimal support for 8125B variant
Add minimal support for 8125B version.
Changes are based on the Linux driver.
Tested on Radxa Rock 5B Rk3588 board.
Connection to a laptop worked fine in 100 Mbps mode.
1000 Mbps mode is not working at the moment.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ehsan Mohandesi [Sat, 22 Apr 2023 00:08:23 +0000 (17:08 -0700)]
test: eth: IPv6 network discovery unit test
Test router advertisement validation and processing functions.
Signed-off-by: Ehsan Mohandesi <emohandesi@linux.microsoft.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Ehsan Mohandesi [Sat, 22 Apr 2023 00:08:22 +0000 (17:08 -0700)]
test/py: IPv6 network discovery test
Test the IPv6 network discovery feature if indicated by boardenv file.
Signed-off-by: Ehsan Mohandesi <emohandesi@linux.microsoft.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Ehsan Mohandesi [Sat, 22 Apr 2023 00:08:21 +0000 (17:08 -0700)]
net: ipv6: Add support for default gateway discovery.
In IPv6, the default gateway and prefix length are determined by receiving
a router advertisement as defined in -
https://www.rfc-editor.org/rfc/rfc4861.
Add support for sending router solicitation (RS) and processing router
advertisements (RA).
If the RA has prefix info option and following conditions are met, then
gatewayip6 and net_prefix_length of ip6addr env variables are initialized.
These are later consumed by IPv6 code for non-local destination IP.
- "Router Lifetime" != 0
- Prefix is NOT link-local prefix (0xfe80::/10)
- L flag is 1
- "Valid Lifetime" != 0
Timing Parameters:
- MAX_RTR_SOLICITATION_DELAY (0-1s)
- RTR_SOLICITATION_INTERVAL (4s) (min retransmit delay)
- MAX_RTR_SOLICITATIONS (3 RS transmissions)
The functionality is enabled by CONFIG_IPV6_ROUTER_DISCOVERY and invoked
automatically from net_init_loop().
Signed-off-by: Ehsan Mohandesi <emohandesi@linux.microsoft.com>
Tested-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>Reviewed-by:
Tested-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Tested-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Sergei Antonov <saproj@gmail.com>
Nishanth Menon [Fri, 14 Apr 2023 22:06:45 +0000 (17:06 -0500)]
net: phy: Make phy_interface_is_rgmii a switch statement
Recent commit
75d28899e3e9 ("net: phy: Synchronize PHY interface modes
with Linux") reordered the enum definitions. This exposed a problem
in range checking functions to identify the interface type. Though
this specific api wasn't impacted (all the RGMII definitions remained
within range), this experience should be used to never to have to face
this kind of challenge again.
While it is possible for the phy drivers to use the enums directly,
drivers such as dp83867, dp83869, marvell, micrel_ksz90x1 etc use this
api.
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Nishanth Menon [Fri, 14 Apr 2023 22:06:44 +0000 (17:06 -0500)]
net: phy: Drop phy_interface_is_sgmii
Recent commit
75d28899e3e9 ("net: phy: Synchronize PHY interface modes
with Linux") reordered the enum definitions. This caused the range of
enums that this api was checking to go bad.
There aren't anymore users of phy_interface_is_sgmii, so, just drop
it. Also the protocols are so very different that it makes no sense to
provide a helper wrapper in the hope of reuse for phy drivers.
Reported-by: Tom Rini <trini@konsulko.com>
Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Suggested-by: Marek Behún <kabel@kernel.org>
Link: https://lore.kernel.org/all/20230414103852.38705065@dellmb/
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>