compiler/types: Spell struct and enum in type names

This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>

compiler/types: Use C compatible cast syntax

This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>

compiler/types: Remove use of auto

This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>

compiler/types: Remove use of references

This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>

compiler/types: Remove use of new/delete

This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>

compiler/types: Remove private related declarations

Now there's no private data in glsl_type anymore, so we can remove
the friend declaration and move the private functions into file local
statics.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>

rusticl/mesa: create COMPUTE_ONLY contexts

This allows drivers to skip initializing unnecessary bits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25466>

anv: Enable barrier handling on video engines

v1: (Lionel)
- Don't check for the layout transition

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9776

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25131>

ac/llvm: replace removed amdgcn.ldexp for LLVM 18

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25393>

ci/etnaviv: Drop some gc2k flakes that I think are resolved.

All these basic GLSL tests should be stable now that other processes
aren't hanging the GPU on us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25442>

ci/etnaviv: Skip some tests that hang the GPU and knock out other tests.

Just a few tests were causing GPU hangs that seem to cause spurious
failures in other tests.  With those skipped, the results mostly
stabilize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25442>

radeonsi: fix compute-only contexts

We can't skip redundant register updates on compute queues, at least
not all of them.

Fixes: 315231b5a519bdc14 - radeonsi: eliminate redundant compute SH register changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25390>

nvk: Init pipelineCacheUUID

Fixes: 968cefbff113 ("nvk: Cache NIR shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25458>

radv/ci: add a manual job for vkd3d-proton on navi31

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25266>

radv/ci: add a manual job to run vkcts on navi31

We currently only have a single navi31, but we'll get more in the
next month or so.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25266>

radv/ci: update the vkcts gfx1100 flake/fail lists

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25266>

glsl: remove now unused varying linker code

All of this varying linking code has now been ported to the NIR linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

glsl: switch to nir linkers cross_validate_outputs_to_inputs()

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

glsl: implement cross_validate_outputs_to_inputs() in nir linker

This is mostly a direct port of the GLSL IR code there are only
2 real functional changes.

1. The direct use of mesa symbol_table instead of glsl_symbol_table.
   However since none of the extra functionality offered by
   glsl_symbol_table was ever used here this can be seen as an
   improvement.

2. Because interface blocks are lowered before this new nir linker
   sees them we must explicitly skip them (they are validated
   elsewhere) to avoid errors.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

nir: add used field to nir variables

Will be use in a following path by the glsl nir based linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

glsl: move is_gl_identifier() to linker_util

This had started to multiply around the NIR linker. Here we move it to a
common helper shared by GLSL IR and NIR.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

glsl: move interpolation_string() to linker_util

Moving it here allows us to use in in the NIR linker too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

nir: copy explicit_invariant flag to nir vars

This will be used in the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>

radv: stop skip emitting CB states when there is no color attachment

This is actually wrong. For example, if there is a DCC decompress
draw followed by a draw without any color attachments,
CB_COLOR_CONTROL.MODE is still CB_DCC_DECOMPRESS but it should be
CB_DISABLED. For some reasons, this hangs on RDNA3 (VM faults are also
reported through dmesg).

This fixes GPU hangs with Resident Evil 6, Star Wars The Old Republic
and probably more games on RDNA3.

Strictly speaking, I don't think this dynamic state optimization is
worth a try, even for other states, and I think it would be safer to
remove it completely.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9335
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8327
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9878
Fixes: c08082e8615 ("radv: ignore all CB dynamic states when there is no color attachments")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25402>

glx: XFree visual info

cc: mesa-stable

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25441>

r300:  Fix out-of-bounds access in ntr_emit_store_output()

This patch resolves the problem by modifying the for loop condition
to ensure that it stays within the bounds of the array (i.e., i < 4)

Signed-off-by: Cong Liu <liucong2@kylinos.cn>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25419>

ci/zink+radv: document flake

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25427>

isaspec: python does not need ';'

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25437>

spirv: Track when a shader has a cooperative matrix

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

spirv: Implement SPV_KHR_cooperative_matrix

Includes a modified version of using extract/insert for OpLoad/OpStore
from Ian.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (earlier version)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (earlier version)
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

spirv: Let vtn_ssa_value hold references to variables

In certain cases, we have complex opaque objects that are loaded
into (SPIR-V) SSA values.  To represent these, we now can store a
reference to a variable in vtn_ssa_value.

Also implements a few operations we know will have to be supported,
like Select and Copy.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

spirv: Expose some memory related functions in vtn_private.h

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

nir: Handle cooperative matrix in various passes

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

nir: Add new intrinsics for Cooperative Matrix

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

compiler/types: Add support for Cooperative Matrix types

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>

anv: enable sparse resources by default

This of course only applies to xe.ko. There is no reason to keep it
disabled by default.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>

anv/sparse: add INTEL_DEBUG=sparse

This pollutes stderr a lot, but I've used it countless times while
developing this code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>

anv/sparse: get ready to issue a single vm_bind ioctl per non-opaque bind

Game testing shows it's common for this operation to result in
multiple bind regions, so try to use a single ioctl when we can.

Actual testing reveals 136 shader-related tests fail when we actually
do this, so for now keep doing a single bind per ioctl while leaving a
very easy way to the desired behavior when we figure this out.

It should also be possible to go even higher-level and do this at the
anv_queue_submit_sparse_bind_locked() layer, but that should happen in
future commits.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>

anv/sparse: add the initial code for Sparse Resources

This giant patch implements a huge chunk of the Vulkan Sparse
Resources API. I previously had this as a nice series of many smaller
patches that evolved as the xe.ko added more features, but once I was
asked to squash some of the major reworks I realized I wouldn't be
able easily rewrite history, so I just squased basically the whole
series into a giant patch. I may end up splitting this again later if
I find a way to properly do it.

If we want to support the DX12 API through vkd3d we need to support
part of the the Sparse Resources API. If we don't, a bunch of Steam
games won't work.

For now we only support the xe.ko backend, but the vast majority of
the code is KMD-independent and so an i915.ko implementation would use
most of what's here, just extending the part that binds and unbinds
memory.

v2+: There's no way to sanely track the version history of this patch
in this commit message. Please refer to Gitlab.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>

intel/isl: simplify the check for maximum surface size

The only thing that changes between these 3 checks is the size.

This entire patch was suggested by Kenneth Graunke, I just converted
his gitlab comment to a git commit.

Credits-to: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>

intel/isl: add ISL_SURF_USAGE_SPARSE_BIT

Vulkan Sparse resources have their own set of rules, so here we try to
make ISL aware of them through ISL_SURF_USAGE_SPARSE_BIT.

The big deal here is when some image ends up not using Tile64 nor
TileYs. Previously Ys was not supported on TGL at all, and Tile64 did
not have support for 3D. Now we still have some formats that end up
not being used with either Tile64 and Ys, but need to support Sparse
on them (e.g., YUV on Tile64). In the future we may have new tiling
formats or hardware restrictions that would force this case to happen
again.

So here we do some adjustments so we can make sparse work with other
tiling formats, although with limited functionality (e.g., those
formats may be restricted to opaque binds, and certainly don't support
the standard block shapes).

v2: before we had Ys support, we had defined TGL's block size as 4k.
v3: move the size_B chunk to before nte notify_failure() checks (Ken).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>

nvk: Cache NIR shaders

We can't cache shader binaries just yet but this at least lets us cache
the output of spirv_to_nir and the initial optimize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>

nvk: Add a default pipeline cache

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>

nvk: Re-structure early shader compilation a bit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>

nvk: Hook up the disk cache

This won't actually do much yet because we don't have pipeline caches
yet but it turns on the infrastructure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>

nvk: Store a 20-bit driver_build_sha in nvk_instance

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>

nir: fix typo in comment

The variable is unused or dead, not used.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25414>

vulkan: Handle vkSetDebugUtilsObjectNameEXT on WSI objects

Some WSI objects don't extend `vk_object_base` therefore they need
special handling.

Fixes: 3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>

vulkan: Extend vkGet/SetPrivateDataEXT handling to VkSurface

VkSurface is handled by WSI and it doesn't extend `vk_object_base` so it
needs special handling.

Fixes: 3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>

vulkan: Extend vkGet/SetPrivateDataEXT handling to all platforms

Non-android platforms use mesa WSI, however some WSI object still don't
extend `vk_object_base` so they still need special handling.

Fixes: 3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>

llvmpipe/cs: migrate cs image handle to common jit code.

This moves some of the code over, and uses the generic paths.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>

llvmpipe/cs: migrate to generic jit texture from pipe code.

This moves some cs specific bits to the generic code and uses it.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>

intel/compiler: mask GS URB handles at thread payload construction

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/mesh: implement IO for xe2

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/mesh: fix position of output URB handle for xe2

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB reads.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB writes.

Rework:
 * Marcin: update emit_urb_indirect_vec4_write

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/fs: Specify number of data components of logical URB writes via control immediate.

This is what most logical SEND messages do when they take a variable
number of components.  'inst->mlen' is expected to be zero for logical
SEND opcodes, which are expected to behave like plain arithmetic
operations, so certain automated transformations (like SIMD lowering)
can manipulate them without opcode-specific special-casing.

Guessing the number of components from 'inst->mlen' has other
disadvantages, because it requires duplicating the logic that infers
the message payload size in every use of the instruction -- Instead we
can just do the computation once during logical send lowering.  In
addition on LNL platform this causes the 'inst->mlen' field of URB
writes to have units inconsistent with every other SEND instruction,
which is likely to lead to confusion and bugs down the road.

Rework:
 * Marcin: update emit_urb_indirect_vec4_write

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/fs/xe2+: Fix URB writes with 0 data components.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/xe2: Update TCS ICP handle code to support SIMD16

Rework:
 * Use ffs(grf_size_bytes) (s-b Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/xe2: Fix URB writes in TCS

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/xe2: URB fence uses LSC now

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8

v2: Account for 512b physical registers which causes the URB handle to be in FIXED_GFR 2 instead of 1.

XXX - Use fs_builder::vgrf() instead of open-coded dispatch_width calculations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/fs: Fix Xe2 URB read/lowering with per-slot offsets

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler: Use enum xe2_lsc_cache_load on xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler: Add enum xe2_lsc_cache_load

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler: Use enum xe2_lsc_cache_store on xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler: Add enum xe2_lsc_cache_store

Rework:
 * Rohan: Fix enum value for L1WB_L3WB
 * Fix write-through comments (Ken)

Ref: bspec 71167
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler: add initial support for URB_LOGICAL_SRC_CHANNEL_MASK to lower_urb_write_logical_send_xe2

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler: add lsc_msg_desc_wcmask

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/xe2: Handle new URB write messages

Rework:
 * idr v1: Fix compilation error.
 * idr v2: Add support for per-channel offsets.
 * idr v3: get_lowered_simd_width is 16 on Xe2+.
 * idr v4: Add disassembly support.  Add validation support.
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

intel/compiler/xe2: Handle new URB read messages

Rework:
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>

vulkan: Remove vk_get_physical_device_core_1_*_feature_ext

It's unused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>

hasvk: Use the common GetPhysicalDeviceFeatures2 implementation

Reviewed-by: Julia Tatz <tatz.j@northeastern.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>

nir/algebraic: optimize u2u32(a >> 32)

fossil-db (navi21):
Totals from 352 (0.44% of 79330) affected shaders:
Instrs: 271816 -> 271240 (-0.21%); split: -0.28%, +0.07%
CodeSize: 1546520 -> 1544448 (-0.13%); split: -0.23%, +0.09%
SpillVGPRs: 832 -> 827 (-0.60%); split: -1.08%, +0.48%
Latency: 4037120 -> 4021748 (-0.38%); split: -0.41%, +0.03%
InvThroughput: 1369540 -> 1362066 (-0.55%); split: -0.59%, +0.04%
VClause: 6476 -> 6471 (-0.08%); split: -0.12%, +0.05%
SClause: 6798 -> 6794 (-0.06%)
Copies: 44828 -> 44630 (-0.44%); split: -0.89%, +0.45%
Branches: 8845 -> 8844 (-0.01%); split: -0.05%, +0.03%
PreSGPRs: 14684 -> 14659 (-0.17%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>

nir/lower_int64: fix find_lsb(0)

If the high 32 bits were zero, this would be umin(find_lsb(lo), 31). This
evaluates to 31 if lo is also zero, instead of -1.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 9293d8e64bc7 ("nir: Add find_lsb lowering to nir_lower_int64.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>

tu/kgsl: Fix bitfield of DITHER_MODE_MRT6

The enum `adreno_rb_dither_mode` needs 2 bits, change the `high` to 13 to make sure 2 bits are used for `DITHER_MODE_MRT6`

Fixes: e03259974e2f2c8e8c0295f8dab56d88e7bd896c ("freedreno: Generate headers from xml files")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25439>

anv: Print warning that Xe2 is not supported rather than failing

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>

anv: Build for Xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>

anv: Disable Ray Tracing on xe2 until our compiler supports Xe2 RT

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>

anv/blorp: Use anv_genX to set device->blorp.exec

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>

iris: Build for Xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>

iris: add missing workaround for 3DSTATE_LINE_STIPPLE

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>

anv: add missing workaround for 3DSTATE_LINE_STIPPLE

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>

anv/iris: widen Wa_14015946265 to Gfx11+

We missed out that ICL+ added a programming requiring a CS_STALL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25426>

tu: Expose VK_KHR_maintenance5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

freedreno/ci: Skip dEQP-VK.info.device_extensions

Copied from anv and radv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Add maintenance5 properties

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Check for DEVICE_LOST in vkGetEventStatus()

Required by maintenance5.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Support VkPipelineCreateFlags2CreateInfoKHR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Use new buffer usage flags

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Implement vkGetRenderingAreaGranularityKHR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Implement vkGetImageSubresourceLayout2KHR and vkGetDeviceImageSubresourceLayoutKHR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Implement vkCmdBindIndexBuffer2KHR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Allow VK_WHOLE_SIZE in tu_CmdBindVertexBuffers2EXT pSizes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu/clear_blit: Allow VK_REMAINING_ARRAY_LAYERS as layerCount

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu/clear_blit: Fix staging image view layer count

This seems to be a mistake that didn't affect anything.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

freedreno/fdl: Support PIPE_FORMAT_R5G5B5A1_UNORM on a6xx

This is just a different swap of the same format.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

tu: Support clearing A8_UNORM

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>

freedreno/fdl: Use A8_UNORM HW format for sampling

We've already been using this for 3d blits on turnip and it works fine.
There's no need to emulate it, and it won't work on turnip where we
can't swizzle the border colors.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>