Calixte Denizet [Tue, 25 Sep 2018 11:12:15 +0000 (11:12 +0000)]
[Profile] Fix gcov tests
Summary: The gcda need to be delete before running the binary to avoid to have an increasing "# of Runs" when a test is failing
Reviewers: vitalybuka, eugenis, marco-c
Reviewed By: marco-c
Subscribers: delcypher, llvm-commits, #sanitizers, sylvestre.ledru, marco-c
Differential Revision: https://reviews.llvm.org/D52456
llvm-svn: 342963
Martin Storsjo [Tue, 25 Sep 2018 10:59:29 +0000 (10:59 +0000)]
[COFF] Add support for creating range extension thunks for ARM
This is a feature that MS link.exe lacks; it currently errors out on
such relocations, just like lld did before.
This allows linking clang.exe for ARM - practically, any image over
16 MB will likely run into the issue.
Differential Revision: https://reviews.llvm.org/D52156
llvm-svn: 342962
Eric Liu [Tue, 25 Sep 2018 10:47:46 +0000 (10:47 +0000)]
[clangd] Check that scheme is valid when parsing URI.
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Differential Revision: https://reviews.llvm.org/D52455
llvm-svn: 342961
Sylvestre Ledru [Tue, 25 Sep 2018 10:36:57 +0000 (10:36 +0000)]
Fix a typo in the help of clangd
llvm-svn: 342960
Tatyana Krasnukha [Tue, 25 Sep 2018 10:30:32 +0000 (10:30 +0000)]
[Swig] Merge typemaps with same bodies
Differential Revision: https://reviews.llvm.org/D52376
llvm-svn: 342959
David Green [Tue, 25 Sep 2018 10:08:47 +0000 (10:08 +0000)]
[LoopUnroll] Add check to Latch's terminator in UnrollRuntimeLoopRemainder
In this patch, I'm adding an extra check to the Latch's terminator in llvm::UnrollRuntimeLoopRemainder,
similar to how it is already done in the llvm::UnrollLoop.
The compiler would crash if this function is called with a malformed loop.
Patch by Rodrigo Caetano Rocha!
Differential Revision: https://reviews.llvm.org/D51486
llvm-svn: 342958
Kirill Bobyrev [Tue, 25 Sep 2018 09:47:01 +0000 (09:47 +0000)]
[clangd] NFC: Remove test duplicate
`FuzzyMatchQ` test was a duplicate of `FuzzyMatch` pulled from MemIndex
tests.
llvm-svn: 342957
Sameer Sahasrabuddhe [Tue, 25 Sep 2018 09:39:21 +0000 (09:39 +0000)]
[AMDGPU] restore r342722 which was reverted with r342743
[AMDGPU] lower-switch in preISel as a workaround for legacy DA
Summary:
The default target of the switch instruction may sometimes be an
"unreachable" block, when it is guaranteed that one of the cases is
always taken. The dominator tree concludes that such a switch
instruction does not have an immediate post dominator. This confuses
divergence analysis, which is unable to propagate sync dependence to
the targets of the switch instruction.
As a workaround, the AMDGPU target now invokes lower-switch as a
preISel pass. LowerSwitch is designed to handle the unreachable
default target correctly, allowing the divergence analysis to locate
the correct immediate dominator of the now-lowered switch.
llvm-svn: 342956
Clement Courbet [Tue, 25 Sep 2018 09:36:44 +0000 (09:36 +0000)]
Revert rL342953 "[llvm-exegesis] Add lit tests."
We also need to make sure that we're on the right subtarget.
llvm-svn: 342955
George Rimar [Tue, 25 Sep 2018 09:32:31 +0000 (09:32 +0000)]
[ELF] - Add -z global option to manual.
This was requested during review of D49374,
but for some unknown reason was not in the final commit.
llvm-svn: 342954
Clement Courbet [Tue, 25 Sep 2018 09:27:43 +0000 (09:27 +0000)]
[llvm-exegesis] Add lit tests.
Summary:
Right now we only have unit tests. This will allow testing the whole
tool. Even though We can't really check actual values, this will avoid
regressions such as PR39055.
Reviewers: gchatelet, alexshap
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52407
llvm-svn: 342953
Heejin Ahn [Tue, 25 Sep 2018 08:25:29 +0000 (08:25 +0000)]
[llvm-exegesis] Add MCParser to LLVM_LINK_COMPONENTS
We need this to make builds with `-DBUILD_SHARED_LIBS=ON` work.
llvm-svn: 342952
Eric Liu [Tue, 25 Sep 2018 08:24:07 +0000 (08:24 +0000)]
Deduplicate replacements from diagnostics.
Summary:
After r329813, clang-apply-replacements stopped deduplicating identical
replacements; however, tools like clang-tidy relies on the deduplication of
identical dignostics replacements from different TUs to apply fixes correctly.
This change partially roll back the behavior by deduplicating changes from
diagnostics. Ideally, we should deduplicate on diagnostics level, but we need to
figure out an effecient way.
Reviewers: bkramer
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D52264
llvm-svn: 342951
Fangrui Song [Tue, 25 Sep 2018 08:07:42 +0000 (08:07 +0000)]
Annotate LookupResult::clear() as LLVM_ATTRIBUTE_REINITIALIZES to silence bugprone-use-after-move after rC342925
Reviewers: rsmith
Reviewed By: rsmith
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D52446
llvm-svn: 342950
Fangrui Song [Tue, 25 Sep 2018 08:06:32 +0000 (08:06 +0000)]
Add macro LLVM_ATTRIBUTE_REINITIALIZES
Summary:
This marks legitimate use-after-move (e.g. `Found.clear()` in rC342925)
which would otherwise be caught by bugprone-use-after-move.
bugprone-use-after-move recognizes this attribute after rCTE339571.
Reviewers: aaron.ballman, rsmith, mboehme, hokein
Reviewed By: mboehme
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D52451
llvm-svn: 342949
Clement Courbet [Tue, 25 Sep 2018 07:48:38 +0000 (07:48 +0000)]
[llvm-exegesis] Fix doc in r342947.
llvm-exegesis.rst was using invalid indentation for bullet points.
llvm-svn: 342948
Clement Courbet [Tue, 25 Sep 2018 07:31:44 +0000 (07:31 +0000)]
[llvm-exegesis] Allow benchmarking arbitrary code snippets.
Summary:
This is a step towards fixing PR38048.
Note that right now the measurements are given per instruction. We'll
need to give measurements a per code snippet and update the analysis (PR38731).
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52041
llvm-svn: 342947
Stefan Maksimovic [Tue, 25 Sep 2018 06:27:49 +0000 (06:27 +0000)]
[mips] Correct MUL pattern for mips64
Guard existing pattern with a predicate, introduce a new one for revision 6.
Differential Revision: https://reviews.llvm.org/D51684
llvm-svn: 342946
Fangrui Song [Tue, 25 Sep 2018 06:19:31 +0000 (06:19 +0000)]
Use unique_ptr to hold AsmInfo,MRI,MII,STI
Reviewers: pcc, dblaikie
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52389
llvm-svn: 342945
Mikael Holmen [Tue, 25 Sep 2018 06:10:04 +0000 (06:10 +0000)]
Use TRI->regsOverlap() in MachineBasicBlock::computeRegisterLiveness
Summary:
For the loop that used MCRegAliasIterator this should be NFC.
For the loop that previously used MCSubRegIterator we should
now detect more cases where the register is actually live out that
we previously missed.
Reviewers: MatzeB, arsenm
Reviewed By: MatzeB
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D52410
llvm-svn: 342944
Hsiangkai Wang [Tue, 25 Sep 2018 06:09:50 +0000 (06:09 +0000)]
[DebugInfo] Do not generate address info for removed debug labels.
In some senario, LLVM will remove llvm.dbg.labels in IR. For example,
when the labels are in unreachable blocks, these labels will not
be generated in LLVM IR. In the case, these debug labels will have
address zero as their address. It is not legal address for debugger to
set breakpoints or query sources. So, the patch inhibits the address info
(DW_AT_low_pc) of removed labels.
Differential Revision: https://reviews.llvm.org/D51908
llvm-svn: 342943
Justin Bogner [Tue, 25 Sep 2018 05:16:44 +0000 (05:16 +0000)]
[MachineCopyPropagation] Reimplement CopyTracker in terms of register units
Change the copy tracker to keep a single map of register units instead
of 3 maps of registers. This gives a very significant compile time
performance improvement to the pass. I measured a 30-40% decrease in
time spent in MCP on x86 and AArch64 and much more significant
improvements on out of tree targets with more registers.
Differential Revision: https://reviews.llvm.org/D52374
llvm-svn: 342942
Lang Hames [Tue, 25 Sep 2018 04:54:03 +0000 (04:54 +0000)]
Revert "[ORC] Switch to asynchronous resolution in JITSymbolResolver."
This reverts commit r342939.
MSVC's promise/future implementation does not like types that are not default
constructible. Reverting while I figure out a solution.
llvm-svn: 342941
Justin Bogner [Tue, 25 Sep 2018 04:45:25 +0000 (04:45 +0000)]
[MachineCopyPropagation] Rework how we manage RegMask clobbers
Instead of updating the CopyTracker's maps each time we come across a
RegMask, defer checking for this kind of interference until we're
actually trying to propagate a copy. This avoids the need to
repeatedly iterate over maps in the cases where we don't end up doing
any work.
This is a slight compile time improvement for MachineCopyPropagation
as is, but it also enables a much bigger improvement that I'll follow
up with soon.
Differential Revision: https://reviews.llvm.org/D52370
llvm-svn: 342940
Lang Hames [Tue, 25 Sep 2018 04:43:38 +0000 (04:43 +0000)]
[ORC] Switch to asynchronous resolution in JITSymbolResolver.
Asynchronous resolution (where the caller receives a callback once the requested
set of symbols are resolved) is a core part of the new concurrent ORC APIs. This
change extends the asynchronous resolution model down to RuntimeDyld, which is
necessary to prevent deadlocks when compiling/linking on a fixed number of
threads: If RuntimeDyld's linking process were a blocking operation, then any
complete K-graph in a program will require at least K threads to link in the
worst case, as each thread would block waiting for all the others to complete.
Using callbacks instead allows the work to be passed between dependent threads
until it is complete.
For backwards compatibility, all existing RuntimeDyld functions will continue
to operate in blocking mode as before. This change will enable the introduction
of a new async finalization process in a subsequent patch to enable asynchronous
JIT linking.
llvm-svn: 342939
Louis Dionne [Tue, 25 Sep 2018 04:13:08 +0000 (04:13 +0000)]
Revert r342936 "Remove redundant null pointer check in operator delete"
A review for the change was opened in https://reviews.llvm.org/D52401
but the change was committed before being approved by any of the code
owners for libc++.
llvm-svn: 342938
Thomas Lively [Tue, 25 Sep 2018 03:39:28 +0000 (03:39 +0000)]
[WebAssembly] SIMD sqrt
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52387
llvm-svn: 342937
Fangrui Song [Tue, 25 Sep 2018 02:50:57 +0000 (02:50 +0000)]
Remove redundant null pointer check in operator delete
C89 4.10.3.2 The free function
C99 7.20.3.2 The free function
C11 7.22.3.3 The free function
If ptr is a null pointer, no action shall occur.
_aligned_free on MSDN:
If memblock is a NULL pointer, this function simply performs no actions.
Reviewers: EricWF, mclow.lists
Subscribers: christof, ldionne, cfe-commits, libcxx-commits
Differential Revision: https://reviews.llvm.org/D52401
llvm-svn: 342936
Stanislav Mekhanoshin [Tue, 25 Sep 2018 01:24:54 +0000 (01:24 +0000)]
[AMDGPU] Remove useless check from test. NFC.
The check for assignment of zero is practically useless
while the assignment moves around with different scheduling.
llvm-svn: 342935
Craig Topper [Tue, 25 Sep 2018 00:16:57 +0000 (00:16 +0000)]
[X86] Don't create FILD ISD nodes when X87 is disabled.
The included test case previously asserted because the type legalizer tried to soften the FILD ISD node.
Fixes PR38819.
llvm-svn: 342934
Craig Topper [Tue, 25 Sep 2018 00:16:54 +0000 (00:16 +0000)]
[X86] Remove superfluous curly braces. NFC
llvm-svn: 342933
Craig Topper [Tue, 25 Sep 2018 00:16:52 +0000 (00:16 +0000)]
[X86] Update comment. Use 'glued' instead of 'flagged' NFC
llvm-svn: 342932
Yury Delendik [Mon, 24 Sep 2018 23:50:55 +0000 (23:50 +0000)]
[WebAssembly] Move .debug_line section address of dead function outside section range
Summary:
Currently we are pointing all debug information that refer removed function code
to the beginning of the code section (offset = 0). A debugger may want to
resolve code offset to the debug information, which will collide with offsets
of the live functions.
Moving offsets of dead functions outside code section range.
Reviewers: sbc100
Reviewed By: sbc100
Subscribers: dblaikie, ruiu, alexcrichton, dschuff, aprantl, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D49446
llvm-svn: 342930
Saleem Abdulrasool [Mon, 24 Sep 2018 23:50:02 +0000 (23:50 +0000)]
Driver: render arguments for the embedded bitcode correctly
When embedding bitcode, only a subset of the arguments should be recorded into
the bitcode compilation commandline. The frontend job is split into two jobs,
one which will generate the bitcode. Ensure that the arguments for the
compilation to bitcode is properly stripped so that the embedded arguments are
the permitted subset.
llvm-svn: 342929
Thomas Lively [Mon, 24 Sep 2018 23:42:07 +0000 (23:42 +0000)]
[WebAssembly][NFC] Fix hardcoded stack indices in tests
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52388
llvm-svn: 342928
Richard Smith [Mon, 24 Sep 2018 23:21:09 +0000 (23:21 +0000)]
[www] Change 'Clang 7' items from yellow to green now Clang 7 is
released.
llvm-svn: 342927
Richard Smith [Mon, 24 Sep 2018 23:19:11 +0000 (23:19 +0000)]
[www] Update cxx_status to mark P0962R1 as done.
llvm-svn: 342926
Richard Smith [Mon, 24 Sep 2018 23:17:44 +0000 (23:17 +0000)]
P0962R1: only use the member form of 'begin' and 'end' in a range-based
for loop if both members exist.
This resolves a DR whereby an errant 'begin' or 'end' member in a base
class could result in a derived class not being usable as a range with
non-member 'begin' and 'end'.
llvm-svn: 342925
Artem Belevich [Mon, 24 Sep 2018 23:10:44 +0000 (23:10 +0000)]
[CUDA] Added basic support for compiling with CUDA-10.0
llvm-svn: 342924
Evgeniy Stepanov [Mon, 24 Sep 2018 23:03:34 +0000 (23:03 +0000)]
[hwasan] Record and display stack history in stack-based reports.
Summary:
Display a list of recent stack frames (not a stack trace!) when
tag-mismatch is detected on a stack address.
The implementation uses alignment tricks to get both the address of
the history buffer, and the base address of the shadow with a single
8-byte load. See the comment in hwasan_thread_list.h for more
details.
Developed in collaboration with Kostya Serebryany.
Reviewers: kcc
Subscribers: srhines, kubamracek, mgorny, hiraditya, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52249
llvm-svn: 342923
Evgeniy Stepanov [Mon, 24 Sep 2018 22:50:32 +0000 (22:50 +0000)]
Revert "[hwasan] Record and display stack history in stack-based reports."
This reverts commit r342921: test failures on clang-cmake-arm* bots.
llvm-svn: 342922
Evgeniy Stepanov [Mon, 24 Sep 2018 21:38:42 +0000 (21:38 +0000)]
[hwasan] Record and display stack history in stack-based reports.
Summary:
Display a list of recent stack frames (not a stack trace!) when
tag-mismatch is detected on a stack address.
The implementation uses alignment tricks to get both the address of
the history buffer, and the base address of the shadow with a single
8-byte load. See the comment in hwasan_thread_list.h for more
details.
Developed in collaboration with Kostya Serebryany.
Reviewers: kcc
Subscribers: srhines, kubamracek, mgorny, hiraditya, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52249
llvm-svn: 342921
George Karpenkov [Mon, 24 Sep 2018 21:20:30 +0000 (21:20 +0000)]
[analyzer] Prevent crashes in FindLastStoreBRVisitor
This patch is a band-aid. A proper solution would be too change
trackNullOrUndefValue to only try to dereference the pointer when it is
relevant to the problem.
Differential Revision: https://reviews.llvm.org/D52435
llvm-svn: 342920
Christy Lee [Mon, 24 Sep 2018 20:47:12 +0000 (20:47 +0000)]
Re-submitting changes in D51550 because it failed to patch.
Reviewers: javed.absar, trentxintong, courbet
Reviewed By: trentxintong
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52433
llvm-svn: 342919
Sanjay Patel [Mon, 24 Sep 2018 20:41:22 +0000 (20:41 +0000)]
[InstCombine] add bitcast+extelt helper function; NFC
We can handle patterns where the elements have different
sizes, so refactoring ahead of trying to add another blob
within these clauses.
llvm-svn: 342918
Jordan Rupprecht [Mon, 24 Sep 2018 20:39:19 +0000 (20:39 +0000)]
[compiler-rt] [builtins] Add logb/logbf/logbl methods to compiler-rt to avoid libm dependencies when possible.
Summary:
The complex division builtins (div?c3) use logb methods from libm to scale numbers during division and avoid rounding issues. However, these come from libm, meaning anyone that uses --rtlib=compiler-rt also has to include -lm. Implement logb* methods for standard ieee 754 floats so we can avoid -lm on those platforms, falling back to the old behavior (using either logb() or `__builtin_logb()`) when not supported.
These new methods are defined internally as `__compiler_rt_logb` so as not to conflict with the libm definitions in any way.
This fixes just the libm methods mentioned in PR32279 and PR28652. libc is still required, although that seems to not be an issue.
Note: this is proposed as an alternative to just adding -lm: D49330.
Reviewers: efriedma, compnerd, scanon, echristo
Reviewed By: echristo
Subscribers: jsji, echristo, nemanjai, dberris, mgorny, kbarton, delcypher, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D49514
llvm-svn: 342917
Simon Pilgrim [Mon, 24 Sep 2018 20:11:50 +0000 (20:11 +0000)]
[X86] Remove shift/rotate by CL memory (RMW) overrides
The uops are slightly different to the register variant, so requires a +1uop tweak
llvm-svn: 342916
Alexander Polyakov [Mon, 24 Sep 2018 19:10:48 +0000 (19:10 +0000)]
[lldb-mi] Fix hanging of target-select-so-path.test
Summary:
The target-select-so-path test might hang on
some platforms. The reason of that behavior
was in incorrect usage of Filecheck and lldb-mi
processes. Instead of redirecting lldb-mi's output
to Filecheck, we should run lldb-mi session,
finish the session, collect its output and then pass
it to Filecheck.
Also, this patch adds a timer to the test to prevent
it from hanging in the future.
Reviewers: tatyana-krasnukha, aprantl, teemperor
Reviewed By: tatyana-krasnukha, teemperor
Subscribers: apolyakov, aprantl, teemperor, ki.stfu, abidh, lldb-commits
Differential Revision: https://reviews.llvm.org/D52139
llvm-svn: 342915
Craig Topper [Mon, 24 Sep 2018 18:55:41 +0000 (18:55 +0000)]
[X86] Infer 64bit feature support from the CPUID results in getHostCPUFeatures.
After r341022, we more strictly check the 64bit feature in X86Subtargets constructor when a 64-bit triple is used. If we don't infer this feature for autodetected CPUs we might incorrectly report an error if the CPU name wasn't autodetected to a CPU that supports 64-bit.
llvm-svn: 342914
Calixte Denizet [Mon, 24 Sep 2018 18:24:29 +0000 (18:24 +0000)]
[profile] Revert commit https://reviews.llvm.org/rL342718
llvm-svn: 342913
Calixte Denizet [Mon, 24 Sep 2018 18:24:18 +0000 (18:24 +0000)]
[CodeGen] Revert commit https://reviews.llvm.org/rL342717
llvm-svn: 342912
Stefan Pintilie [Mon, 24 Sep 2018 18:14:50 +0000 (18:14 +0000)]
[Power9] [CLANG] Add __float128 exponent GET and SET builtins
Added
__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp
Builtins should behave the same way as in GCC.
Differential Revision: https://reviews.llvm.org/D48184
llvm-svn: 342911
Stefan Pintilie [Mon, 24 Sep 2018 18:14:13 +0000 (18:14 +0000)]
[Power9] [LLVM] Add __float128 exponent GET and SET builtins
Added
__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp
Builtins should behave the same way as in GCC.
Differential Revision: https://reviews.llvm.org/D48185
llvm-svn: 342910
Benjamin Kramer [Mon, 24 Sep 2018 17:51:15 +0000 (17:51 +0000)]
Fix the type of 1<<31 integer constants.
Shifting into the sign bit is technically undefined behavior. No known
compiler exploits it though.
llvm-svn: 342909
Simon Pilgrim [Mon, 24 Sep 2018 17:26:31 +0000 (17:26 +0000)]
[X86][AVX] Add truncation as shuffle test for PR31451
llvm-svn: 342908
Christy Lee [Mon, 24 Sep 2018 17:26:30 +0000 (17:26 +0000)]
Reland r342494 after fixing LIT checks.
llvm-svn: 342907
Sanjay Patel [Mon, 24 Sep 2018 17:18:32 +0000 (17:18 +0000)]
[Analysis] add comment to generalize finding a scalar op from vector; NFC
llvm-svn: 342906
Sanjay Patel [Mon, 24 Sep 2018 17:17:16 +0000 (17:17 +0000)]
[InstCombine] add/move tests for extractelement; NFC
llvm-svn: 342905
Simon Pilgrim [Mon, 24 Sep 2018 16:58:26 +0000 (16:58 +0000)]
[X86] Remove WriteDiv/WriteIDiv schedule overrides - use classes directly. NFCI.
We're missing quite a bit of data for these instruction, removing the overrides makes this obvious - inconsistent reg/mem variants is a concern as well.
Also, we have Divider resources (HWDivider etc.) but they aren't actually used consistently.
llvm-svn: 342904
Sam McCall [Mon, 24 Sep 2018 16:52:48 +0000 (16:52 +0000)]
[clangd] Fix uninit bool in r342888
llvm-svn: 342903
Sanjay Patel [Mon, 24 Sep 2018 16:39:03 +0000 (16:39 +0000)]
[InstCombine] improve variable name and use 'match'; NFC
'width' of a vector usually refers to the bit-width.
https://bugs.llvm.org/show_bug.cgi?id=39016
shows a case where we could extend this fold to handle
a case where the number of elements in the bitcasted
vector is not equal to the resulting value.
llvm-svn: 342902
Luke Cheeseman [Mon, 24 Sep 2018 16:36:33 +0000 (16:36 +0000)]
Reverting r342895
- The used builtins do not compile for pre arm v8.3a targets with gcc
llvm-svn: 342901
Evandro Menezes [Mon, 24 Sep 2018 16:35:14 +0000 (16:35 +0000)]
[ARM] Adjust the cost model for Exynos
Tune `MaxInterleaveFactor` and `LdStMultipleTiming`and remove
`PartialUpdateClearance` for the Exynos processors.
llvm-svn: 342900
Evandro Menezes [Mon, 24 Sep 2018 16:35:09 +0000 (16:35 +0000)]
[ARM] Adjust the feature set for Exynos
Enable crypto and literals fusion for the Exynos processors.
llvm-svn: 342899
Zhaoshi Zheng [Mon, 24 Sep 2018 16:15:23 +0000 (16:15 +0000)]
[Thumb1] Any imm8 should have cost of 1
A simple MOVS rd, imm8 can materialize [-128, 127] in signed i8 type or
[0, 255] in unsigned i8 type on Thumb1.
Differential Revision: https://reviews.llvm.org/D52257
llvm-svn: 342898
Michal Gorny [Mon, 24 Sep 2018 16:10:25 +0000 (16:10 +0000)]
[python] [tests] Update test_code_completion
Update expected completions to match output generated by clang-7.0.
Differential Revision: https://reviews.llvm.org/D50171
llvm-svn: 342897
Fedor Sergeev [Mon, 24 Sep 2018 16:08:15 +0000 (16:08 +0000)]
[New PM][PassInstrumentation] IR printing support for New Pass Manager
Implementing -print-before-all/-print-after-all/-filter-print-func support
through PassInstrumentation callbacks.
- PrintIR routines implement printing callbacks.
- StandardInstrumentations class provides a central place to manage all
the "standard" in-tree pass instrumentations. Currently it registers
PrintIR callbacks.
Reviewers: chandlerc, paquette, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D50923
llvm-svn: 342896
Luke Cheeseman [Mon, 24 Sep 2018 15:55:35 +0000 (15:55 +0000)]
[AArch64] Unwinding support for return address signing
- When return address signing is enabled, the LR may be signed on function entry
- When an exception is thrown the return address is inspected used to unwind the call stack
- Before this happens, the return address must be correctly authenticated to avoid causing an abort by dereferencing the signed pointer
Differential Revision: https://reviews.llvm.org/D51432
llvm-svn: 342895
Will Wilson [Mon, 24 Sep 2018 15:28:03 +0000 (15:28 +0000)]
[lld-link] Generalize handling of /debug and /debug:{none,full,fastlink,ghash,symtab}
Implement final argument precedence if multiple /debug arguments are passed on the command-line to match expected link.exe behavior.
Support /debug:none and emit warning for /debug:fastlink with automatic fallback to /debug:full.
Emit error if last /debug:option is unknown.
Emit warning if last /debugtype:option is unknown.
https://reviews.llvm.org/D50404
llvm-svn: 342894
Kristina Brooks [Mon, 24 Sep 2018 15:26:08 +0000 (15:26 +0000)]
Revert "rL342883: [Clang][CodeGen][ObjC]: Fix CoreFoundation on ELF with `-fconstant-cfstrings`."
Seems to be causing buildbot failures, need to look into it.
llvm-svn: 342893
Simon Pilgrim [Mon, 24 Sep 2018 15:21:57 +0000 (15:21 +0000)]
[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)
Split WriteIMul by size and also by IMUL multiply-by-imm and multiply-by-reg cases.
This removes all the scheduler overrides for gpr multiplies and stops WriteMULH being ignored for BMI2 MULX instructions.
llvm-svn: 342892
Luke Cheeseman [Mon, 24 Sep 2018 15:13:48 +0000 (15:13 +0000)]
[Arm][AsmParser] Restrict register list size for VSTM/VLDM
- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52082
llvm-svn: 342891
Kristina Brooks [Mon, 24 Sep 2018 14:52:48 +0000 (14:52 +0000)]
[CFString][ELF] Fix a missed test causing buildbot failures from 342883.
Accidetanlly forgot to update it, big sorry.
llvm-svn: 342890
Eric Liu [Mon, 24 Sep 2018 14:52:11 +0000 (14:52 +0000)]
[VFS] Use llvm::StringMap instead of std::map. NFC
llvm-svn: 342889
Sam McCall [Mon, 24 Sep 2018 14:51:15 +0000 (14:51 +0000)]
[clangd] Do bounds checks while reading data, otherwise var-length records are too painful. NFC
llvm-svn: 342888
Ed Maste [Mon, 24 Sep 2018 14:47:56 +0000 (14:47 +0000)]
Correct RISC-V link in release notes
llvm-svn: 342887
Sanjay Patel [Mon, 24 Sep 2018 14:47:15 +0000 (14:47 +0000)]
[DAGCombiner] use UADDO to optimize saturated unsigned add
This is a preliminary step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613
If we have an 'add' instruction that sets flags, we can use that to eliminate an
explicit compare instruction or some other instruction (cmn) that sets flags for
use in the later select.
As shown in the unchanged tests that use 'icmp ugt %x, %a', we're effectively
reversing an IR icmp canonicalization that replaces a variable operand with a
constant:
https://rise4fun.com/Alive/V1Q
But we're not using 'uaddo' in those cases via DAG transforms. This happens in
CGP after D8889 without checking target lowering to see if the op is supported.
So AArch already shows 'uaddo' codegen for the i8/i16/i32/i64 test variants with
"using_cmp_sum" in the title. That's the pattern that CGP matches as an unsigned
saturated add and converts to uaddo without checking target capabilities.
This patch is gated by isOperationLegalOrCustom(ISD::UADDO, VT), so we see only
see AArch diffs for i32/i64 in the tests with "using_cmp_notval" in the title
(unlike x86 which sees improvements for all sizes because all sizes are 'custom').
But the AArch code (like x86) looks better when translated to 'uaddo' in all cases.
So someone that is involved with AArch may want to set i8/i16 to 'custom' for UADDO,
so this patch will fire on those tests.
Another possibility given the existing behavior: we could remove the legal-or-custom
check altogether because we're assuming that a UADDO sequence is canonical/optimal
before we ever reach here. But that seems like a bug to me. If the target doesn't
have an add-with-flags op, then it's not likely that we'll get optimal DAG combining
using a UADDO node. This is similar justification for why we don't canonicalize IR to
the overflow math intrinsic sibling (llvm.uadd.with.overflow) for UADDO in the first
place.
Differential Revision: https://reviews.llvm.org/D51929
llvm-svn: 342886
Anastasia Stulova [Mon, 24 Sep 2018 14:21:56 +0000 (14:21 +0000)]
Revert "We allow implicit function declarations as an extension in all C dialects. Remove OpenCL special case."
Discussed on cfe-commits (Week-of-Mon-
20180820), this change leads to
the generation of invalid IR for OpenCL without giving an error.
Therefore, the conclusion was to revert.
llvm-svn: 342885
Petar Jovanovic [Mon, 24 Sep 2018 14:14:19 +0000 (14:14 +0000)]
[Mips][FastISel] Fix selectBranch on icmp i1
The r337288 tried to fix result of icmp i1 when its input is not sanitized
by falling back to DagISel. While it now produces the correct result for
bit 0, the other bits can still hold arbitrary value which is not supported
by MipsFastISel branch lowering. This patch fixes the issue by falling back
to DagISel in this case.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D52045
llvm-svn: 342884
Kristina Brooks [Mon, 24 Sep 2018 14:06:47 +0000 (14:06 +0000)]
[Clang][CodeGen][ObjC]: Fix CoreFoundation on ELF with `-fconstant-cfstrings`.
[Clang][CodeGen][ObjC]: Fix non-bridged CoreFoundation builds on ELF targets
that use `-fconstant-cfstrings`. The original changes from differential
for a similar patch to PE/COFF (https://reviews.llvm.org/D44491) did not
check for an edge case where the global could be a constant which surfaced
as an issue when building for ELF because of different linkage semantics.
This patch addresses several issues with crashes related to CF builds on ELF
as well as improves data layout by ensuring string literals that back
the actual CFConstStrings end up in .rodata in line with Mach-O.
Change itself tested with CoreFoundation on Linux x86_64 but should be valid
for BSD-like systems as well that use ELF as the native object format.
Differential Revision: https://reviews.llvm.org/D52344
llvm-svn: 342883
Zaara Syeda [Mon, 24 Sep 2018 14:01:16 +0000 (14:01 +0000)]
[PowerPC] Support operand modifier 'x' in inline asm
gcc uses operand modifier 'x' in inline asm for VSX registers.
Without this modifier, instructions which use VSX numbering for their
operands are printed as VMX registers. This patch adds support for the
operand modifier 'x'.
Differential Revision: https://reviews.llvm.org/D52244
llvm-svn: 342882
Jonas Devlieghere [Mon, 24 Sep 2018 13:56:36 +0000 (13:56 +0000)]
[dsymutil] Set LSan blacklist whenever sanitizers are enabled.
LSan can be enabled by itself or as part of the address sanitizer.
Rather than checking the enabled sanitizers for both, just set the LSan
env options whenever a sanitizer is enabled.
llvm-svn: 342881
Roman Lebedev [Mon, 24 Sep 2018 13:24:20 +0000 (13:24 +0000)]
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants
It would be best to introduce ISD::BitFieldExtract,
because clearly more than one backend faces the same problem.
But for now let's solve this in the x86-specific DAG combine.
https://bugs.llvm.org/show_bug.cgi?id=38938
llvm-svn: 342880
Matt Arsenault [Mon, 24 Sep 2018 13:18:15 +0000 (13:18 +0000)]
AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses
If the alignment is at least 4, this should report true.
Something still seems off with how < 4-byte types are
handled here though.
Fixing this seems to change how some combines get
to where they get, but somehow isn't changing the net
result.
llvm-svn: 342879
Matt Arsenault [Mon, 24 Sep 2018 12:47:17 +0000 (12:47 +0000)]
Fix some missing opcodes in bcanalyzer
llvm-svn: 342878
Andrea Di Biagio [Mon, 24 Sep 2018 12:45:26 +0000 (12:45 +0000)]
[llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFC
llvm-svn: 342877
Sven van Haastregt [Mon, 24 Sep 2018 12:12:03 +0000 (12:12 +0000)]
Fix Wundef NDEBUG warning; NFC
Check for definedness of the NDEBUG macro rather than its value,
to be consistent with other uses.
llvm-svn: 342876
Pavel Labath [Mon, 24 Sep 2018 12:11:04 +0000 (12:11 +0000)]
Add NativeProcessProtocol unit tests
Summary:
NativeProcessProtocol is an abstract class, but it still contains a
significant amount of code. Some of that code is tested via tests of
specific derived classes, but these tests don't run everywhere, as they
are OS and arch-specific. They are also relatively high-level, which
means some functionalities (particularly the failure cases) are
hard/impossible to test.
In this approach, I replace the abstract methods with mocks, which
allows me to inject failures into the lowest levels of breakpoint
setting code and test the class behavior in this situation.
Reviewers: zturner, teemperor
Subscribers: mgorny, lldb-commits
Differential Revision: https://reviews.llvm.org/D52152
llvm-svn: 342875
Sjoerd Meijer [Mon, 24 Sep 2018 12:02:50 +0000 (12:02 +0000)]
[ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33
A sequence of VMUL and VADD instructions always give the same or better
performance than a fused VMLA instruction on the Cortex-M4 and Cortex-M33.
Executing the VMUL and VADD back-to-back requires the same cycles, but
having separate instructions allows scheduling to avoid the hazard between
these 2 instructions.
Differential Revision: https://reviews.llvm.org/D52289
llvm-svn: 342874
Hans Wennborg [Mon, 24 Sep 2018 11:40:07 +0000 (11:40 +0000)]
Revert r341932 "[ARM] Enable ARMCodeGenPrepare by default"
This caused miscompilation of WebRTC for Android: PR39060.
> We've had the pass enabled downstream for a couple of weeks and it
> seems to be okay, so enable it by default.
>
> Differential Revision: https://reviews.llvm.org/D51920
llvm-svn: 342873
Luke Cheeseman [Mon, 24 Sep 2018 10:42:22 +0000 (10:42 +0000)]
[ARM][ARMLoadStoreOptimizer]
- The load store optimizer is currently merging multiple loads/stores into VLDM/VSTM with more than 16 doubleword registers
- This is an UNPREDICTABLE instruction and shouldn't be done
- It looks like the Limit for how many registers included in a merge got dropped at some point so I am reintroducing it in this patch
- This fixes https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52085
llvm-svn: 342872
Petar Jovanovic [Mon, 24 Sep 2018 10:01:24 +0000 (10:01 +0000)]
[deadargelim] Update dbg.value of 'unused' parameters
DeadArgElim pass marks unused function arguments as ‘undef’ without updating
existing dbg.values referring to it. As a consequence the debug info
metadata in the final executable was wrong.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D51968
llvm-svn: 342871
Sam Parker [Mon, 24 Sep 2018 09:34:06 +0000 (09:34 +0000)]
[ARM] bottom-top mul support ARMParallelDSP
Originally committed in rL342210 but was reverted in rL342260 because
it was causing issues in vectorized code, because I had forgotten to
ensure that we're operating on scalar values.
Original commit message:
On failing to find sequences that can be converted into dual macs,
try to find sequential 16-bit loads that are used by muls which we
can then use smultb, smulbt, smultt with a wide load.
Differential Revision: https://reviews.llvm.org/D51983
llvm-svn: 342870
Dan Liew [Mon, 24 Sep 2018 09:30:33 +0000 (09:30 +0000)]
When running the ios/iossim prepare script show the script output when it returns with a non-zero exit code.
Summary:
Previously we'd just show the exception and not the output from the
executed script. This is unhelpful in the case that the script actually
reports some useful information on the failure.
Now we print the output and re-raise the exception.
Reviewers: kubamracek, george.karpenkov
Subscribers: #sanitizers, llvm-commits
Differential Revision: https://reviews.llvm.org/D52350
llvm-svn: 342869
Dan Liew [Mon, 24 Sep 2018 09:28:35 +0000 (09:28 +0000)]
Fix the configuration of the Primary allocator for Darwin ARM64 by
changing the value of `SANITIZER_MMAP_RANGE_SIZE` to something more
sensible. The available VMA is at most 64GiB and not 256TiB that
was previously being used.
This change gives us several wins:
* Drastically improves LeakSanitizer performance on
Darwin ARM64 devices. On a simple synthentic benchmark
this took leak detection time from ~30 seconds to 0.5 seconds
due to the `ForEachChunk(...)` method enumerating a much smaller
number of regions. Previously we would pointlessly iterate
over a large portion of the SizeClassAllocator32's ByteMap
that would could never be set due it being configured for a much
larger VM space than is actually availble.
* Decreases the memory required for the Primary allocator.
Previously the ByteMap inside the the allocator used
an array of pointers that took 512KiB of space. Now the required
space for the array is 128 bytes.
rdar://problem/
43509428
Differential Revision: https://reviews.llvm.org/D51173
llvm-svn: 342868
Kirill Bobyrev [Mon, 24 Sep 2018 08:45:18 +0000 (08:45 +0000)]
[clangd] Force Dex to respect symbol collector flags
`Dex` should utilize `FuzzyFindRequest.RestrictForCodeCompletion` flags
and omit symbols not meant for code completion when asked for it.
The measurements below were conducted with setting
`FuzzyFindRequest.RestrictForCodeCompletion` to `true` (so that it's
more realistic). Sadly, the average latency goes down, I suspect that is
mostly because of the empty queries where the number of posting lists is
critical.
| Metrics | Before | After | Relative difference
| ----- | ----- | ----- | -----
| Cumulative query latency (7000 `FuzzyFindRequest`s over LLVM static index) |
6182735043 ns |
7202442053 ns | +16%
| Whole Index size | 81.24 MB | 81.79 MB | +0.6%
Out of 292252 symbols collected from LLVM codebase 136926 appear to be
restricted for code completion.
Reviewers: ioeric
Differential Revision: https://reviews.llvm.org/D52357
llvm-svn: 342866
Clement Courbet [Mon, 24 Sep 2018 08:39:48 +0000 (08:39 +0000)]
[llvm-exegesis] Fix PR39021.
Summary:
The `set` statements was incorrectly reading the value of the local variable and
setting the value of the parent variable.
Reviewers: tycho, gchatelet, john.brawn
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52343
llvm-svn: 342865
Hans Wennborg [Mon, 24 Sep 2018 08:34:17 +0000 (08:34 +0000)]
Fix llvm-diff anon-func.ll test
llvm-svn: 342864
Hans Wennborg [Mon, 24 Sep 2018 08:18:47 +0000 (08:18 +0000)]
Remove debug printf leftover from r342397
llvm-svn: 342863
Sjoerd Meijer [Mon, 24 Sep 2018 07:55:20 +0000 (07:55 +0000)]
[ARM][AArch64] Add feature +fp16fml
Armv8.4-A adds a few FP16 instructions that can optionally be implemented
in CPUs of Armv8.2-A and above.
This patch adds a feature to clang to permit selection of these
instructions. This interacts with the +fp16 option as follows:
Prior to Armv8.4-A:
*) +fp16fml implies +fp16
*) +nofp16 implies +nofp16fml
From Armv8.4-A:
*) The above conditions apply, additionally: +fp16 implies +fp16fml
Patch by Bernard Ogden.
Differential Revision: https://reviews.llvm.org/D50229
llvm-svn: 342862