blorp: drop undefined macro

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 97d6ceaf04 ("intel: Remove GEN_IS_HASWELL macro")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>

crocus: fix GFX_VERx10 macro

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>

crocus: add a __gen_get_batch_address declaration

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>

anv: use the lineage number for WA

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d0669f3ede ("intel/dev: switch defect identifiers to use lineage numbers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>

iris: use the correct WA macros and lineage numbers

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0ce595a89a ("intel: use generated helpers for Wa_1508744258")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>

anv: drop dead ifdef

The GFX_VERX10 macro doesn't exist and we no longer use
SCRATCH_SURFACE_STATE_POOL_SIZE.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b3f6e5dc702 ('anv: remove incorrect ifdef')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>

intel: Limit Intel Vulkan RT to x86_64

Note: passed CI repeatedly except for the timing out WHL jobs.

Fixes: 28c1053c07c ("intel: Allow using intel_clc from the system")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25009>

ci: Disable WHL jobs

Timing out all day.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

ci: Disable known broken Bifrost Vulkan job

Until someone does the work to eliminate faults, PanVK will be inherently flaky
and should not be in CI. deqp-runner can eat a lot of flakes, and then retrying
the whole job eats more flakes, but neither is a substitute for not testing
known broken (and hence flaky) code and both increase runtime unacceptably. the
g52-vk job earned 2 spots on the latest leaderboard for slowest jobs, I clicked
on https://gitlab.freedesktop.org/mesa/mesa/-/jobs/48142375 to see a jawdropping
54 flakes reported by deqp-runner.

If people insist on keeping the job, then panfrost-g52-vk needs to be demoted to
manual until after someone fixes all these bugs on the driver side. If that's
not going to happen, then there's no point in it being in CI at all. It's broken
code. After a buggy MR, it'll still be broken code. CI doesn't matter if we're
ok with it being broken.

Bottom line is, we can't be running known broken code in CI (bugs = faults =
flakes = unhappy developers), at least for non-robust stacks (panfrost.ko
included). This needs to be policy if it isn't already. Merging this single
character change deals with the hot problem without any fanfare or adverse
effects.

This turns the job into a nightly as David suggested to get it out of the
premerge path until someone is committed to supporting it and does the work to
make it happen.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9721
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24943>

aco: implement some exclusive scans with inclusive scans

exclusive scan lowering uses full wave shift, for iadd/ixor it's faster
to do inclusive scans and subtract/xor the thread's source.

Foz-DB Navi21:
Totals from 21 (0.02% of 132657) affected shaders:
Instrs: 10925 -> 10727 (-1.81%)
CodeSize: 58064 -> 56488 (-2.71%)
Latency: 178471 -> 177928 (-0.30%)
InvThroughput: 24374 -> 24145 (-0.94%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24555>

rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24982>

nir: add nir_scalar_equal

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>

nir: add nir_scalar intrinsic helpers

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>

docs: add LAVA farm informations

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>

Revert "ci: disable a660 jobs"

This reverts commit 209ed8eace0ba9095e3ef956a10cd9196407047f.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>

anv: enable standard Y tiles

We kept those tilings disabled up to know. Now that ISL has proper
support for them, remove this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

anv: Align memory VA to support for Ys, Tile64 tiled images

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: enable Tile64 for 3D images

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Allow Ys tiling

Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: reorder tiling selection

Select tilings in this order :
  - recommended Y tilings
  - Yf tilings
  - Ys/Tile64 tilings
  - legacy tilings (W, X) & Linear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/aux_map: correctly program tiling mode for Ys

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling

The data in Ys/Yf/Tile64 tiled images is arranged differently for 2D &
3D images. Therefore we cannot assume that we will use 2D images for
blits/copies.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: disable CCS on Ys/Yf

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: disable miptails on gfx12 with yuv formats

A number of CTS tests are failing, like :

   dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal

Failures are reproduced on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: disallow miptails on planar formats

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: add Gfx12/12.5 restriction on 3D surfaces & compression

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Disallow CCS on 3D surfaces with miptails

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Start using miptails

This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Support miptails in isl_surf_get_uncompressed_surf

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: make isl_surf_get_uncompressed_surf robust to argument accesses

Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Add support for computing offsets with miptails

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Add a max_miptail_levels field to isl_tile_info

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Add initial data-structure support for miptails

This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code.  We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Support Yf/Ys tiling in surf_fill_state

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Indent uncompressed surface code

We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64

With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us.  We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces

This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: disallow TileYs/Yf on 3D storage images on Gfx9/11

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: add a usage flag to request 2D/3D compatible views

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: disable Yf/Ys/Tile64 tilings for 1D images

The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Implement correct tile size calculations for Ys/Yf

The tile size calculations use a clever bit of math to make them short
and simple.  We add unit tests to assert that they identically match the
tables in the PRM.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Add ICL variants of Yf and Ys tiling

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s

The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented

Since this value is 0, it doesn't change anything, but it's just good
practice like we did for Gfx12.5 right above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

genxml/gfx12: rename Tiled Resource Mode

To match documentation.

BSpec 46965

TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER

This field doesn't exist according to documentation. Only a MBZ.

BSpec 6511

ICL PRMs, Volume 2a - Command Reference: Instructions (Command
Opcodes) 3DSTATE_HIER_DEPTH_BUFFER

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

anv: add missing ISL storage usage

ISL makes a bunch of decision on programming (MOCS,
RENDER_SURFACE_STATE values) based on this flag. It's important to set
it if we're going to use an image as storage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

intel: Allow using intel_clc from the system

With -Dintel-clc=system, the build system will search for an `intel_clc`
binary and use it instead of building `intel_clc` itself.

This allows Intel Vulkan ray tracing support to be built when cross
compiling without terrible hacks (that would otherwise be necessary due
to `intel_clc`'s dependence on SPIRV-LLVM-Translator, libclc, clang, and
LLVM).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24983>

rusticl/memory: do not verify pitch for IMAGE1D_BUFFER

Devices might report an image_pitch_alignment of 0 leading to a division
by 0 trap.

Fixes: 06daa03c5cd ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>

ci/amd: split the polaris10 rules into one for each farm

There is now one polaris10 in each farm, so we need two rules for which
one to use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>

intel: allow reduced memory usage for INTEL_MEASURE

The default batch size was increased to support large numbers of
INTEL_MEASURE snapshots for complex workloads.  Some titles create
large numbers of small secondary command buffers, and quickly exhaust
memory.  An example of this is Dota2, where INTEL_MEASURE increases
the memory usage by a factor of 20.

Allow the user to specify smaller batch sizes and buffer sizes.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24860>

aco: use v_cvt_f32_ubyte for signed casts too

The extract is always positive, so signed vs unsigned conversion doesn't matter.

Foz-DB GFX11:
Totals from 167 (0.13% of 133461) affected shaders:
Instrs: 401631 -> 401225 (-0.10%)
CodeSize: 2107256 -> 2104344 (-0.14%)
VGPRs: 13320 -> 13332 (+0.09%)
Latency: 6468063 -> 6467241 (-0.01%)
InvThroughput: 801854 -> 801653 (-0.03%)
Copies: 13926 -> 13927 (+0.01%); split: -0.08%, +0.09%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24893>

anv: Initialize the clear color more often for FCV

Instead of only initializing the clear color when the first subresource
is accessed, initialize it for every FCV-enabled subresource. This is
needed because writes to any subresource may be converted to fast
clears.

Now that init_fast_clear_color is called for every subresource, we take
care not to stomp on the fast-clear-tracking state of the first
subresource by moving the code which updates it outside of
init_fast_clear_color.

Now init_fast_clear_color does just what it says: initializes the fast
clear color.

This fixes the regression introduced with commit 57445adc891,
("anv: Re-enable CCS_E on TGL+").

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8461
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24857>

radv/ci: re-enable vkcts-polaris10-valve

This was disabled a long time ago because of unknown GPU hangs during
boot but it seems stable again for some reasons.

This also bumps the job timeouts to make sure it will be able to finish.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24968>

rusticl/queue: properly implement clCreateCommandQueueWithProperties

It didn't do any of the error checking, but it was supposed to be. Also
the error checking was slightly wrong and we should return
CL_INVALID_QUEUE_PROPERTIES instead of CL_INVALID_VALUE for unsupported
properties.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24991>

zink/ci: add zink-radv-polaris10-valve

This introduces Zink/RADV testing on Polaris10!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24976>

meson: Move video to separate section in meson configuration summary

Since the video configuration is shared by multiple video APIs, not
just vulkan, move it to a separate section.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24598>

ci: add a fix for KHR-GLES3.packed_pixels.*snorm tests

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>

mesa: remove GL_UNSIGNED_BYTE as supported for snorm reads

UNSIGNED_BYTE should not be allowed for reading snorm color buffers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9718
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>

pvr: Implement VK_EXT_tooling_info

This commit will enable the EXT_tooling_info extension,
which was already implemented in the common code.

Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24928>

anv: use the pre defined _3DPRIMITIVE_DIRECT macro

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24978>

aco/lower_to_cssa: Fix typo

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>

radv: Only generate debug info if required

Fixes: 51f2fa1a5ef ("radv: Break up radv_shader_nir_to_asm")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>

aco: Unify demote and demote_if selection

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>

aco: Use bytes() instead of size() in emit_wqm

This should get most of the cases that would fail validation.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>

aco/validate: Handle p_wqm like p_parallelcopy

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>

aco: allow separate compilation of NGG shaders

Also prevent to emit a long-jump for VS as NGG without a GS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>

aco: adjust fix_exports() for VS/TES as NGG and non-monolithic shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>

aco: flag blocks with long-jump as export_end for separate compilation

This will allow us to adjust fix_exports().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>

radv: preserve shader argument for separate compilation of NGG shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>

radeonsi: enable aco compile for part mode standalone vs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>

radeonsi: set vs has prolog aco shader info

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>

radeonsi: add vs prolog aco build

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>

radeonsi: fix aco options has_ls_vgpr_init_bug setup

Fixes: b313d950e23 ("radeonsi: enable aco compile for mono merged LS/HS")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>

radeonsi: extract si_get_vs_prolog_args to be shared with aco

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>

radeonsi: remove is_monolithic from vs prolog key

We do not generate vs prolog for monolithic shader any more.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>

nvk: add build_id linker argument.

the build id was failing for a gentoo build causing instance
creation to fail, this seems to fix it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24916>

radeonsi: fill aco_shader_info->is_monolithic

Fixes: 80177e02962 ("aco: add support for compiling VS+TCS separately on GFX9+")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24944>

rusticl/event: disable profiling for devices without timestamps

Timestamp queries are strictly required, but a bit odd to not expose CL
for not supporting it...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>

rusticl/query: fix use-after-free, but also fix incorrect usage of unsafe

`PipeQuery::new` create a `PipeQuery` wrapper before handling errors, so
we ended up calling `drop` and destroy_query, meaning the latter ended up
being called twice.

While at it, also restrict visibility of related methods and add some
unsafe declarations.

Fixes: 52e53938c37 ("rusticl: Wrap pipe queries")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>

docs: Add row for VK_KHR_maintenance5

Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24980>

intel: Only build perf if drivers or tools are enabled

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>

intel: Only build ds if drivers are enabled

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>

intel: Only build blorp if drivers are enabled

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>

intel: Consider with_intel_clc in with_any_intel

This makes it possible to configure mesa to build only intel_clc.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>

intel: Rearrange for next commit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>

radeonsi: use wave size to determine index stride

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>

radeonsi: use AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 to determine wave size

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>

amd/common: add AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 property

This property can be used to determine wave size on gfx10+.

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>

freedreno/a7xx: Add CP_RESET_CONTEXT_STATE

Used by the kernel driver. Definition taken from kgsl.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24969>

egl: bind dri2_set_WL_bind_wayland_display for zink when necessary

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24701>

egl: call dri3_x11_connect() for zink

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24701>

egl/dri3: only set driver_name if not already set

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24701>

ci/b2c: assert that install folder is present whether or not the tarball was extracted

We already `rm -rf install` at the beginning so it can't be a stale install folder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24970>

ci/b2c: don't allow failures in test script preparation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24970>

ci/b2c: skip install.tar extraction if the tarball is not present

This is the case when retrying after a B2C_TIMEOUT for instance.

Fixes: 85a8f03211090bc9a23a ("ci: delete install.tar after extracting it to avoid re-uploading it")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24970>

radv/rt: Pre-initialize instance address

It's not disallowed by spec to load instance-related data in case of a
miss where no instance was ever visited. Such loads make no sense, so we
can return garbage, but it mustn't hang the GPU. Initialize the instance
addresses to the TLAS base to make sure we always have valid memory to load from.

Partially fixes GPU hangs in RTX Remix games.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24971>