Icenowy Zheng [Mon, 12 Dec 2022 08:22:37 +0000 (16:22 +0800)]
lib: utils/timer: mtimer: add a quirk for lacking mtime register
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.
Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Anup Patel <anup@brainfault.org>
Icenowy Zheng [Mon, 12 Dec 2022 08:22:36 +0000 (16:22 +0800)]
lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the
MSWI part is compliant.
Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing
the same codepath with SiFive CLINT.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Anup Patel <anup@brainfault.org>
Bin Meng [Sun, 11 Dec 2022 06:54:24 +0000 (14:54 +0800)]
lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.
Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Bin Meng [Sun, 11 Dec 2022 06:54:23 +0000 (14:54 +0800)]
lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
plic->num_src holds the number of interrupt sources without interrupt
source 0 but the interrupt enable register includes a bit for the
interrupt source 0 in the first word.
Fixes:
415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Bin Meng [Sun, 11 Dec 2022 06:54:22 +0000 (14:54 +0800)]
lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
The number of interrupt enable register in words was once correct,
but was wrongly changed to have an off-by-one error since
commit
8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").
Fixes:
8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Bin Meng [Sun, 11 Dec 2022 06:54:21 +0000 (14:54 +0800)]
lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
Currently the priority save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.
Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Bin Meng [Sun, 11 Dec 2022 06:54:20 +0000 (14:54 +0800)]
lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers
Interrupt source 0 is reserved. Hence the irq should start from 1.
Fixes:
2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Lad Prabhakar [Sat, 10 Dec 2022 10:30:11 +0000 (10:30 +0000)]
docs: platform: Add documentation for Renesas RZ/Five SoC
This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Lad Prabhakar [Sat, 10 Dec 2022 10:30:10 +0000 (10:30 +0000)]
platform: generic: Add Renesas RZ/Five initial support
This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.
The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch
Useful links:
-------------
Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Lad Prabhakar [Sat, 10 Dec 2022 10:30:09 +0000 (10:30 +0000)]
lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.
While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.
dts example (Single-core AX45MP):
soc: soc {
....
plic: interrupt-controller@
12c00000 {
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
#interrupt-cells = <2>;
#address-cells = <0>;
riscv,ndev = <511>;
interrupt-controller;
reg = <0x0 0x12c00000 0 0x400000>;
clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
};
....
};
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Lad Prabhakar [Sat, 10 Dec 2022 10:30:08 +0000 (10:30 +0000)]
lib: utils: serial: Add FDT driver for Renesas SCIF
Add FDT driver for Renesas SCIF.
dts example:
soc: soc {
....
scif0: serial@
1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
<414 IRQ_TYPE_LEVEL_HIGH>,
<415 IRQ_TYPE_LEVEL_HIGH>,
<413 IRQ_TYPE_LEVEL_HIGH>,
<416 IRQ_TYPE_LEVEL_HIGH>,
<416 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
....
};
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Lad Prabhakar [Sat, 10 Dec 2022 10:30:07 +0000 (10:30 +0000)]
lib: utils: serial: Add Renesas SCIF driver
Add Renesas SCIF driver.
Based on a patch in the BSP by Takeki Hamada
<takeki.hamada.ak@bp.renesas.com>
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Himanshu Chauhan [Fri, 9 Dec 2022 06:13:35 +0000 (11:43 +0530)]
scripts: use env to invoke bash
Not all systems have bash at a fixed location like /bin/bash.
FreeBSD, for example, would typically have it at /usr/local/bin/bash.
When building OpenSBI on freebsd system, the build breaks.
Its advisable to use: #!/usr/bin/env bash
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Himanshu Chauhan [Mon, 5 Dec 2022 16:42:31 +0000 (22:12 +0530)]
lib: sbi: Synchronize PMP settings with virtual memory system
As per section 3.7.2 of RISC-V Privileged Specification,
PMP settings must be synchronized with the virtual memory
system after PMP settings have been written.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Heinrich Schuchardt [Thu, 8 Dec 2022 01:14:21 +0000 (02:14 +0100)]
lib: fix irqchip_plic_update_hartid_table
After determining cpu_offset we have to check this value.
Addresses-Coverity-ID: 1529706 ("Logically dead code")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Heinrich Schuchardt [Thu, 8 Dec 2022 01:14:20 +0000 (02:14 +0100)]
lib: fix __fdt_parse_region()
If fdt_getprop() returns NULL, this indicates an error. In this case lenp
is set to an error code. But even if lenp = 0 we should not continue.
If fdt_getprop() returns a wider value than we expect this is a separate
error condition.
In both cases the device-tree is invalid.
Addresses-Coverity-ID: 1529703 ("Dereference after null check")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Heinrich Schuchardt [Thu, 8 Dec 2022 01:14:19 +0000 (02:14 +0100)]
lib: fix is_region_valid()
For 'reg->order == __riscv_xlen' the term 'BIT(reg->order)' is undefined.
Addresses-Coverity-ID: 1529706 ("Bad bit shift operation")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Lad Prabhakar [Wed, 7 Dec 2022 16:14:19 +0000 (16:14 +0000)]
platform: generic: Make use of fdt_match_node()
It makes sense to use fdt_match_node() instead of fdt_find_match()
in fw_platform_lookup_special() as we already have the start offset
to search from.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Sergey Matyukevich [Sat, 3 Dec 2022 21:04:15 +0000 (00:04 +0300)]
gitignore: add vim swap files
Update .gitignore for vim swap files.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Lad Prabhakar [Fri, 2 Dec 2022 11:59:47 +0000 (11:59 +0000)]
lib: utils: Add fdt_fixup_node() helper function
Add a helper function fdt_fixup_node() based on the compatible string.
This will avoid code duplication for every new node fixup being added.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Mon, 5 Dec 2022 02:04:00 +0000 (10:04 +0800)]
scripts/create-binary-archive.sh: remove andes/ae350 build directory
The andes-specific files have been moved to generic platform so we
can drop this line.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Mon, 5 Dec 2022 02:03:59 +0000 (10:03 +0800)]
docs: andes-ae350.md: fix watchdog nodename in dts example
The example should use watchdog as nodename instead of wdt.
This is defined in watchdog common schemas:
https://github.com/torvalds/linux/blob/v6.0/Documentation/devicetree/bindings/watchdog/watchdog.yaml#L19
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Mon, 5 Dec 2022 02:03:58 +0000 (10:03 +0800)]
docs: platform: Update AE350 and generic platform documentation
Update compile option and platform compatible string for AE350 and
add it to the generic platform list.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Mon, 5 Dec 2022 02:03:57 +0000 (10:03 +0800)]
platform: generic/andes: Enable generic platform support for AE350
We move andes directory to platform/generic as the necessary fdt
drivers are available, the users can enable the console, timer, ipi,
irqchip and reset devices by adding device tree nodes stated in the
docs/platform/andes-ae350.md.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Dongdong Zhang [Tue, 29 Nov 2022 03:54:07 +0000 (11:54 +0800)]
firmware: Minor optimization for relocate
The t3 register stores the address of _load_end. If relocation is not
required, it is unnecessary to calculate the address of _load_end.
This can reduce the operation time of two instructions.
Signed-off-by: Dongdong Zhang <zhangdongdong@eswincomputing.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Heinrich Schuchardt [Mon, 28 Nov 2022 09:14:20 +0000 (10:14 +0100)]
lib: fix fdt_parse_aclint_node()
After determining cpu_offset we have to check this variable and not
cpu_intc_offset.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Heinrich Schuchardt [Mon, 28 Nov 2022 09:14:19 +0000 (10:14 +0100)]
lib: simplify fdt_translate_address()
Don't assign a value to offset which is never used.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Heinrich Schuchardt [Mon, 28 Nov 2022 09:14:18 +0000 (10:14 +0100)]
lib: fix fdt_parse_plicsw_node()
cpu_offset and cpu_intc_offset must be int to detect failed invocations of
fdt_node_offset_by_phandle() or fdt_parent_offset().
After determining cpu_offset we have to check this value and not
cpu_intc_offset.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Heinrich Schuchardt [Mon, 28 Nov 2022 09:14:17 +0000 (10:14 +0100)]
lib: fix fdt_parse_plmt_node()
cpu_offset, cpu_intc_offset must be int to discover failed invocations of
fdt_node_offset_by_phandle() or fdt_parent_offset().
After determining cpu_offset we have to check this value and not
cpu_intc_offset.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Heinrich Schuchardt [Mon, 28 Nov 2022 09:14:16 +0000 (10:14 +0100)]
lib: simplify fdt_parse_plicsw_node()
We should not check !plicsw_base || !size twice.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Heinrich Schuchardt [Mon, 28 Nov 2022 09:14:15 +0000 (10:14 +0100)]
lib: simplify fdt_parse_plmt_node()
We should not check !plmt_base || !plmt_size twice.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Xiang W [Thu, 24 Nov 2022 03:16:05 +0000 (11:16 +0800)]
lib: sbi: Fix is_region_valid()
When order is equal to __riscv_xlen, the shift operation will not perform
any operation, which will cause reg->base & (BIT(reg->order) - 1) to always
be 0, and the condition has not been established.
This patch fixes this bug.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Xiang W [Thu, 24 Nov 2022 03:16:03 +0000 (11:16 +0800)]
lib: sbi: Simplified mmio match checking
We simplify the mmio flag matching in sbi_domain_check_addr().
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Alejandro Cabrera Aldaya [Tue, 22 Nov 2022 10:28:25 +0000 (12:28 +0200)]
Makefile: bugfix for handling platform paths
If the path where this repo is located contains the platform name on
it, the original Makefile replaced its occurrences from the path making
it an invalid path. This commit prevents this behavior replacing only
the last part of the path as intended.
Signed-off-by: Alejandro Cabrera Aldaya <aldaya@gmail.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
KaDiWa [Mon, 21 Nov 2022 15:59:05 +0000 (16:59 +0100)]
Makefile: replace `echo` with `printf` for compatibility
I don't know why but `echo -n` didn't work for me. macOS supports
the `-n` option but it doesn't work in the makefile. What it does
instead is it literally writes `-n` to the file and then also
leaves a newline at the end.
I'm using GNU Make 4.4 (`gmake` from Homebrew).
Signed-off-by: KaDiWa <kalle.wachsmuth@gmail.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Xiang W [Sat, 19 Nov 2022 08:55:07 +0000 (16:55 +0800)]
platform: generic/allwinner: Remove ghostly type cast
Corrected the same parameter of writel_relaxed in sun20i_d1_riscv_cfg_init
to be u32 for a while and u64 for a while.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Leizheng Zhang [Fri, 18 Nov 2022 05:20:29 +0000 (13:20 +0800)]
platform: generic/allwinner: Remove unused header files
Remove "#include <sbi/sbi_console.h>"
Signed-off-by: Leizheng Zhang <zhangleizheng@eswincomputing.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Xiang W <wxjstz@126.com>
Leizheng Zhang [Mon, 21 Nov 2022 08:26:22 +0000 (16:26 +0800)]
firmware: payloads: Optimize usage of "ALIGN"
Delete the redundant "ALIGN" and adjust the position of "ALIGN"
Signed-off-by: Leizheng Zhang <zhangleizheng@eswincomputing.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Vivian Wang [Wed, 9 Nov 2022 06:53:37 +0000 (14:53 +0800)]
lib: sbi_ecall: Split up sbi_ecall_replace
Split up sbi_ecall_replace so that each extension is in its individual
file.
Also reorganize the corresponding section in lib/sbi/objects.mk so
that it is grouped by extension, now that the object file targets are
split up.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Anup Patel [Tue, 8 Nov 2022 12:10:16 +0000 (17:40 +0530)]
lib: utils/serial: Fix semihosting compile error using LLVM
We fix the following semihosting compile error observed using LLVM:
lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
ret = ch > -1 ? ch : -1;
~~ ^ ~~
Fixes:
7f09fba86e43 ("lib: utils/serial: add semihosting support")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
zhangdongdong [Tue, 25 Oct 2022 00:57:41 +0000 (08:57 +0800)]
docs: fix some typos
Corrected the typos of some documents in the 'docs' folder.
Signed-off-by: zhangdongdong <zhangdongdong@eswincomputing.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Xiang W [Mon, 31 Oct 2022 11:21:45 +0000 (19:21 +0800)]
lib: utils/fdt: Simplified code
Simplified fdt_parse_xxx_uart_node which direct call
fdt_parse_uart_node_common.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Xiang W [Mon, 31 Oct 2022 11:21:44 +0000 (19:21 +0800)]
lib: utils/fdt: Remove redundant code
uart->reg_offset and uart->reg_io_width are only used on uart8250 and
not required on other platforms. Remove for sifive and gaisler.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Mon, 10 Oct 2022 16:34:45 +0000 (00:34 +0800)]
lib: sbi_ecall: Add Kconfig option for each extension
For each SBI extension, we:
- Add a Kconfig option for it
- Add the extension to sbi_ecall_exts only if the extension is enabled
- Add the corresponding sbi_ecall_* object file only if the extension is
enabled
Special cases are as follows:
- The legacy extensions are lumped together as one 'big' extension, as
has always been the case in OpenSBI code.
- The platform-defined vendor extensions are regarded as one extension.
- The Base extension cannot be disabled.
- sbi_ecall_replace implements multiple extensions, so it's not easy to
avoid linking it in. Enable it always, and use #ifdef to
disable/enable individual extensions.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Mon, 10 Oct 2022 16:34:44 +0000 (00:34 +0800)]
lib: sbi_ecall: Generate extensions list with carray
Instead of hard-coding the list of extensions in C code, use carray to
generate the list of extensions.
Using carray makes adding and removing extensions slightly cleaner. This
also paves the way for using Kconfig to disable unneeded extensions.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Mon, 10 Oct 2022 16:34:43 +0000 (00:34 +0800)]
Makefile: Add rules for carray sources in lib/sbi
Add back the missing rules needed to build carray files in lib/sbi. This
allows future usage of carray in lib/sbi.
Fixes:
de80e9337d81 ("Makefile: Compile lib/utils sources separately for each platform")
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yangjie Zhang [Thu, 20 Oct 2022 14:41:08 +0000 (22:41 +0800)]
docs/firmware: update the document
Since
commit
9c07c513aa9b ("firmware:Remove FW_PAYLOAD_FDT_PATH compile-time option"),
the section where FDT would be embedded in has changed from *.text* to *.rodata*,
but some places in fw_payload.md and fw.md are still *.text*.
This patch updates the document.
Signed-off-by: Yangjie Zhang <pyjmstr@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tan En De [Thu, 13 Oct 2022 01:26:23 +0000 (09:26 +0800)]
Makefile: Add cscope support
Add cscope support so that running `make cscope` will generate/update
cscope files used for source code browsing, while running `make
distclean` will remove the cscope files.
Also add entry in .gitignore to ignore generated cscope files.
Signed-off-by: Tan En De <ende.tan@linux.starfivetech.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:52 +0000 (08:32 +0800)]
docs: andes-ae350.md: Update ae350 documentation for fdt driver support
We update ae350 documentation to add details about platform device tree.
The nodes and their properties must be provided to properly initialize
data of underlying hardware and access their mmio registers.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:51 +0000 (08:32 +0800)]
platform: andes/ae350: Add AE350 domain support
Add domains_init platform hook for Andes AE350, users can add domain
description in device tree and select FDT domain support in Kconfig
to achieve system-level partitioning.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:50 +0000 (08:32 +0800)]
lib: utils/ipi: Add Andes fdt ipi driver support
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.
Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.
dts example (Quad-core AX45MP):
plicsw: interrupt-controller@
e6400000 {
compatible = "andestech,plicsw";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:49 +0000 (08:32 +0800)]
platform: andes/ae350: Add fw_platform_init for platform initialization
This patch adds fw_platform_init() to initialize ae350 platform.name
and platform.hart_count by parsing device tree.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:48 +0000 (08:32 +0800)]
platform: andes/ae350: Use fdt irqchip driver
Andes PLIC is compatible with plic driver. The PLIC base address and
number of source can be obtained by parsing the device tree.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:47 +0000 (08:32 +0800)]
lib: utils/reset: Add Andes fdt reset driver support
Add ATCWDT200 as reset device of AE350 platform, this driver requires
SMU to program the reset vector registers before triggering WDT software
restart signal.
dts example:
smu@
f0100000 {
compatible = "andestech,atcsmu";
reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
};
wdt: wdt@
f0500000 {
compatible = "andestech,atcwdt200";
reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
interrupts = <3 4>;
interrupt-parent = <&plic0>;
clock-frequency = <
15000000>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:46 +0000 (08:32 +0800)]
lib: utils/timer: Add Andes fdt timer support
Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.
dts example (Quad-core AX45MP):
cpus {
...
timebase-frequency = <0x3938700>;
...
}
soc {
...
plmt0@
e6000000 {
compatible = "andestech,plmt0";
reg = <0x00 0xe6000000 0x00 0x100000>;
interrupts-extended = <&cpu0_intc 0x07
&cpu1_intc 0x07
&cpu2_intc 0x07
&cpu3_intc 0x07>;
};
...
}
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:45 +0000 (08:32 +0800)]
platform: andes/ae350: Use fdt serial driver
Andes UART is compatible with uart8250 driver. We can use
fdt_serial_init() as platform console init hook.
dts example:
serial0: serial@
f0300000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
interrupts = <9 4>;
interrupt-parent = <&plic0>;
clock-frequency = <
19660800>;
current-speed = <38400>;
reg-shift = <2>;
reg-offset = <32>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:44 +0000 (08:32 +0800)]
platform: andes/ae350: Use kconfig to set platform version and default name
This patch makes andes platform name and version can be set in
menuconfig interface.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:43 +0000 (08:32 +0800)]
platform: andes/ae350: Remove enabling cache from an350_final_init
The boot-time cache operations have been handled by U-boot SPL, so we
can drop duplicate code.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:42 +0000 (08:32 +0800)]
lib: sbi: Add sbi_domain_root_add_memrange() API
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:41 +0000 (08:32 +0800)]
include: sbi: Fix grammar in comment
Fix minor grammar issue in function description.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:40 +0000 (08:32 +0800)]
lib: sbi: Fix typo in comment
%s/is is/is
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Yu Chien Peter Lin [Fri, 14 Oct 2022 00:32:39 +0000 (08:32 +0800)]
include: sbi: Fix typo in comment
%s/Priviledge/Privilege
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Heiko Stuebner [Tue, 4 Oct 2022 16:42:27 +0000 (18:42 +0200)]
platform: generic: allwinner: add support for c9xx pmu
With the T-HEAD C9XX cores being designed before or during ratification
of the SSCOFPMF extension, they implement a PMU extension that behaves
very similar but not equal to it by providing overflow interrupts though
in a slightly different registers format.
The sun20i-d1 is using this core. So implement the necessary overrides
to allow its pmu to be used via the standard sbi-pmu extension.
For now it's also the only soc using this core, so keep the additional
code in the d1-space for now.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Tue, 4 Oct 2022 16:42:26 +0000 (18:42 +0200)]
platform: generic: add extensions_init handler and platform-override
Init of non-standard extensions is a platform-specific thing,
so allow generic platforms to do this via a platform-override.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Tue, 4 Oct 2022 16:42:25 +0000 (18:42 +0200)]
lib: sbi_platform: expose hart_features to extension_init callback
The platform-specific extension_init callback is supposed to
set specific things for the platform opensbi is running on.
So it's also the right place to override specific hart_features
if needed - when it's know that autodetection has provided
wrong results for example.
Suggested-by: Atish Patra <atishp@atishpatra.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Tue, 4 Oct 2022 16:42:24 +0000 (18:42 +0200)]
lib: sbi_hart: move hart_features struct to a public location
Platforms may need to override auto-detected hart features
in their override functions. So move the hart_features
struct to the sbi_hart.h header allowing us to pass it over
to platform-handlers.
Suggested-by: Atish Patra <atishp@atishpatra.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Tue, 4 Oct 2022 16:42:23 +0000 (18:42 +0200)]
lib: sbi_pmu: move pmu irq information into pmu itself
Don't spread checking for pmu extensions through the code
but instead introduce a sbi-pmu function that other code can
call to get the correct information about the existence of the
pmu interrupt.
Add a sbi_pmu_device override function to allow overridung this
bit as well if needed.
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
zhangdongdong [Wed, 28 Sep 2022 02:35:30 +0000 (10:35 +0800)]
docs: Fix some typos
We fix few typos in documentation.
Signed-off-by: zhangdongdong <zhangdongdong@eswincomputing.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Nylon.Chen [Tue, 27 Sep 2022 07:34:09 +0000 (15:34 +0800)]
docs/firmware: Update FW_JUMP documentation
Add a tip for OpenSBI's FW_JUMP which helps
users avoid overwriting the kernel.
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Kautuk Consul [Mon, 12 Sep 2022 10:52:53 +0000 (16:22 +0530)]
lib: utils/serial: add semihosting support
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Rahul Pathak [Tue, 13 Sep 2022 09:47:08 +0000 (15:17 +0530)]
lib: sbi: Fix sbi_strnlen wrong count decrement
count(maxlen) should not be decremented here
Fixes:
1901e8a287bc ("platform: Add minimal libc support.")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Anup Patel [Tue, 13 Sep 2022 09:10:15 +0000 (14:40 +0530)]
lib: utils/fdt: Fix DT parsing in fdt_pmu_setup()
This patch does following fixes in fdt_pmu_setup():
1) If any of the event mapping DT property is absent or too small
then don't skip parsing of other DT properties.
2) Return failure if sbi_pmu_add_hw_event_counter_map() fails.
3) Return failure if sbi_pmu_add_raw_event_counter_map() fails.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Vivian Wang [Fri, 2 Sep 2022 15:48:35 +0000 (23:48 +0800)]
lib: sbi_misaligned_ldst: Set GVA if not emulating
If a particular misaligned load or store cannot be emulated at all, for
the redirected trap, trap.gva is set to 0, but it should be the same as
mstatus[h].GVA of the original trap. Fix this so that if the trap is
destined for HS-mode, hstatus.GVA is then set correctly.
Fixes:
1c4ce74f5128 ("lib: sbi: Set gva when creating sbi_trap_info")
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Fri, 2 Sep 2022 15:48:34 +0000 (23:48 +0800)]
lib: sbi_trap: Add helper to get GVA in sbi_trap_regs
The GVA bit is in mstatus on RV64, and in mstatush in RV32. Refactor
code handling this in sbi_trap_handler into a helper function to extract
GVA from sbi_trap_regs, so that future code accessing GVA can be
XLEN-agnostic.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Nikita Shubin [Fri, 2 Sep 2022 07:41:04 +0000 (10:41 +0300)]
docs: pmu: extend bindings example for Unmatched
Extend example for Unmatched board to provide SBI PMU bindings
for generalized and cache event's where they are applicable.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Nikita Shubin [Fri, 2 Sep 2022 07:41:03 +0000 (10:41 +0300)]
docs: pmu: fix Unmatched example typo
bitmap for MHPMCOUNTERx should be 0x18 and not 0x0c, we check
against SBI_PMU_FIXED_CTR_MASK which assumes than first 3 bits are
dedicated to mcycle, mtime and minstret, u74 has 2 hardware counters.
Reported-by: Zhang Xin <zhangxin.xa@gmail.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Anup Patel [Wed, 24 Aug 2022 11:19:30 +0000 (16:49 +0530)]
include: sbi: Reduce includes in sbi_pmu.h
The sbi_pmu.h should only include minimal required headers whereas
sbi_pmu.c should include all required headers.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Wed, 24 Aug 2022 09:59:27 +0000 (15:29 +0530)]
lib: sbi: Print platform PMU device at boot-time
Let us print the platform PMU device name at the boot-time so that users
know whether the underlying platform has custom per-HART PMU operations.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Wed, 24 Aug 2022 09:41:41 +0000 (15:11 +0530)]
lib: sbi_pmu: Add custom PMU device operations
We extend SBI PMU implementation to allow custom PMU device operations
which a platform can use for platform specific quirks.
The custom PMU device operations added by this patch include:
1) Operations to allow a platform implement custom firmware events.
These custom firmware events can be SBI vendor extension related
events or platform specific per-HART events are not possible to
count through HPM CSRs.
2) Operations to allow a platform implement custom way for enabling
(or disabling) an overflow interrupt (e.g. T-Head C9xx).
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Wed, 24 Aug 2022 07:57:19 +0000 (13:27 +0530)]
lib: sbi_pmu: Simplify FW counters to reduce memory usage
Currently, we have 32 elements (i.e. SBI_PMU_FW_EVENT_MAX) array of
"struct sbi_pmu_fw_event" for each of 128 possible HARTs
(i.e. SBI_HARTMASK_MAX_BITS).
To reduce memory usage of OpenSBI, we update FW counter implementation
as follows:
1) Remove SBI_PMU_FW_EVENT_MAX
2) Remove "struct sbi_pmu_fw_event"
3) Create per-HART bitmap of XLEN bits to track FW counters
which are started on each HART
4) Create per-HART uint64_t array to track values of FW
counters on each HART.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Wed, 24 Aug 2022 06:14:40 +0000 (11:44 +0530)]
lib: sbi_pmu: Firmware counters are always 64 bits wide
As-per SBI specification, all firmware counters are always 64 bits
wide so let us update the SBI PMU implementation to reflect this fact.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Wed, 24 Aug 2022 06:09:02 +0000 (11:39 +0530)]
lib: sbi_pmu: Replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read()
The "read a firmware counter" SBI call should only work for firmware
counters so let us replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read()
which works only on firmware counters.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Wed, 24 Aug 2022 05:50:15 +0000 (11:20 +0530)]
lib: sbi_pmu: Remove "event_idx" member from struct sbi_pmu_fw_event
The "event_idx" member of struct sbi_pmu_fw_event is not used
anywhere so let us remove it.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Rahul Pathak [Wed, 24 Aug 2022 14:54:37 +0000 (20:24 +0530)]
include: Remove sideleg and sedeleg
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.
These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -
commit
f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit
b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Jun Liang Tan [Wed, 17 Aug 2022 15:40:56 +0000 (23:40 +0800)]
lib: utils: serial: Add Cadence UART driver
Add Cadence UART driver
Signed-off-by: Jun Liang Tan <junliang.tan@linux.starfivetech.com>
Signed-off-by: Wei Liang Lim <weiliang.lim@linux.starfivetech.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Anup Patel [Thu, 18 Aug 2022 15:07:03 +0000 (20:37 +0530)]
lib: sbi: Use the official extension name for AIA M-mode CSRs
The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).
Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf)
Based on above, we update generic library to use "Smaia" extension
name for AIA M-mode CSRs.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Rahul Pathak [Fri, 12 Aug 2022 13:54:42 +0000 (19:24 +0530)]
lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop
In case of missing "FENCE.TSO" instruction implementation,
opensbi can emulate the "FENCE.TSO" with "FENCE RW,RW", but
mepc was not incremented to continue from the next instruction
causing infinite trap.
Fixes:
cb8271c8 ("lib: sbi_illegal_insn: Add emulation for fence.tso")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Vivian Wang [Thu, 4 Aug 2022 14:32:31 +0000 (22:32 +0800)]
lib: sbi_trap: Set hstatus.GVA when going to HS-mode
The privileged spec specifies that on a trap to HS-mode, hstatus.GVA
should be set to 1 if stval is written with a guest virtual address, and
to 0 otherwise. Implement this by setting hstatus.GVA to trap->gva when
redirecting traps to HS-mode.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Thu, 4 Aug 2022 14:32:30 +0000 (22:32 +0800)]
lib: sbi_trap: Set hypervisor CSRs for HS-mode
The hypervisor CSRs hstatus, htval, htinst should always be set if the
trap is to be taken in HS-mode, regardless of which mode it came from.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Thu, 4 Aug 2022 14:32:29 +0000 (22:32 +0800)]
lib: sbi: Set gva when creating sbi_trap_info
In some cases the sbi_trap_info argument passed to sbi_trap_redirect is
created from scratch by filling its fields. Since we previously added a
gva field to struct sbi_trap_info, initialize gva in these cases also.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Thu, 4 Aug 2022 14:32:28 +0000 (22:32 +0800)]
lib: sbi_trap: Save mstatus[h].GVA in trap->gva
The machine mode GVA field is available if the hypervisor extension is
implemented, and indicates if mtval is a guest virtual address. Add a
gva field to sbi_trap_info for this, and in __sbi_expected_trap_hext,
save mstatus[h].GVA to it, so that gva indicates if tval is a guest
virtual address. If the hypervisor extension is not implemented, always
set gva to 0.
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Vivian Wang [Thu, 4 Aug 2022 14:32:27 +0000 (22:32 +0800)]
include: Add mstatus[h].GVA encodings
The machine mode GVA field is in mstatus for RV64 and mstatush for RV32,
and is available if the hypervisor extension is available. If an
exception occurs, we may need to redirect the trap to HS-mode, in which
case, hstatus.GVA should be set to same as the machine mode GVA bit.
Add MSTATUS_GVA for RV64, MSTATUSH_GVA for RV32, and their SHIFT
encodings. The SHIFT index is helpful in assembly code, since field
extraction can be implemented in only one register. In pseudocode:
- For RV32: gva = (mstatus >> MSTATUS_GVA_SHIFT) & 1;
- For RV64: gva = (mstatush >> MSTATUSH_GVA_SHIFT) & 1;
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Anup Patel [Mon, 8 Aug 2022 04:04:43 +0000 (09:34 +0530)]
Makefile: Fix typo related to object.mk
The "object.mk" name referred in top-level makefile should be
"objects.mk".
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:04:31 +0000 (09:34 +0530)]
docs: Update documentation for kconfig support
We update all documentation files to:
1) Remove references to platform specific config.mk file since it is
has been removed.
2) Add details about platform specific configs/defconfig and Kconfig
files mandatory for each platform.
3) Add required packages in top-level README.md
4) Fix typo releated to object.mk in docs/platform/platform.md
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:04:25 +0000 (09:34 +0530)]
platform: Remove redundant config.mk from all platforms
The options defined in config.mk can be specified in objects.mk of each
platform so let us remove config.mk from all platforms.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:04:20 +0000 (09:34 +0530)]
platform: generic: Use kconfig to set platform version and default name
The generic platform version and default name should be set based
on kconfig options so that users can override it.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:04:14 +0000 (09:34 +0530)]
platform: generic: Use kconfig for enabling/disabling overrides
We update generic platform to use kconfig for enabling/disabling
platform overrides. We also enable all platform overrides in generic
platform defconfig.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:04:08 +0000 (09:34 +0530)]
lib: utils/fdt: Use kconfig for enabling/disabling
We update FDT support makefile to use kconfig for enabling/disabling.
To avoid compilation errors, we also enable FDT for each platform.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:04:02 +0000 (09:34 +0530)]
lib: utils/gpio: Use kconfig for enabling/disabling drivers
We update gpio drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate gpio
drivers for each platform.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Anup Patel [Mon, 8 Aug 2022 04:03:57 +0000 (09:33 +0530)]
lib: utils/i2c: Use kconfig for enabling/disabling drivers
We update i2c drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate i2c
drivers for each platform.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>