Andy Wingo [Fri, 28 May 2021 10:42:12 +0000 (12:42 +0200)]
Revert "[WebAssembly][CodeGen] IR support for WebAssembly local variables"
This reverts commit
00ecf18979e3326b3afee8af3dc701c53ffdc93f, as it
broke the AMDGPU build. Will reland later with a fix.
Tim Northover [Wed, 10 Feb 2021 14:35:16 +0000 (14:35 +0000)]
SwiftTailCC: teach verifier musttail rules applicable to this CC.
SwiftTailCC has a different set of requirements than the C calling convention
for a tail call. The exact argument sequence doesn't have to match, but fewer
ABI-affecting attributes are allowed.
Also make sure the musttail diagnostic triggers if a musttail call isn't
actually a tail call.
Tim Northover [Mon, 1 Feb 2021 10:08:40 +0000 (10:08 +0000)]
ARM: support mandatory tail calls for tailcc & swifttailcc
This adds support for callee-pop conventions to the ARM backend so that it can
ensure a call marked "tail" is actually a tail call.
dongAxis [Fri, 28 May 2021 09:50:38 +0000 (17:50 +0800)]
[NFC][Transforms][Utils] remove useless variable in CloneBasicBlock
Florian Hahn [Fri, 28 May 2021 09:32:40 +0000 (10:32 +0100)]
Revert "[LAA] Support pointer phis in loop by analyzing each incoming pointer."
This reverts commit
1ed7f8ede564c3b11da4fdca30c36ccbff422576.
This change can cause loop-distribute to crash in some cases. Revert
until I have more time to wrap up a fix.
See PR50296, PR5028 and D102266.
Sebastian Neubauer [Thu, 27 May 2021 16:32:42 +0000 (18:32 +0200)]
[AMDGPU] Fix function calls with flat scratch
When flat scratch is used, the stack pointer needs to be added when
writing arguments to the stack.
For buffer instructions, this is done in SelectMUBUFScratchOffen
and SelectMUBUFScratchOffset.
Move that to call argument lowering, like it is done in GlobalISel.
Differential Revision: https://reviews.llvm.org/D103166
Sebastian Neubauer [Wed, 26 May 2021 12:29:04 +0000 (14:29 +0200)]
[AMDGPU] Precommit test
Add scratch run to gfx-callable-argument-types.ll.
Andy Wingo [Wed, 21 Apr 2021 13:41:48 +0000 (15:41 +0200)]
[WebAssembly][CodeGen] IR support for WebAssembly local variables
This patch adds TargetStackID::WasmLocal. This stack holds locations of
values that are only addressable by name -- not via a pointer to memory.
For the WebAssembly target, these objects are lowered to WebAssembly
local variables, which are managed by the WebAssembly run-time and are
not addressable by linear memory.
For the WebAssembly target IR indicates that an AllocaInst should be put
on TargetStackID::WasmLocal by putting it in the non-integral address
space WASM_ADDRESS_SPACE_WASM_VAR, with value 1. SROA will mostly lift
these allocations to SSA locals, but any alloca that reaches instruction
selection (usually in non-optimized builds) will be assigned the new
TargetStackID there. Loads and stores to those values are transformed
to new WebAssemblyISD::LOCAL_GET / WebAssemblyISD::LOCAL_SET nodes,
which then lower to the type-specific LOCAL_GET_I32 etc instructions via
tablegen patterns.
Differential Revision: https://reviews.llvm.org/D101140
Vitaly Buka [Fri, 28 May 2021 06:05:35 +0000 (23:05 -0700)]
[cmake][scudo] Add missing headers
Vitaly Buka [Fri, 28 May 2021 08:57:55 +0000 (01:57 -0700)]
[NFC][scudo] Re-enable check in the test
It should pass with patched QEMU.
Vitaly Buka [Fri, 28 May 2021 08:53:42 +0000 (01:53 -0700)]
Revert "[scudo] Check if MADV_DONTNEED zeroes memory"
This reverts commit
d423509b8036c29bbf94dab192d12097555ce0f8.
We are going to use patched QEMU.
Martin Storsjö [Thu, 20 May 2021 20:45:21 +0000 (23:45 +0300)]
[clang] [MinGW] Fix gcc version detection/picking
Actually compare each version to the version of the last chosen one.
There's no guarantee that the added test case does showcase the
previous issue (it depends on the order that directory entries
are returned when iterating), but with the issue fixed it should behave
deterministically in any case.
Also improve the match patterns in the mingw-sysroot.cpp test a bit.
Differential Revision: https://reviews.llvm.org/D102873
Yang Fan [Fri, 28 May 2021 08:15:12 +0000 (16:15 +0800)]
[ConstantFolding] Fix -Wunused-variable warning (NFC)
GCC warning:
```
/llvm-project/llvm/lib/Analysis/ConstantFolding.cpp: In function ‘llvm::Constant* llvm::ConstantFoldLoadFromConstPtr(llvm::Constant*, llvm::Type*, const llvm::DataLayout&)’:
/llvm-project/llvm/lib/Analysis/ConstantFolding.cpp:713:19: warning: unused variable ‘SimplifiedGEP’ [-Wunused-variable]
713 | if (auto *SimplifiedGEP = dyn_cast<GEPOperator>(Simplified)) {
| ^~~~~~~~~~~~~
```
eopXD [Fri, 28 May 2021 07:51:04 +0000 (07:51 +0000)]
Revert "[LoopNest][LoopFlatten] Change LoopFlattenPass to LoopNest pass"
This reverts commit
7952ddb21fb7e086d5a6f97767f235d2f6ae2176.
Differential Revision: https://reviews.llvm.org/D103302
eopXD [Fri, 28 May 2021 07:48:04 +0000 (07:48 +0000)]
Revert "[LoopNest][LoopFlatten] Change LoopFlattenPass to LoopNest pass"
This reverts commit
ffc4d3e06855550a8bd2a691f6d05828d5bf4ddf.
KareemErgawy [Fri, 28 May 2021 06:49:45 +0000 (08:49 +0200)]
[MLIR][SPIRV] Use getAsmResultName(...) hook for ConstantOp.
Implements better naming for results of `spv.Constant` ops by making it
inherit from OpAsmOpInterface and implementing the associated
getAsmResultName(...) hook.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D103152
eopXD [Fri, 28 May 2021 07:19:46 +0000 (07:19 +0000)]
[LoopNest][LoopFlatten] Change LoopFlattenPass to LoopNest pass
This patch changes LoopFlattenPass from FunctionPass to LoopNestPass.
Utilize LoopNest and let function 'Flatten' generate information from it.
Reviewed By: Whitney
Differential Revision: https://reviews.llvm.org/D102904
eopXD [Fri, 28 May 2021 06:58:10 +0000 (06:58 +0000)]
[LoopNest][LoopFlatten] Change LoopFlattenPass to LoopNest pass
This patch changes LoopFlattenPass from FunctionPass to LoopNestPass.
Utilize LoopNest and let function 'Flatten' generate information from it.
Reviewed By: Whitney
Differential Revision: https://reviews.llvm.org/D102904
Amara Emerson [Thu, 27 May 2021 06:28:44 +0000 (23:28 -0700)]
[AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources.
Also changes the fewerElements helper to use the lookthrough constant helper
instead of m_ICst, since m_ICst doesn't look through extends.
Differential Revision: https://reviews.llvm.org/D103227
Max Kazantsev [Fri, 28 May 2021 04:05:30 +0000 (11:05 +0700)]
Revert "[NFCI] Lazily evaluate SCEVs of PHIs"
This reverts commit
51d334a845a082338735b0fdfc620a4b15fa26fe.
Reported failures, need to analyze.
Reid Kleckner [Thu, 27 May 2021 21:32:48 +0000 (14:32 -0700)]
Pass -gcodeview-ghash when using clang-cl and lld-link
This precomputes some hashes that LLD uses for type merging to speed up
linking when PDBs are enabled. Only do this if any kind of /DEBUG flag
is passed to the linker. -gcodeview-ghash is orthogonal to /Z7, -g, -g1,
or -gmlt, so it is safe to set it independently from those flags. It
will not increase debug info emission.
Differential Revision: https://reviews.llvm.org/D103287
Zequan Wu [Thu, 27 May 2021 23:38:09 +0000 (16:38 -0700)]
[clang-cl] Bump default -fms-compatibility-version to 19.14
MSVC required version is 19.14 now (https://reviews.llvm.org/D92515). Update the
default -fms-compatibility-version to 19.14.
Differential Revision: https://reviews.llvm.org/D103293
Reid Kleckner [Fri, 28 May 2021 02:48:53 +0000 (19:48 -0700)]
[PDB] Fix ubsan complaint about memcpy from null pointer
Jinsong Ji [Fri, 28 May 2021 02:18:12 +0000 (02:18 +0000)]
[AIX] Enable stackprotect feature
AIX use `__ssp_canary_word` instead of `__stack_chk_guard`.
This patch update the target hook to use correct symbol,
so that the basic stackprotect feature can work.
The traceback will be handled in follow up patch.
Reviewed By: #powerpc, shchenz
Differential Revision: https://reviews.llvm.org/D103100
Jianzhou Zhao [Wed, 26 May 2021 22:51:54 +0000 (22:51 +0000)]
[dfsan] Add a flag about whether to propagate offset labels at gep
DFSan has flags to control flows between pointers and objects referred
by pointers. For example,
a = *p;
L(a) = L(*p) when -dfsan-combine-pointer-labels-on-load = false
L(a) = L(*p) + L(p) when -dfsan-combine-pointer-labels-on-load = true
*p = b;
L(*p) = L(b) when -dfsan-combine-pointer-labels-on-store = false
L(*p) = L(b) + L(p) when -dfsan-combine-pointer-labels-on-store = true
The question is what to do with p += c.
In practice we found many confusing flows if we propagate labels from c
to p. So a new flag works like this
p += c;
L(p) = L(p) when -dfsan-propagate-via-pointer-arithmetic = false
L(p) = L(p) + L(c) when -dfsan-propagate-via-pointer-arithmetic = true
Reviewed-by: gbalats
Differential Revision: https://reviews.llvm.org/D103176
Mehdi Amini [Fri, 28 May 2021 00:02:36 +0000 (00:02 +0000)]
Fix comment to reflect what the method is doing (NFC)
Jordan Rupprecht [Thu, 27 May 2021 23:48:40 +0000 (16:48 -0700)]
[NFC][libObject] clang-format Archive{.h,.cpp}
In preparation for D100651
Andrea Di Biagio [Thu, 27 May 2021 23:14:29 +0000 (00:14 +0100)]
[MCA] Minor changes to the InOrderIssueStage. NFC
The constructor of InOrderIssueStage no longer takes as input a reference to the
target scheduling model. The stage can always query the subtarget to obtain a
reference to the scheduling model.
The ResourceManager is no longer stored internally as a unique_ptr.
Moved a couple of method definitions to the .cpp file.
Arthur Eubanks [Thu, 22 Apr 2021 19:04:14 +0000 (12:04 -0700)]
[ConstFold] Simplify a load's GEP operand through local aliases
MSVC-style RTTI produces loads through a GEP of a local alias which
itself is a GEP. Currently we aren't able to devirtualize any virtual
calls when MSVC RTTI is enabled.
This patch attempts to simplify a load's GEP operand by calling
SymbolicallyEvaluateGEP() with an option to look through local aliases.
Differential Revision: https://reviews.llvm.org/D101100
Craig Topper [Thu, 27 May 2021 22:20:02 +0000 (15:20 -0700)]
[RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli.
If an instruction's AVL operand is a PHI node in the same block,
we may be able to peek through the PHI to find vsetvli instructions
that produce the AVL in other basic blocks. If we can prove those
vsetvli instructions have the same VTYPE and were the last vsetvli
in their respective blocks, then we don't need to insert a vsetvli
for this pseudo instruction.
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D103277
Arthur Eubanks [Thu, 27 May 2021 21:54:45 +0000 (14:54 -0700)]
[SanCov] Properly set ABI parameter attributes
Arguments need to have the proper ABI parameter attributes set.
Followup to D101806.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D103288
Roman Lebedev [Thu, 27 May 2021 21:57:15 +0000 (00:57 +0300)]
[NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes
Aart Bik [Thu, 27 May 2021 20:33:32 +0000 (13:33 -0700)]
[mlir][capi] fix build issue with "all passes" registration
Some builds exposed missing dependences on trafo/conv passes.
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D103283
Ryan Prichard [Thu, 27 May 2021 21:53:49 +0000 (14:53 -0700)]
[sanitizer] Android ELF TLS is supported from Q (API 29)
Reviewed By: oontvoo, MaskRay
Differential Revision: https://reviews.llvm.org/D103214
River Riddle [Thu, 27 May 2021 21:42:20 +0000 (14:42 -0700)]
[mlir-lsp-server] Add support for processing split files
MLIR tools very commonly use `// -----` to split a file into distinct sub documents, that are processed separately. This revision adds support to mlir-lsp-server for splitting MLIR files based on this sigil, and processing them separately.
Differential Revision: https://reviews.llvm.org/D102660
Andrea Di Biagio [Thu, 27 May 2021 20:50:57 +0000 (21:50 +0100)]
[MCA] Refactor the InOrderIssueStage stage. NFCI
Moved the logic that checks for RAW hazards from the InOrderIssueStage to the
RegisterFile.
Changed how the InOrderIssueStage keeps track of backend stalls. Stall events
are now generated from method notifyStallEvent().
No functional change intended.
Quinn Pham [Thu, 27 May 2021 18:35:12 +0000 (13:35 -0500)]
[PowerPC] Added multiple PowerPC builtins
This is the first in a series of patches to provide builtins for
compatibility with the XL compiler. Most of the builtins already had
intrinsics and only needed to be implemented in the front end.
Intrinsics were created for the three iospace builtins, eieio, and icbt.
Pseudo instructions were created for eieio and iospace_eieio to
ensure that nops were inserted before the eieio instruction.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D102443
Reid Kleckner [Thu, 20 May 2021 23:18:18 +0000 (16:18 -0700)]
[PDB] Enable parallel ghash type merging by default
Ghashing is probably going to be faster in most cases, even without
precomputed ghashes in object files.
Here is my table of results linking clang.pdb:
-------------------------------
| threads | GHASH | NOGHASH |
-------------------------------
| j1 | 51.031s | 25.141s |
| j2 | 31.079s | 22.109s |
| j4 | 18.609s | 23.156s |
| j8 | 11.938s | 21.984s |
| j28 | 8.375s | 18.391s |
-------------------------------
This shows that ghashing is faster if at least four cores are available.
This may make the linker slower if most cores are busy in the middle of
a build, but in that case, the linker probably isn't on the critical
path of the build. Incremental build performance is arguably more
important than highly contended batch build link performance.
The -time output indicates that ghash computation is the dominant
factor:
Input File Reading: 924 ms ( 1.8%)
GC: 689 ms ( 1.3%)
ICF: 527 ms ( 1.0%)
Code Layout: 414 ms ( 0.8%)
Commit Output File: 24 ms ( 0.0%)
PDB Emission (Cumulative): 49938 ms ( 94.8%)
Add Objects: 46783 ms ( 88.8%)
Global Type Hashing: 38983 ms ( 74.0%)
GHash Type Merging: 5640 ms ( 10.7%)
Symbol Merging: 2154 ms ( 4.1%)
Publics Stream Layout: 188 ms ( 0.4%)
TPI Stream Layout: 18 ms ( 0.0%)
Commit to Disk: 2818 ms ( 5.4%)
--------------------------------------------------
Total Link Time: 52669 ms (100.0%)
We can speed that up with a faster content hash (not SHA1).
Differential Revision: https://reviews.llvm.org/D102888
Craig Topper [Thu, 27 May 2021 21:04:44 +0000 (14:04 -0700)]
[RISCV] Fix typo, use addImm instead of addReg.
River Riddle [Thu, 27 May 2021 20:47:52 +0000 (13:47 -0700)]
[mlir] Add support for querying the ModRef behavior from the AliasAnalysis class
This allows for checking if a given operation may modify/reference/or both a given value. Right now this API is limited to Value based memory locations, but we should expand this to include attribute based values at some point. This is left for future work because the rest of the AliasAnalysis API also has this restriction.
Differential Revision: https://reviews.llvm.org/D101673
Martin Storsjö [Wed, 26 May 2021 10:22:23 +0000 (10:22 +0000)]
[libcxx] [test] Convert an XFAIL LIBCXX-WINDOWS-FIXME into UNSUPPORTED with explanation
Differential Revision: https://reviews.llvm.org/D103149
Martin Storsjö [Sat, 22 May 2021 22:47:04 +0000 (01:47 +0300)]
[clang] [MinGW] Don't mark emutls variables as DSO local
These actually can be automatically imported from another DLL. (This
works properly as long as the actual implementation of emutls is
linked dynamically from e.g. libgcc; if the implementation comes from
compiler-rt or a statically linked libgcc, it doesn't work as intended.)
This fixes PR50146 and https://github.com/msys2/MINGW-packages/issues/8706
(fixing calling std::call_once in a dynamically linked libstdc++);
since
f73183958482602c4588b0f4a1c3a096e7542947 the dso_local attribute
on the TLS variable affected the actual generated code for accessing
the emutls variable.
The dso_local attribute on the emutls variable made those accesses to
use 32 bit relative addressing in code, which requires runtime pseudo
relocations in the text section, and breaks entirely if the actual
other variable ends up loaded too far away in the virtual address
space.
Differential Revision: https://reviews.llvm.org/D102970
Louis Dionne [Thu, 27 May 2021 20:51:38 +0000 (16:51 -0400)]
[libc++] NFC: Make it easier for vendors to extend the run-buildbot script
Erich Keane [Thu, 27 May 2021 20:40:15 +0000 (13:40 -0700)]
Replace 'magic static' with a member variable for SCYL kernel names
I discovered when merging the __builtin_sycl_unique_stable_name into my
downstream that it is actually possible for the cc1 invocation to have
more than 1 Sema instance, if you pass it multiple input files, each
gets its own Sema instance and thus ASTContext instance. The result was
that the call to Filter the SYCL kernels was using an
ItaniumMangleContext stored via a 'magic static', so it had an invalid
reference to ASTContext when processing the 2nd failure.
The failure is unfortunately flakey/transient, but the test that fails
was added anyway.
The magic-static was switched to a unique_ptr member variable in
ASTContext that is initialized when needed.
Sanjay Patel [Thu, 27 May 2021 19:13:16 +0000 (15:13 -0400)]
[x86] add tests for extend of vector compare; NFC
Roman Lebedev [Thu, 27 May 2021 20:24:19 +0000 (23:24 +0300)]
[NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR
Now that i've reimplemented the testcase generator
to produce actual IR (https://godbolt.org/z/s7PM8E6v9),
it turns out that this was the only discrepancy
from what the LV would produce.
Adrian Prantl [Thu, 27 May 2021 01:23:02 +0000 (18:23 -0700)]
Support stripping indirectly referenced DILocations from !llvm.loop metadata
in stripDebugInfo(). This patch fixes an oversight in
https://reviews.llvm.org/D96181 and also takes into account loop
metadata pointing to other MDNodes that point into the debug info.
rdar://
78487175
Differential Revision: https://reviews.llvm.org/D103220
Georgeta Igna [Thu, 27 May 2021 19:25:49 +0000 (12:25 -0700)]
[analyzer] RetainCountChecker: Disable reference counting for OSMetaClass.
It is a reference-counted class but it uses different methods for that
and the checker doesn't understand them yet.
Differential Revision: https://reviews.llvm.org/D103081
Eugene Zhulenev [Thu, 27 May 2021 19:42:59 +0000 (12:42 -0700)]
[mlir:Async] Convert assertions to async errors only inside async functions
Differential Revision: https://reviews.llvm.org/D103278
Walter Erquinigo [Thu, 20 May 2021 19:41:09 +0000 (12:41 -0700)]
[lldb][intel-pt] Remove old plugin
Now that LLDB proper has built-in support for intel-pt traces, we can remove the old plugin written by Intel. It has less features and it's hard to work with.
As a test, I ran "ninja lldbIntelFeatures" and it worked.
Differential Revision: https://reviews.llvm.org/D102866
Craig Topper [Thu, 27 May 2021 18:28:19 +0000 (11:28 -0700)]
[RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop.
This is another case we need to look through a phi to prove.
Louis Dionne [Thu, 27 May 2021 18:22:38 +0000 (14:22 -0400)]
[libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup
The test would previously disable itself using `#if TEST_STD_VER` instead
of using UNSUPPORTED markup.
Vitaly Buka [Thu, 27 May 2021 17:02:47 +0000 (10:02 -0700)]
[NFC][scudo] Check zeros on smaller allocations
1Tb counting was the slowest test under the QEMU with MTE.
Jacques Pienaar [Thu, 27 May 2021 18:11:58 +0000 (11:11 -0700)]
[mlir] Update cmake variable post D102976
Eugene Zhulenev [Thu, 27 May 2021 17:47:21 +0000 (10:47 -0700)]
[mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr
Differential Revision: https://reviews.llvm.org/D103270
Saleem Abdulrasool [Thu, 27 May 2021 17:43:09 +0000 (10:43 -0700)]
MC: mark `dump` with `LLVM_DUMP_METHOD`
Mark the `ELFRelocationEntry::dump` method as `LLVM_DUMP_METHOD` to
annotate it properly as used to prevent the function being dead stripped
away. This allows use of `dump` in the debugger. This is purely to
improve the developer experience.
Vitaly Buka [Thu, 27 May 2021 16:49:34 +0000 (09:49 -0700)]
[NFC][scudo] Rename internal function
Louis Dionne [Thu, 27 May 2021 17:42:00 +0000 (13:42 -0400)]
Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11"
That fix was actually incorrect and caused tests to start failing.
Roman Lebedev [Thu, 27 May 2021 17:29:27 +0000 (20:29 +0300)]
[NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes
Simon Pilgrim [Thu, 27 May 2021 15:25:45 +0000 (16:25 +0100)]
[CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets
Determined from llvm-mca analysis (btver2 vs bdver2 vs sandybridge), the split+extends+concat sequence on AVX1 capable targets are cheaper than the #ops that the cost was previously based on.
Craig Topper [Thu, 27 May 2021 16:32:11 +0000 (09:32 -0700)]
[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.
This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0. For other register AVLs it can shorter the live
range of the AVL register if it isn't needed later.
There's probably no advantage when AVL is a 5 bit immediate that
can use vsetivli. But do it anyway for consistency.
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D103215
thomasraoux [Thu, 27 May 2021 16:26:06 +0000 (09:26 -0700)]
[mlir][NFC] Don't outline kernel in MMA integration tests
This matches better how other gpu integration tests are done.
Differential Revision: https://reviews.llvm.org/D103099
Eugene Zhulenev [Wed, 26 May 2021 20:33:38 +0000 (13:33 -0700)]
[mlir] Async: Add error propagation support to async groups
Depends On D103109
If any of the tokens/values added to the `!async.group` switches to the error state, than the group itself switches to the error state.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D103203
Craig Topper [Thu, 27 May 2021 15:31:57 +0000 (08:31 -0700)]
[X86] Fold (shift undef, X)->0 for vector shifts by immediate.
We could previously do this by accident through the later
call to getTargetConstantBitsFromNode I think, but that only worked
if N0 had a single use. This patch makes it explicit for undef and
doesn't have a use count check.
I think this is needed to move the (shl X, 1)->(add X, X)
fold to isel for PR50468. We need to be sure X won't be IMPLICIT_DEF
which might prevent the same vreg from being used for both operands.
Differential Revision: https://reviews.llvm.org/D103192
Craig Topper [Thu, 27 May 2021 15:21:07 +0000 (08:21 -0700)]
[X86] Pre-commit tests for D103192. NFC
Eugene Zhulenev [Tue, 25 May 2021 22:06:34 +0000 (15:06 -0700)]
[mlir] Add error state and error propagation to async runtime values
Depends On D103102
Not yet implemented:
1. Error handling after synchronous await
2. Error handling for async groups
Will be addressed in the followup PRs
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D103109
Marco Elver [Thu, 27 May 2021 16:24:21 +0000 (18:24 +0200)]
[Clang] Enable __has_feature(coverage_sanitizer)
Like other sanitizers, enable __has_feature(coverage_sanitizer) if clang
has enabled at least one SanitizerCoverage instrumentation type.
Because coverage instrumentation selection is not handled via normal
-fsanitize= (and thus not in SanitizeSet), passing this information
through to LangOptions required propagating the already parsed
-fsanitize-coverage= options from CodeGenOptions through to LangOptions
in FixupInvocation().
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D103159
Eugene Zhulenev [Tue, 25 May 2021 18:02:42 +0000 (11:02 -0700)]
[mlir] Async reference counting for block successors with divergent reference counted liveness
Support reference counted values implicitly passed (live) only to some of the successors.
Example: if branched to ^bb2 token will leak, unless `drop_ref` operation is properly created
```
^entry:
%token = async.runtime.create : !async.token
cond_br %cond, ^bb1, ^bb2
^bb1:
async.runtime.await %token
async.runtime.drop_ref %token
br ^bb2
^bb2:
return
```
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D103102
maekawatoshiki [Thu, 27 May 2021 16:17:23 +0000 (01:17 +0900)]
[LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass
This patch changes LoopUnrollAndJamPass from FunctionPass to LoopNest pass.
The next patch will utilize LoopNest to effectively handle loop nests.
Reviewed By: Whitney
Differential Revision: https://reviews.llvm.org/D99149
Qiu Chaofan [Thu, 27 May 2021 16:10:04 +0000 (00:10 +0800)]
[SPE] Disable strict-fp for SPE by default
As discussed in PR50385, strict-fp on PowerPC SPE has not been handled
well. This patch disables it by default for SPE.
Reviewed By: nemanjai, vit9696, jhibbits
Differential Revision: https://reviews.llvm.org/D103235
thomasraoux [Thu, 27 May 2021 15:58:11 +0000 (08:58 -0700)]
[mlir][gpu] Relax restriction on MMA store op to allow chain of mma ops.
In order to allow large matmul operations using the MMA ops we need to chain
operations this is not possible unless "DOp" and "COp" type have matching
layout so remove the "DOp" layout and force accumulator and result type to
match.
Added a test for the case where the MMA value is accumulated.
Differential Revision: https://reviews.llvm.org/D103023
Yaxun (Sam) Liu [Sun, 23 May 2021 03:45:15 +0000 (23:45 -0400)]
[HIP] Check compatibility of -fgpu-sanitize with offload arch
-fgpu-sanitize is incompatible with offload arch containing xnack-.
This patch checks that.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D102975
Fraser Cormack [Thu, 27 May 2021 15:54:42 +0000 (16:54 +0100)]
[RISCV] Add a test case showing incorrect call-conv lowering
@HsiangKai helped find a bug in the lowering of indirect split
scalable-vector types in our calling convention. An imminent patch will
fix this.
Matt Arsenault [Tue, 18 May 2021 21:05:49 +0000 (17:05 -0400)]
GlobalISel: Do not change register types in lowerLoad
Adjusting the load register type is a widenScalar type action, not a
lowering. lowerLoad should be reserved for operations that change the
memory access size, such as unaligned load decomposition. With this
trying to adjust the register type, it was hard to avoid infinite
loops in the legalizer. Adds a bandaid to avoid regressing a few
AArch64 tests, but I'm not sure what the exact condition is and
there's probably a cleaner way to do this.
For AMDGPU this regresses handling of some cases for unaligned loads,
but the way this is currently working is a pretty ugly hack.
jasonliu [Thu, 27 May 2021 15:47:20 +0000 (15:47 +0000)]
[AIX] Add -lc++abi and -lunwind for linking
Summary:
We are going to have libc++abi.a and libunwind.a on AIX.
Add the necessary linking command to pick the libraries up.
Reviewed By: daltenty
Differential Revision: https://reviews.llvm.org/D102813
Aaron Puchert [Thu, 27 May 2021 15:45:59 +0000 (17:45 +0200)]
Thread safety analysis: Allow exlusive/shared joins for managed and asserted capabilities
Similar to how we allow managed and asserted locks to be held and not
held in joining branches, we also allow them to be held shared and
exclusive. The scoped lock should restore the original state at the end
of the scope in any event, and asserted locks need not be released.
We should probably only allow asserted locks to be subsumed by managed,
not by (directly) acquired locks, but that's for another change.
Reviewed By: delesley
Differential Revision: https://reviews.llvm.org/D102026
Aaron Puchert [Thu, 27 May 2021 15:44:43 +0000 (17:44 +0200)]
Thread safety analysis: Factor out function for merging locks (NFC)
It's going to become a bit more complicated, so let's have it separate.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D102025
Nico Weber [Thu, 27 May 2021 15:40:51 +0000 (11:40 -0400)]
Revert "Emit correct location lists with basic block sections."
Breaks check-llvm on non-linux, see comments on https://reviews.llvm.org/D85085
This reverts commit
caae570978c490a137921b9516162a382831209e
and follow-up commit
1546c52d971292ed4145b6d41aaca0d02229ebff.
Louis Dionne [Thu, 27 May 2021 15:41:26 +0000 (11:41 -0400)]
[libc++] NFC: Parenthesize expression to satisfy GCC 11
Otherwise it issues a -Werror=parentheses suggesting parentheses.
Louis Dionne [Tue, 25 May 2021 22:15:58 +0000 (18:15 -0400)]
[libc++] Deprecate std::iterator and remove it as a base class
C++17 deprecated std::iterator and removed it as a base class for all
iterator adaptors. We implement that change, but we still provide a way
to inherit from std::iterator in the few cases where doing otherwise
would be an ABI break.
Supersedes D101729 and the std::iterator base parts of D103101 and D102657.
Differential Revision: https://reviews.llvm.org/D103171
Matt Arsenault [Tue, 25 May 2021 20:25:34 +0000 (16:25 -0400)]
AMDGPU/GlobalISel: Use IncomingValueAssigner for implicit return
This makes no real difference since we assign the same register either
way.
Matt Arsenault [Fri, 21 May 2021 00:50:34 +0000 (20:50 -0400)]
AMDGPU/GlobalISel: Fix broken test run line
Simon Pilgrim [Thu, 27 May 2021 14:36:29 +0000 (15:36 +0100)]
[CostModel][X86] AVX512 truncation ops are slower than cost models indicate.
The SkylakeServer model (and later IceLake/TigerLake targets according to Agner) have the PMOV truncations as uops=2, rthroughput=2 instructions.
Noticed while trying to reduce the diffs between cost tables and llvm-mca analysis.
Simon Pilgrim [Wed, 26 May 2021 16:42:22 +0000 (17:42 +0100)]
[X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads
Sven van Haastregt [Thu, 27 May 2021 15:06:33 +0000 (16:06 +0100)]
[OpenCL][NFC] Fix typos in test
Isaac Perry [Thu, 27 May 2021 07:56:16 +0000 (08:56 +0100)]
[Flang][Openmp] Fortran specific semantic checks for Allocate directive
This patch adds the following Fortran specific semantic checks for the OpenMP
Allocate directive.
1) A type parameter inquiry cannot appear in an ALLOCATE directive.
2) List items specified in the ALLOCATE directive must not have the ALLOCATABLE
attribute unless the directive is associated with an ALLOCATE statement.
Co-authored-by: Irina Dobrescu <irina.dobrescu@arm.com>
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D102061
Matt Arsenault [Mon, 29 Oct 2018 22:55:33 +0000 (18:55 -0400)]
VirtRegMap: Preserve LiveDebugVariables
This avoids recomputing it between regalloc runs when allocation is
split, and also avoids a debug info test regression.
Aaron Ballman [Thu, 27 May 2021 14:37:33 +0000 (10:37 -0400)]
Disable misc-no-recursion checking in Clang
We currently enable misc-no-recursion, but Clang uses recursion
intentionally in a fair number of places (like RecursiveASTVisitor).
Disabling this check reduces a noise in reviews that add new AST nodes,
like https://reviews.llvm.org/D103112#2780747 which has five CI
warnings that the author can do nothing about.
Fraser Cormack [Mon, 24 May 2021 14:24:54 +0000 (15:24 +0100)]
[VP][SelectionDAG] Add a target-configurable EVL operand type
This patch adds a way for the target to configure the type it uses for
the explicit vector length operands of VP SDNodes. The type must be a
legal integer type (there is still no target-independent legalization of
this operand) and must currently be at least as big as i32, the type
used by the IR intrinsics. An implicit zero-extension takes place on
targets which choose a larger type. All VP nodes should be created with
this type used for the EVL operand.
This allows 64-bit RISC-V to avoid custom legalization of all VP nodes,
keeping them in their target-independent form for that bit longer.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D103027
Mats Petersson [Fri, 30 Apr 2021 13:13:55 +0000 (14:13 +0100)]
[OpenMP]Add support for workshare loop modifier in lowering
When lowering the dynamic, guided, auto and runtime types of scheduling,
there is an optional monotonic or non-monotonic modifier. This patch
adds support in the OMP IR Builder to pass this down to the runtime
functions.
Also implements tests for the variants.
Differential Revision: https://reviews.llvm.org/D102008
Aaron Ballman [Thu, 27 May 2021 14:25:39 +0000 (10:25 -0400)]
Hopefully fix the Clang sphinx doc build.
This was broken several days ago in
826905787ae4c8540bb8a2384fac59c606c7eaff.
Erich Keane [Thu, 27 May 2021 14:19:20 +0000 (07:19 -0700)]
Correct the 'KEYALL' mask.
It should technically be a 1, since we are only setting the first bit.
Jamie Schmeiser [Thu, 27 May 2021 14:19:13 +0000 (10:19 -0400)]
Reuse temporary files for print-changed=diff
Summary:
Make the file name and descriptors static so that they are reused by
print-changed=diff. This avoids errors about being unable to create
temporary files when doing the later comparisons in a large compile.
Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: aeubanks (Arthur Eubanks)
Differential Revision: https://reviews.llvm.org/D100116
Erich Keane [Fri, 23 Apr 2021 15:22:35 +0000 (08:22 -0700)]
Reimplement __builtin_unique_stable_name-
The original version of this was reverted, and @rjmcall provided some
advice to architect a new solution. This is that solution.
This implements a builtin to provide a unique name that is stable across
compilations of this TU for the purposes of implementing the library
component of the unnamed kernel feature of SYCL. It does this by
running the Itanium mangler with a few modifications.
Because it is somewhat common to wrap non-kernel-related lambdas in
macros that aren't present on the device (such as for logging), this
uniquely generates an ID for all lambdas involved in the naming of a
kernel. It uses the lambda-mangling number to do this, except replaces
this with its own number (starting at 10000 for readabililty reasons)
for lambdas used to name a kernel.
Additionally, this implements itself as constexpr with a slight catch:
if a name would be invalidated by the use of this lambda in a later
kernel invocation, it is diagnosed as an error (see the Sema tests).
Differential Revision: https://reviews.llvm.org/D103112
Aaron Ballman [Thu, 27 May 2021 13:54:09 +0000 (09:54 -0400)]
Speculatively fix this harder and with improved spelling capabilities.
Aaron Ballman [Thu, 27 May 2021 13:48:43 +0000 (09:48 -0400)]
Speculatively fix a -Woverloaded-virtual diagnostic; NFC
Matt Arsenault [Tue, 18 May 2021 22:22:09 +0000 (18:22 -0400)]
AMDGPU/GlobalISel: Lower constant-32-bit zextload/sextload consistently
We were accidentally leaning on code in lowerLoad which expands
extending loads which should be removed.
Matt Arsenault [Tue, 18 May 2021 21:02:25 +0000 (17:02 -0400)]
AMDGPU/GlobalISel: Remove redundant parameter from function
Aaron Ballman [Thu, 27 May 2021 13:23:20 +0000 (09:23 -0400)]
Fix -Wswitch warning; NFC
Fraser Cormack [Wed, 26 May 2021 15:04:59 +0000 (16:04 +0100)]
[DAGCombine][RISCV] Don't try to trunc-store combined vector stores
DAGCombine's `mergeStoresOfConstantsOrVecElts` optimization is told
whether it's to use vector types and also whether it's to issue a
truncating store. However, the truncating store code path assumes a
scalar integer `ConstantSDNode`, and when using vector types it creates
either a `BUILD_VECTOR` or `CONCAT_VECTORS` to store: neither of which
is a constant.
The `riscv64` target is able to expose a crash here because it switches
on both code paths at the same time. The `f32` is stored as `i32` which
must be promoted to `i64`, necessitating a truncating store.
It also decides later that it prefers a vector store of `v2f32`.
While vector truncating stores are legal, this combine is not able to
emit them. We also don't have a test case. This patch adds an assert to
catch this case more gracefully, and updates one of the caller functions
to the function to turn off the use of truncating stores when preferring
vectors.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D103173