Aart Bik [Tue, 11 May 2021 23:14:00 +0000 (16:14 -0700)]
[mlir][sparse] keep runtime support library signature consistent
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D102285
Amara Emerson [Wed, 12 May 2021 08:04:55 +0000 (01:04 -0700)]
[AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting.
This caused performance regressions vs SDAG on SingleSource/Benchmarks/Adobe-C++
Greg McGary [Tue, 30 Mar 2021 00:33:48 +0000 (17:33 -0700)]
[lld-macho] Implement branch-range-extension thunks
Extend the range of calls beyond an architecture's limited branch range by first calling a thunk, which loads the far address into a scratch register (x16 on ARM64) and branches through it.
Other ports (COFF, ELF) use multiple passes with successively-refined guesses regarding the expansion of text-space imposed by thunk-space overhead. This MachO algorithm places thunks during MergedOutputSection::finalize() in a single pass using exact thunk-space overheads. Thunks are kept in a separate vector to avoid the overhead of inserting into the `inputs` vector of `MergedOutputSection`.
FIXME:
* arm64-stubs.s test is broken
* add thunk tests
* Handle thunks to DylibSymbol in MergedOutputSection::finalize()
Differential Revision: https://reviews.llvm.org/D100818
Jon Chesterfield [Wed, 12 May 2021 16:30:40 +0000 (17:30 +0100)]
[libomptarget][amdgpu][nfc] Expand errorcheck macros
[libomptarget][amdgpu][nfc] Expand errorcheck macros
These macros expand to continue, which is confusing, or exit,
which is incompatible with continuing execution on offloading fail.
Expanding the macros in place makes the code look untidy but the
control flow obvious and amenable to improving. In particular, exit
becomes easier to eliminate.
Reviewed By: pdhaliwal
Differential Revision: https://reviews.llvm.org/D102230
Abhina Sreeskantharajan [Wed, 12 May 2021 16:26:00 +0000 (12:26 -0400)]
[SystemZ][z/OS] Fix warning caused by umask returning a signed integer type
On z/OS, umask() returns an int because mode_t is type int, however it is being compared to an unsigned int. This patch fixes the following warning we see when compiling Path.cpp.
```
comparison of integers of different signs: 'const int' and 'const unsigned int'
```
Reviewed By: muiez
Differential Revision: https://reviews.llvm.org/D102326
Malcolm Parsons [Wed, 12 May 2021 16:11:19 +0000 (17:11 +0100)]
[docs] Fix documentation for bugprone-dangling-handle
string_view isn't experimental anymore.
This check has always handled both forms.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D102313
Fabian Schuiki [Wed, 21 Apr 2021 08:57:29 +0000 (10:57 +0200)]
[MLIR] Factor pass timing out into a dedicated timing manager
This factors out the pass timing code into a separate `TimingManager`
that can be plugged into the `PassManager` from the outside. Users are
able to provide their own implementation of this manager, and use it to
time additional code paths outside of the pass manager. Also allows for
multiple `PassManager`s to run and contribute to a single timing report.
More specifically, moves most of the existing infrastructure in
`Pass/PassTiming.cpp` into a new `Support/Timing.cpp` file and adds a
public interface in `Support/Timing.h`. The `PassTiming` instrumentation
becomes a wrapper around the new timing infrastructure which adapts the
instrumentation callbacks to the new timers.
Reviewed By: rriddle, lattner
Differential Revision: https://reviews.llvm.org/D100647
Victor Huang [Wed, 12 May 2021 15:56:54 +0000 (10:56 -0500)]
[PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td
Baptiste Saleil [Wed, 12 May 2021 15:37:06 +0000 (11:37 -0400)]
[AMDGPU] Disable the SIFormMemoryClauses pass at -O1
This patch disables the SIFormMemoryClauses pass at -O1. This pass has a
significant impact on compilation time, so we only want it to be enabled
starting from -O2.
Differential Revision: https://reviews.llvm.org/D101939
Paul Robinson [Wed, 12 May 2021 15:48:50 +0000 (08:48 -0700)]
Fix grammar in README.md
Simon Pilgrim [Wed, 12 May 2021 15:25:08 +0000 (16:25 +0100)]
[X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI.
Pull out repeated code to create a concat_vectors of the same operand from all subvecs.
Simon Pilgrim [Wed, 12 May 2021 14:46:52 +0000 (15:46 +0100)]
[X86][AVX] Add v4i64 shift-by-32 tests
AVX1 could perform this as a v8f32 shuffle instead of splitting - based off PR46621
Fraser Cormack [Fri, 7 May 2021 14:25:40 +0000 (15:25 +0100)]
[TargetLowering] Improve legalization of scalable vector types
This patch extends the vector type-conversion and legalization capabilities of
scalable vector types.
Firstly, `vscale x 1` types now behave more like the corresponding `vscale x
2+` types. This enables the integer promotion legalization of extended scalable
types, such as the promotion of `<vscale x 1 x i5>` to `<vscale x 1 x i8>`.
These `vscale x 1` types are also now better handled by
`getVectorTypeBreakdown`, where what looks like older handling for 1-element
fixed-length vector types was spuriously updated to include scalable types.
Widening of scalable types is now better supported, by using `INSERT_SUBVECTOR`
to insert the smaller scalable vector "value" type into the wider scalable
vector "part" type. This allows AArch64 to pass and return `vscale x 1` types
by value by widening.
There are still cases where we are unable to legalize `vscale x 1` types, such
as where expansion would require splitting the vector in two.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D102073
Valentin Clement [Wed, 12 May 2021 15:31:18 +0000 (11:31 -0400)]
[mlir][openacc] Conversion of data operand to LLVM IR dialect
Add a conversion pass to convert higher-level type before translation.
This conversion extract meangingful information and pack it into a struct that
the translation (D101504) will be able to understand.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D102170
Anastasia Stulova [Wed, 12 May 2021 15:19:13 +0000 (16:19 +0100)]
[OpenCL] Remove pragma requirement from Arm dot extension.
This removed the pointless need for extension pragma since
it doesn't disable anything properly and it doesn't need to
enable anything that is not possible to disable.
The change doesn't break existing kernels since it allows to
compile more cases i.e. without pragma statements but the
pragma continues to be accepted.
Differential Revision: https://reviews.llvm.org/D100985
Jordan Rupprecht [Wed, 12 May 2021 01:36:53 +0000 (18:36 -0700)]
[llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility.
Much like other LLVM binary utilities, `llvm-cov` has a symlink compatibility feature where it runs in `gcov` compatibility mode if the binary name ends in `gcov`. This is identical to invoking `llvm-cov gcov ...`.
Differential Revision: https://reviews.llvm.org/D102299
Yaxun (Sam) Liu [Tue, 11 May 2021 14:09:38 +0000 (10:09 -0400)]
[CUDA][HIP] Fix device template variables
Currently clang does not emit device template variables
instantiated only in host functions, however, nvcc is
able to do that:
https://godbolt.org/z/fneEfferY
This patch fixes this issue by refactoring and extending
the existing mechanism for emitting static device
var ODR-used by host only. Basically clang records
device variables ODR-used by host code and force
them to be emitted in device compilation. The existing
mechanism makes sure these device variables ODR-used
by host code are added to llvm.compiler-used, therefore
they are guaranteed not to be deleted.
It also fixes non-ODR-use of static device variable by host code
causing static device variable to be emitted and registered,
which should not.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D102237
Craig Topper [Wed, 12 May 2021 14:27:52 +0000 (07:27 -0700)]
[ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements()
getVectorNumElements() returns a value for scalable vectors
without any warning so it is effectively getVectorMinNumElements().
By renaming it and making getVectorNumElements() forward to
it, we can insert a check for scalable vectors into getVectorNumElements()
similar to EVT. I didn't do that in this patch because there are still more
fixes needed, but I was able to temporarily do it and passed the RISCV
lit tests with these changes.
The changes to isPow2VectorType and getPow2VectorType are copied from EVT.
The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table.
We're now considering SameNumElts to require the scalable property to match which
removes some unneeded type checks.
This was motivated by the bug I fixed yesterday in
80b9510806cf11c57f2dd87191d3989fc45defa8
Reviewed By: frasercrmck, sdesmalen
Differential Revision: https://reviews.llvm.org/D102262
Stefan Pintilie [Wed, 12 May 2021 14:42:09 +0000 (09:42 -0500)]
Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"
This reverts commit
6c80361b8474535852afb2f7201370fb5f410091.
Breaks PowerPC Big Endian buildbots.
Hendrik Greving [Tue, 11 May 2021 15:57:18 +0000 (08:57 -0700)]
[DAGCombiner] Fix DAG combine store elimination, different address space.
Fixes a bug in the DAG combiner that eliminates the stores because it missed
to inspect the address space of the pointers.
%v = load %ptr_as1
// no chain side effect
store %v, %ptr_as2
As well as
store %v, %ptr_as1
store %v, %ptr_as2
Fixes a test for above in X86.
Differential Revision: https://reviews.llvm.org/D102096
Hendrik Greving [Tue, 11 May 2021 14:16:35 +0000 (07:16 -0700)]
[DAGCombiner] Add test exposing bug in DAG combine.
Adds a test in X86, exposing a bug in DAG combine eliminating stores that
are the same value but no the same address space.
Differential Revision: https://reviews.llvm.org/D102243
Peter Waller [Tue, 27 Apr 2021 12:29:42 +0000 (12:29 +0000)]
[CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr
When a ptest is used to set flags from the output of rdffr, the ptest
can be eliminated, using a flags-setting rdffrs instead.
Additionally, check that nothing consumes flags between rdffr and ptest;
this case appears to have been missed previously.
* There is no unpredicated RDFFRS instruction.
* If substituting RDFFR_PP, require that the mask argument of the
PTEST matches that of the RDFFR_PP.
* Move some precondition code up inside optimizePTestInstr, so that it
covers the new code paths for RDFFR which return earlier.
* Only consider RDFFR, PTEST in same basic block.
* Check for other flag setting instructions between the two, abort if
found.
* Drop an old TODO comment about removing dead PTEST instructions.
RDFFR_P to follow in later patch.
Differential Revision: https://reviews.llvm.org/D101357
Ben Shi [Wed, 12 May 2021 14:01:28 +0000 (22:01 +0800)]
[clang][AVR] Redefine some types to be compatible with avr-gcc
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D100701
David Sherwood [Wed, 12 May 2021 13:49:04 +0000 (14:49 +0100)]
[NFC] Use variable GEP index in vec_demanded_elts tests
I've changed a test in each of these files:
Transforms/InstCombine/vec_demanded_elts.ll
Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
to use a variable GEP index instead of a constant value so that
we're testing the more general case.
Martin Storsjö [Wed, 12 May 2021 09:03:54 +0000 (12:03 +0300)]
[Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64
The bug (PR50227, affecting COFF) that caused the revert in
6f5670a4c3d8c079d4b676140ee69e5cc235d5a8 has been fixed in
382c505d9cfca8adaec47aea2da7bbcbc00fc05c now, so it should be safe
to reenable the pass for that target (and ELF).
In PR50227 it's also mentioned that the same pass seems to cause
problems on aarch64 on darwin, so leaving it disabled there for now.
Greg McGary [Mon, 3 May 2021 02:08:02 +0000 (19:08 -0700)]
[llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly
`__mh_(execute|dylib|dylinker|bundle|preload|object)_header` are special symbols whose values hold the VMA of the Mach header to support introspection. They are attached to the first section in `__TEXT`, even though their addresses are outside `__TEXT`, and they do not refer to code.
It is normally harmless, but when the first section of `__TEXT` has no other symbols, `__mh_*_header` is considered by the disassembler when determing function boundaries. Since `__mh_*_header` refers to an address outside `__TEXT`, the boundary determination fails and disassembly quits.
Since `__TEXT,__text` normally has symbols, this bug is obscured. Experiments placing `__stubs` and `__stub_helper` first exposed the bug, since neither has symbols.
Differential Revision: https://reviews.llvm.org/D101786
Julien Pagès [Wed, 12 May 2021 13:14:56 +0000 (14:14 +0100)]
[AMDGPU] Improve Codegen for build_vector
Improve the code generation of build_vector.
Use the v_pack_b32_f16 instruction instead of
v_and_b32 + v_lshl_or_b32
Differential Revision: https://reviews.llvm.org/D98081
Patch by Julien Pagès!
Roman Lebedev [Wed, 12 May 2021 13:09:37 +0000 (16:09 +0300)]
[InstCombine] ~(C + X) --> ~C - X (PR50308)
We can not rely on (C+X)-->(X+C) already happening,
because we might not have visited that `add` yet.
The added testcase would get stuck in an endless combine loop.
Jay Foad [Tue, 11 May 2021 14:14:04 +0000 (15:14 +0100)]
[TargetRegisterInfo] Speed up getAllocatableSet. NFCI.
MachineRegisterInfo caches the reserved register set that is computed by
by TargetRegisterInfo::getReservedRegs, so call into MRI to get the
reserved regs to avoid recomputing them.
In particular this speeds up AMDGPU's SIFormMemoryClauses pass because
AMDGPU has a particularly complicated reserved set that is expensive to
compute.
Differential Revision: https://reviews.llvm.org/D102318
Tobias Gysi [Wed, 12 May 2021 12:43:34 +0000 (12:43 +0000)]
[mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).
Differential Revision: https://reviews.llvm.org/D102245
Piotr Sobczak [Wed, 12 May 2021 12:52:02 +0000 (14:52 +0200)]
[AMDGPU] Remove assert
Remove assert introduced in D101177, following post-commit feedback.
Sanjay Patel [Wed, 12 May 2021 12:03:11 +0000 (08:03 -0400)]
[x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ
This is motivated by the example in https://llvm.org/PR50055 ,
but it doesn't do anything for that bug currently because we
don't actually have a zero-extended setcc there.
Proof for the generic transform (inverse of what we would
try to do in combining):
https://alive2.llvm.org/ce/z/aBL-Mg
Differential Revision: https://reviews.llvm.org/D102275
Sanjay Patel [Tue, 11 May 2021 19:52:43 +0000 (15:52 -0400)]
[x86] add test for pcmpeq with 0; NFC
Nathan James [Wed, 12 May 2021 12:18:40 +0000 (13:18 +0100)]
[clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers
There should be a follow up to this for changing the traversal mode, but some of the tests don't like that.
Reviewed By: steveire
Differential Revision: https://reviews.llvm.org/D101614
Tobias Gysi [Wed, 12 May 2021 12:00:08 +0000 (12:00 +0000)]
[mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).
Differential Revision: https://reviews.llvm.org/D102308
David Spickett [Wed, 12 May 2021 12:12:28 +0000 (13:12 +0100)]
Revert "[scudo] Enable arm32 arch"
This reverts commit
b1a77e465e37fc400c16f9fda2a637f11c698bb9.
Which has a failing test on our armv7 bots:
https://lab.llvm.org/buildbot/#/builders/59/builds/1812
Hana Joo [Wed, 12 May 2021 11:57:17 +0000 (12:57 +0100)]
[clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule
The `IgnoreArray` flag was not used before while running the rule. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=47288 | b/47288 ]]
Reviewed By: njames93
Differential Revision: https://reviews.llvm.org/D101239
Tobias Gysi [Wed, 12 May 2021 11:34:13 +0000 (11:34 +0000)]
[mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).
Differential Revision: https://reviews.llvm.org/D102236
Kristina Bessonova [Sun, 9 May 2021 17:29:56 +0000 (19:29 +0200)]
[libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages
Differential Revision: https://reviews.llvm.org/D102195
Simon Pilgrim [Wed, 12 May 2021 11:02:06 +0000 (12:02 +0100)]
[X86][AVX] canonicalizeShuffleMaskWithHorizOp - improve support for 256/512-bit vectors
Extend the HOP(HOP(X,Y),HOP(Z,W)) and SHUFFLE(HOP(X,Y),HOP(Z,W)) folds to handle repeating 256/512-bit vector cases.
This allows us to drop the UNPACK(HOP(),HOP()) custom fold in combineTargetShuffle.
This required isRepeatedTargetShuffleMask to be tweaked to support target shuffle masks taking more than 2 inputs.
gbreynoo [Wed, 12 May 2021 11:09:08 +0000 (12:09 +0100)]
[llvm-readelf] Unhide short options to match the command guide
The readelf command guide shows the short options used as aliases but
these are not found in the help text unless --show-hidden is used, other
tools show aliases with --help. This change fixes the help output to be
consistent with the command guide.
Differential Revision: https://reviews.llvm.org/D102173
gbreynoo [Wed, 12 May 2021 11:04:54 +0000 (12:04 +0100)]
[llvm-symbolizer] Place Mach-O options into the Mach-O option group.
In the help output of other tools and in the symbolizer command guide,
Mach-O specific options are in their own section. This change fixes the
symbolizer help output to be consistent.
Differential Revision: https://reviews.llvm.org/D102178
David Sherwood [Wed, 21 Apr 2021 15:36:11 +0000 (16:36 +0100)]
[LoopVectorize] Fix scalarisation crash in widenPHIInstruction for scalable vectors
In InnerLoopVectorizer::widenPHIInstruction there are cases where we have
to scalarise a pointer induction variable after vectorisation. For scalable
vectors we already deal with the case where the pointer induction variable
is uniform, but we currently crash if not uniform. For fixed width vectors
we calculate every lane of the scalarised pointer induction variable for a
given VF, however this cannot work for scalable vectors. In this case I
have added support for caching the whole vector value for each unrolled
part so that we can always extract an arbitrary element. Additionally, we
still continue to cache the known minimum number of lanes too in order
to improve code quality by avoiding an extractelement operation.
I have adapted an existing test `pointer_iv_mixed` from the file:
Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
and added it here for scalable vectors instead:
Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
Differential Revision: https://reviews.llvm.org/D101294
Peter Waller [Thu, 29 Apr 2021 15:40:34 +0000 (15:40 +0000)]
[AArch64][SVE] Improve sve.convert.to.svbool lowering
The sve.convert.to.svbool lowering has the effect of widening a logical
<M x i1> vector representing lanes into a physical <16 x i1> vector
representing bits in a predicate register.
In general, if converting to svbool, the contents of lanes in the
physical register might not be known. For sve.convert.to.svbool the new
lanes are specified to be zeroed, requiring 'and' instructions to mask
off the new lanes. For lanes coming from a ptrue or a comparison,
however, they are known to be zero.
CodeGen Before:
ptrue p0.s, vl16
ptrue p1.s
ptrue p2.b
and p0.b, p2/z, p0.b, p1.b
ret
After:
ptrue p0.s, vl16
ret
Differential Revision: https://reviews.llvm.org/D101544
Michał Górny [Wed, 5 May 2021 11:06:55 +0000 (13:06 +0200)]
[Process/elf-core] Read PID from FreeBSD prpsinfo
Add a function to read NT_PRPSINFO note from FreeBSD core dumps. This
is necessary to get the process ID (NT_PRSTATUS has only thread ID).
Move the lp64 check from NT_PRSTATUS parsing to the parseFreeBSDNotes()
to avoid repeating it.
Differential Revision: https://reviews.llvm.org/D101893
Michał Górny [Thu, 22 Apr 2021 17:21:50 +0000 (19:21 +0200)]
[lldb] [Process/elf-core] Fix reading FPRs from FreeBSD/i386 cores
The FreeBSD coredumps from i386 systems contain only FSAVE-style
NT_FPREGSET. Since we do not really support reading that kind of data
anymore, just use NT_X86_XSTATE to get FXSAVE-style data when available.
Differential Revision: https://reviews.llvm.org/D101086
Stephen Tozer [Mon, 10 May 2021 13:00:01 +0000 (14:00 +0100)]
Reapply "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST"
Previous crashes caused by this patch were the result of machine
subregisters being incorrectly handled in updateDbgUsersToReg; this has
been fixed by using RegUnits to determine overlapping registers, instead
of using the register values directly.
Differential Revision: https://reviews.llvm.org/D101523
This reverts commit
7ca26c5fa2df253878cab22e1e2f0d6f1b481218.
Neal (nealsid) [Wed, 12 May 2021 08:46:35 +0000 (09:46 +0100)]
Remove Windows editline from LLDB
I don't mean to undo others' work but it looks like the hand-rolled EditLine for LLDB on Windows isn't used. It'd be easier to make changes to bring the other platforms' Editline wrapper up to date (e.g. simplifying char vs wchar_t) without modifying/testing this one too.
Reviewed By: amccarth
Differential Revision: https://reviews.llvm.org/D102208
Piotr Sobczak [Wed, 12 May 2021 07:23:59 +0000 (09:23 +0200)]
[AMDGPU] Skip invariant loads when avoiding WAR conflicts
No need to handle invariant loads when avoiding WAR conflicts, as
there cannot be a vector store to the same memory location.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D101177
Qiu Chaofan [Wed, 12 May 2021 08:51:52 +0000 (16:51 +0800)]
Revert "[PowerPC] [Clang] Enable float128 feature on VSX targets"
This commit brought build break in some f128 related tests. But that's
not the root cause. There exists some differences between Clang and
GCC's definition for 128-bit float types on PPC, so macros/functions in
glibc may not work with clang -mfloat128 well. We need to handle this
carefully and reland it.
Tomas Matheson [Tue, 11 May 2021 16:15:07 +0000 (17:15 +0100)]
[ARM] Prevent spilling between ldrex/strex pairs
Based on the same for AArch64:
4751cadcca45984d7671e594ce95aed8fe030bf1
At -O0, the fast register allocator may insert spills between the ldrex and
strex instructions inserted by AtomicExpandPass when expanding atomicrmw
instructions in LL/SC loops. To avoid this, expand to cmpxchg loops and
therefore expand the cmpxchg pseudos after register allocation.
Required a tweak to ARMExpandPseudo::ExpandCMP_SWAP to use the 4-byte encoding
of UXT, since the pseudo instruction can be allocated a high register (R8-R15)
which the 2-byte encoding doesn't support. However, the 4-byte encodings
are not present for ARM v8-M Baseline. To enable this, two new pseudos are
added for Thumb which are only valid for v8mbase, tCMP_SWAP_8 and
tCMP_SWAP_16.
The previously committed attempt in D101164 had to be reverted due to runtime
failures in the test suites. Rather than spending time fixing that
implementation (adding another implementation of atomic operations and more
divergence between backends) I have chosen to follow the approach taken in
D101163.
Differential Revision: https://reviews.llvm.org/D101898
Depends on D101912
Tomas Matheson [Wed, 5 May 2021 14:51:21 +0000 (15:51 +0100)]
[ARM] Precommit test for D101898
Differential Revision: https://reviews.llvm.org/D101912
Alex Orlov [Wed, 12 May 2021 08:39:30 +0000 (12:39 +0400)]
Fixed llvm-objcopy to add correct symbol table for ELF with program headers.
This fixes the following bugs:
https://bugs.llvm.org/show_bug.cgi?id=43935
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D102258
Djordje Todorovic [Tue, 11 May 2021 08:23:31 +0000 (01:23 -0700)]
[NFC][llvm-dwarfdump] Avoid passing std::string by value in collectStatsForDie()
Guillaume Chatelet [Wed, 12 May 2021 07:24:53 +0000 (07:24 +0000)]
[libc] Simplifies multi implementations
This is a roll forward of D101895 with two additional fixes:
Original Patch description:
> This is a follow up on D101524 which:
>
> - simplifies cpu features detection and usage,
> - flattens target dependent optimizations so it's obvious which implementations are generated,
> - provides an implementation targeting the host (march/mtune=native) for the mem* functions,
> - makes sure all implementations are unittested (provided the host can run them).
Additional fixes:
- Fix uninitialized ALL_CPU_FEATURES
- Use non pseudo microarch as it is only supported from Clang 12 on
Differential Revision: https://reviews.llvm.org/D102233
Dmitry Vyukov [Wed, 12 May 2021 07:07:00 +0000 (09:07 +0200)]
scudo: fix CheckFailed-related build breakage
I was running:
$ ninja check-sanitizer check-msan check-asan \
check-tsan check-lsan check-ubsan check-cfi \
check-profile check-memprof check-xray check-hwasan
but missed check-scudo...
Differential Revision: https://reviews.llvm.org/D102314
Ulysse Beaugnon [Wed, 12 May 2021 07:07:44 +0000 (09:07 +0200)]
[MLIR] Enable conversion from llvm::SMLoc to mlir::Location with OpAsmParser.
DialectAsmParser already allows converting an llvm::SMLoc location to a
mlir::Location location. This commit adds the same functionality to OpAsmParser.
Implementation is copied from DialectAsmParser.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D102165
Dumitru Potop [Wed, 12 May 2021 06:45:25 +0000 (08:45 +0200)]
[mlir] Support alignment in LLVM dialect GlobalOp
First step in adding alignment as an attribute to MLIR global definitions. Alignment can be specified for global objects in LLVM IR. It can also be specified as a named attribute in the LLVMIR dialect of MLIR. However, this attribute has no standing and is discarded during translation from MLIR to LLVM IR. This patch does two things: First, it adds the attribute to the syntax of the llvm.mlir.global operation, and by doing this it also adds accessors and verifications. The syntax is "align=XX" (with XX being an integer), placed right after the value of the operation. Second, it allows transforming this operation to and from LLVM IR. It is checked whether the value is an integer power of 2.
Reviewed By: ftynse, mehdi_amini
Differential Revision: https://reviews.llvm.org/D101492
Dmitry Vyukov [Wed, 12 May 2021 06:54:34 +0000 (08:54 +0200)]
tsan: fix syscall test on aarch64
Add missing includes and use SYS_pipe2 instead of SYS_pipe
as it's not present on some arches.
Differential Revision: https://reviews.llvm.org/D102311
Martin Storsjö [Tue, 11 May 2021 07:04:02 +0000 (10:04 +0300)]
[COFF] Fix ARM and ARM64 REL32 relocations to be relative to the end of the relocation
This matches how they are defined on X86.
This should fix the relative lookup tables pass for COFF, allowing
it to be reenabled.
Differential Revision: https://reviews.llvm.org/D102217
Dmitry Vyukov [Tue, 11 May 2021 08:18:48 +0000 (10:18 +0200)]
sanitizer_common: deduplicate CheckFailed
We have some significant amount of duplication around
CheckFailed functionality. Each sanitizer copy-pasted
a chunk of code. Some got random improvements like
dealing with recursive failures better. These improvements
could benefit all sanitizers, but they don't.
Deduplicate CheckFailed logic across sanitizers and let each
sanitizer only print the current stack trace.
I've tried to dedup stack printing as well,
but this got me into cmake hell. So let's keep this part
duplicated in each sanitizer for now.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D102221
Qiu Chaofan [Wed, 12 May 2021 06:32:37 +0000 (14:32 +0800)]
[PowerPC] [Clang] Enable float128 feature on VSX targets
Reviewed By: nemanjai, steven.zhang
Differential Revision: https://reviews.llvm.org/D92815
Kristina Bessonova [Mon, 10 May 2021 07:06:09 +0000 (09:06 +0200)]
[libcxx][test] Split more debug mode tests
Split a few more debug mode tests missed in D100592.
Differential Revision: https://reviews.llvm.org/D102194
Dmitry Vyukov [Mon, 10 May 2021 11:27:06 +0000 (13:27 +0200)]
sanitizer_common: don't write into .rodata
setlocale interceptor imitates a write into result,
which may be located in .rodata section.
This is the only interceptor that tries to do this and
I think the intention was to initialize the range for msan.
So do that instead. Writing into .rodata shouldn't happen
(without crashing later on the actual write) and this
traps on my local tsan experiments.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D102161
Vitaly Buka [Wed, 12 May 2021 05:51:36 +0000 (22:51 -0700)]
[symbolizer] Fix leak after D96883
Dmitry Vyukov [Mon, 10 May 2021 11:43:20 +0000 (13:43 +0200)]
sanitizer_common: fix SIG_DFL warning
Currently we have:
sanitizer_posix_libcdep.cpp:146:27: warning: cast between incompatible
function types from ‘__sighandler_t’ {aka ‘void (*)(int)’} to ‘sa_sigaction_t’
146 | sigact.sa_sigaction = (sa_sigaction_t)SIG_DFL;
We don't set SA_SIGINFO, so we need to assign to sa_handler.
And SIG_DFL is meant for sa_handler, so this gets rid of both
compiler warning, type cast and potential runtime misbehavior.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D102162
Dmitry Vyukov [Mon, 10 May 2021 07:04:20 +0000 (09:04 +0200)]
tsan: declare annotations in test.h
We already declare subset of annotations in test.h.
But some are duplicated and declared in tests.
Move all annotation declarations to test.h.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D102152
Qiu Chaofan [Wed, 12 May 2021 05:18:20 +0000 (13:18 +0800)]
[VectorComine] Restrict single-element-store index to inbounds constant
Vector single element update optimization is landed in 2db4979. But the
scope needs restriction. This patch restricts the index to inbounds and
vector must be fixed sized. In future, we may use value tracking to
relax constant restrictions.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D102146
Dmitry Vyukov [Fri, 7 May 2021 09:16:03 +0000 (11:16 +0200)]
tsan: mark sigwait as blocking
Add a test case reported in:
https://github.com/google/sanitizers/issues/1401
and fix it.
The code assumes sigwait will process other signals.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D102057
Dmitry Vyukov [Tue, 11 May 2021 08:37:48 +0000 (10:37 +0200)]
tsan: add a simple syscall test
Add a simple test that uses syscall annotations.
Just to ensure at least basic functionality works.
Also factor out annotated syscall wrappers into a separate
header file as they may be useful for future tests.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D102223
Chia-hung Duan [Wed, 12 May 2021 03:21:25 +0000 (11:21 +0800)]
[mlir][AsmPrinter] Remove recursion while SSA naming
Address the TODO of removing recursion while SSA naming.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D102226
Vitaly Buka [Wed, 12 May 2021 02:03:50 +0000 (19:03 -0700)]
[NFC][msan] Move setlocale test into sanitizer_common
Congzhe Cao [Wed, 12 May 2021 01:25:16 +0000 (21:25 -0400)]
[LoopInterchange] Handle lcssa PHIs with multiple predecessors
This is a bugfix in the transformation phase.
If the original outer loop header branches to both the inner loop
(header) and the outer loop latch, and if there is an lcssa PHI
node outside the loop nest, then after interchange the new outer latch
will have an lcssa PHI node inserted which has two predecessors, i.e.,
the original outer header and the original outer latch. Currently
the transformation assumes it has only one predecessor (the original
outer latch) and crashes, since the inserted lcssa PHI node does
not take both predecessors as incoming BBs.
Reviewed By: Whitney
Differential Revision: https://reviews.llvm.org/D100792
Jim Ingham [Wed, 12 May 2021 01:26:22 +0000 (18:26 -0700)]
Removing test...
Actually, I don't think this test is going to be stable enough
to be worthwhile. Let me see if I can think of a better way to
test this.
Matt Arsenault [Mon, 10 May 2021 13:22:45 +0000 (09:22 -0400)]
AMDGPU: Fix SILoadStoreOptimizer for gfx90a
This was hardcoding the register class to use for the newly created
pointer registers, violating the aligned VGPR requirement.
Jim Ingham [Wed, 12 May 2021 01:09:51 +0000 (18:09 -0700)]
This test is failing on Linux, skip while I investigate.
The gdb-remote tests are a bit artificial, depending on
Python threading, and sleeps. So I'm not 100% surprised it doesn't
work straight up on another XSsystem.
Sam Clegg [Tue, 11 May 2021 15:58:13 +0000 (08:58 -0700)]
[lld][WebAssembly] Fix for string merging + negative addends
Don't include the relocation addend when calculating the
virtual address of a symbol. Instead just pass the symbol's
offset and add the addend afterwards.
Without this fix we hit the `offset is outside the section`
error in MergeInputSegment::getSegmentPiece.
This fixes a real world error we were are seeing in emscripten.
Differential Revision: https://reviews.llvm.org/D102271
Richard Smith [Wed, 12 May 2021 00:46:18 +0000 (17:46 -0700)]
Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope."
This reverts commit
697ac15a0fc71888c372667bdbc5583ab42d4695, for which
review was not complete. That change was accidentally pushed when
an unrelated change was pushed.
Richard Smith [Wed, 12 May 2021 00:34:14 +0000 (17:34 -0700)]
Add test for PR50039.
I believe Clang's behavior is correct according to the standard here,
but this is an unusual situation for which we had no test coverage, so
I'm adding some.
Richard Smith [Thu, 6 May 2021 01:56:58 +0000 (18:56 -0700)]
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.
This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.
Differential Revision: https://reviews.llvm.org/D101968
Matt Arsenault [Thu, 6 May 2021 00:25:31 +0000 (20:25 -0400)]
GlobalISel: Don't hardcode varargs=false in resultsCompatible
Matt Arsenault [Tue, 11 May 2021 21:12:33 +0000 (17:12 -0400)]
AMDGPU: Fix assert on constant load from addrspacecasted pointer
This was trying to create a bitcast between different address spaces.
Matt Arsenault [Wed, 12 May 2021 00:10:55 +0000 (20:10 -0400)]
GlobalISel: Make constant fields const
Matt Arsenault [Tue, 4 May 2021 22:12:38 +0000 (18:12 -0400)]
GlobalISel: Split ValueHandler into assignment and emission classes
Currently the ValueHandler handles both selecting the type and
location for arguments, as well as inserting instructions needed to
handle them. Split this so that the determination of the argument
handling is independent of the function state. Currently the checks
for tail call compatibility do not follow the full assignment logic,
so it misses cases where arguments require nontrivial legalization.
This should help avoid targets ending up in a buggy state where the
argument evaluation may change in different contexts.
Matt Arsenault [Tue, 4 May 2021 21:32:09 +0000 (17:32 -0400)]
GlobalISel: Move AArch64 AssignFnVarArg to base class
We can handle the distinction easily enough in the generic code, and
this makes it easier to abstract the selection of type/location from
the code to insert code.
Jordan Rupprecht [Tue, 11 May 2021 23:08:53 +0000 (16:08 -0700)]
Revert "[GVN] Clobber partially aliased loads."
This reverts commit
6c570442318e2d3b8b13e95c2f2f588d71491acb.
It causes assertion errors due to widening atomic loads, and potentially causes miscompile elsewhere too. Repro, also posted to D95543:
```
$ cat repro.ll
; ModuleID = 'repro.ll'
source_filename = "repro.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
%struct.widget = type { i32 }
%struct.baz = type { i32, %struct.snork }
%struct.snork = type { %struct.spam }
%struct.spam = type { i32, i32 }
@global = external local_unnamed_addr global %struct.widget, align 4
@global.1 = external local_unnamed_addr global i8, align 1
@global.2 = external local_unnamed_addr global i32, align 4
define void @zot(%struct.baz* %arg) local_unnamed_addr align 2 {
bb:
%tmp = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1
%tmp1 = bitcast %struct.snork* %tmp to i64*
%tmp2 = load i64, i64* %tmp1, align 4
%tmp3 = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1, i32 0, i32 1
%tmp4 = icmp ugt i64 %tmp2,
4294967295
br label %bb5
bb5: ; preds = %bb14, %bb
%tmp6 = load i32, i32* %tmp3, align 4
%tmp7 = icmp ne i32 %tmp6, 0
%tmp8 = select i1 %tmp7, i1 %tmp4, i1 false
%tmp9 = zext i1 %tmp8 to i8
store i8 %tmp9, i8* @global.1, align 1
%tmp10 = load i32, i32* @global.2, align 4
switch i32 %tmp10, label %bb11 [
i32 1, label %bb12
i32 2, label %bb12
]
bb11: ; preds = %bb5
br label %bb14
bb12: ; preds = %bb5, %bb5
%tmp13 = load atomic i32, i32* getelementptr inbounds (%struct.widget, %struct.widget* @global, i64 0, i32 0) acquire, align 4
br label %bb14
bb14: ; preds = %bb12, %bb11
br label %bb5
}
$ opt -O2 repro.ll -disable-output
opt: /home/rupprecht/src/llvm-project/llvm/lib/Transforms/Utils/VNCoercion.cpp:496: llvm::Value *llvm::VNCoercion::getLoadValueForLoad(llvm::LoadInst *, unsigned int, llvm::Type *, llvm::Instruction *, const llvm::DataLayout &): Assertion `SrcVal->isSimple() && "Cannot widen volatile/atomic load!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0. Program arguments: /home/rupprecht/dev/opt -O2 repro.ll -disable-output
...
```
Lang Hames [Tue, 11 May 2021 23:04:00 +0000 (16:04 -0700)]
[JITLink] Fix bogus format string.
Leonard Chan [Thu, 6 May 2021 22:54:28 +0000 (15:54 -0700)]
[clang][Fuchsia] Introduce compat multilibs
These are GCC-compatible multilibs that use the generic Itanium C++ ABI
instead of the Fuchsia C++ ABI.
Differential Revision: https://reviews.llvm.org/D102030
Congzhe Cao [Tue, 11 May 2021 22:34:32 +0000 (18:34 -0400)]
[LoopInterchange] Fix legality for triangular loops
This is a bug fix in legality check.
When we encounter triangular loops such as the following form:
for (int i = 0; i < m; i++)
for (int j = 0; j < i; j++), or
for (int i = 0; i < m; i++)
for (int j = 0; j*i < n; j++),
we should not perform interchange since the number of executions
of the loop body will be different before and after interchange,
resulting in incorrect results.
Reviewed By: bmahjour
Differential Revision: https://reviews.llvm.org/D101305
Petr Hosek [Fri, 9 Apr 2021 18:53:59 +0000 (11:53 -0700)]
[Coverage] Support overriding compilation directory
When making compilation relocatable, for example in distributed
compilation scenarios, we want to set compilation dir to a relative
value like `.` but this presents a problem when generating reports
because if the file path is relative as well, for example `..`, you
may end up writing files outside of the output directory.
This change introduces a flag that allows overriding the compilation
directory that's stored inside the profile with a different value that
is absolute.
Differential Revision: https://reviews.llvm.org/D100232
Lang Hames [Tue, 11 May 2021 21:47:40 +0000 (14:47 -0700)]
[JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes.
These can be used to create eh-frame section fixing passes outside the usual
linker pipeline, which can be useful for tests and tools that just want to
verify or dump graphs.
Lang Hames [Tue, 11 May 2021 21:45:14 +0000 (14:45 -0700)]
[JITLink][x86-64] Add an x86_64 PointerSize constexpr.
This can be used in place of magic '8' values in generic x86-64 utilities.
Lang Hames [Tue, 11 May 2021 21:09:49 +0000 (14:09 -0700)]
[JITLink] Make LinkGraph debug dumps more readable.
This commit reorders some fields and fixes the width of others to try to
maintain more consistent columns. It also switches to long-hand scope
and linkage names, since LinkGraph dumps aren't read often enough for
single-character codes to be memorable.
Victor Huang [Tue, 11 May 2021 21:35:13 +0000 (16:35 -0500)]
[AIX][TLS] Diagnose use of unimplemented TLS models
Add front end diagnostics to report error for unimplemented TLS models set by
- compiler option `-ftls-model`
- attributes like `__thread int __attribute__((tls_model("local-exec"))) var_name;`
Reviewed by: aaron.ballman, nemanjai, PowerPC
Differential Revision: https://reviews.llvm.org/D102070
Congzhe Cao [Tue, 11 May 2021 22:06:41 +0000 (18:06 -0400)]
Revert "[LoopInterchange] Fix legality for triangular loops"
This reverts commit
29342291d25b83da97e74d75004b177ba41114fc.
The test case requires an assert build. Will add REQUIRES and re-commit.
Petr Hosek [Thu, 15 Apr 2021 08:22:04 +0000 (01:22 -0700)]
[llvm-cov] Support for v4 format in convert-for-testing
v4 moves function records to a dedicated section so we need to write
and read it separately.
https://reviews.llvm.org/D100535
Evandro Menezes [Tue, 11 May 2021 17:17:26 +0000 (12:17 -0500)]
[RISCV] Move instruction information into the RISCVII namespace (NFC)
Move instruction attributes into the `RISCVII` namespace and add associated helper functions.
Differential Revision: https://reviews.llvm.org/D102268
Nikita Popov [Tue, 11 May 2021 20:51:16 +0000 (22:51 +0200)]
[InstCombine] Clean up one-hot merge optimization (NFC)
Remove the requirement that the instruction is a BinaryOperator,
make the predicate check more compact and use slightly more
meaningful naming for the and operands.
Rob Suderman [Tue, 11 May 2021 20:40:03 +0000 (13:40 -0700)]
[mlir][tosa] Tosa elementwise broadcasting had some minor bugs
Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).
Differential Revision: https://reviews.llvm.org/D102276
River Riddle [Tue, 11 May 2021 19:40:27 +0000 (12:40 -0700)]
[mlir] Elide large elements attrs when printing Operations in diagnostics
Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.
Differential Revision: https://reviews.llvm.org/D102272