Mike Blumenkrantz [Wed, 27 Jul 2022 19:10:12 +0000 (15:10 -0400)]
zink: use stored format features for blit functionality
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17773>
Mike Blumenkrantz [Wed, 27 Jul 2022 19:08:44 +0000 (15:08 -0400)]
zink: store VkFormatFeatureFlags on creation
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17773>
Mike Blumenkrantz [Wed, 27 Jul 2022 18:57:06 +0000 (14:57 -0400)]
zink: handle mutable swapchain images with dmabuf
if a non-kopper swapchain image supports srgb, add a VkImageFormatListCreateInfo
to permit srgb mutability and avoid violating spec
cc: mesa-stable
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17773>
Dylan Baker [Wed, 3 Aug 2022 16:44:58 +0000 (09:44 -0700)]
docs: reset new features
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17875>
Dylan Baker [Wed, 3 Aug 2022 16:43:58 +0000 (09:43 -0700)]
VERSION: bump 22.3.0-devel
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17875>
Emma Anholt [Thu, 21 Jul 2022 22:42:18 +0000 (15:42 -0700)]
turnip: Use the GMEM CCU space for attachments when the stores won't.
Since the CCU only gets used for unaligned attachment stores or resolves
with the wrong formats, we can use that space for attachments in many
cases.
This gets two more of vk-5-normal's main renderpass's attachments to fit
in the next gmem_pixels increment, leaving 1 to go. Other renderpasses do
get better gmem_pixels, and a few get better tile sizes as a result, but
the fps increase from those looks to be <.2% at least.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
Emma Anholt [Thu, 21 Jul 2022 21:58:04 +0000 (14:58 -0700)]
turnip: Split the tiling config into separate layouts based on CCU usage.
We now choose between two (equal as of this commit) layouts based on
whether the renderpass's stores will use the CCU space, and assert that we
always know the chosen layout when we go using the gmem offsets.
This required making vkCmdClearAttachments in a secondary take the 3D path
instead of gmem blits, since secondaries only have to be compatible with
the primary's renderpass, rather than equal.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
Emma Anholt [Tue, 26 Jul 2022 17:51:15 +0000 (10:51 -0700)]
ci/freedreno: Update a630 s8 resolve xfails.
These tests are all only run in a full vk run. These removed ones were
fixed in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17684
and I'm betting the bypass ones were pre-existing (we hadn't updated 630's
full vk run list for these new stencil tests, I belive -- my previous full
run update was just from one of the two jobs).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
Connor Abbott [Mon, 18 Jul 2022 10:30:59 +0000 (12:30 +0200)]
tu: Restore formatting of tu_clear_blit.c
Conflict resolution appears to have gone awry. Use my previous resolution
of that rebase instead.
Fixes:
89263fde2057 ("tu: Use common vk_image struct")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
Nanley Chery [Mon, 1 Aug 2022 21:20:53 +0000 (14:20 -0700)]
iris: Dedent enum iris_depth_reg_mode
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
Nanley Chery [Mon, 1 Aug 2022 21:13:46 +0000 (14:13 -0700)]
iris: Make the D16 reg mode single-sampled
Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.
As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.
Make the workaround tracking code sample-dependent to fix this.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
Nanley Chery [Mon, 1 Aug 2022 21:19:55 +0000 (14:19 -0700)]
anv: Make the D16 reg mode single-sampled
Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.
As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.
Make the workaround tracking code sample-dependent to fix this.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
Alyssa Rosenzweig [Mon, 1 Aug 2022 22:56:01 +0000 (18:56 -0400)]
nir/lower_idiv: Be less creative about signs
I'm sorry to whoever wrote this, but
(x - (int) (x < 0)) ^ -((int) (x < 0))
is not an acceptable way to write iabs.
Shader-db results on Intel Tiger Lake with lower_idiv enabled:
total instructions in shared programs:
21122548 ->
21122570 (<.01%)
instructions in affected programs: 2369 -> 2391 (0.93%)
helped: 2
HURT: 8
total cycles in shared programs:
791609360 ->
791608062 (<.01%)
cycles in affected programs: 114106 -> 112808 (-1.14%)
helped: 9
HURT: 1
If we make the Intel back-end less stupid, we get to 9/1 helped/HURT for
instructions as well but that's for a different MR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17845>
Mike Blumenkrantz [Tue, 2 Aug 2022 12:18:34 +0000 (08:18 -0400)]
zink: combine loops for lazy descriptor program deinit
the bindless and push sets don't have update templates stored to
the program, so merging these loops avoids trying to destroy them
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
Mike Blumenkrantz [Tue, 2 Aug 2022 12:11:29 +0000 (08:11 -0400)]
zink: don't flag lazy push constant set dirty on batch change
this has its own flag
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
Mike Blumenkrantz [Mon, 1 Aug 2022 19:08:48 +0000 (15:08 -0400)]
zink: fix gfx program cache pruning with generated tcs
if the tcs was generated, then the prgram was added to the non-tcs cache,
which means deleting it from the tcs+tes cache will fail and then
context_destroy will explode
Fixes:
4123ee3c714 ("zink: invoke descriptor_program_deinit for programs on context destroy")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
Danylo Piliaiev [Thu, 28 Jul 2022 07:28:55 +0000 (10:28 +0300)]
ir3: Never remove GS_HEADER_IR3 sysval input
Without GS header geometry shader is never invoked which may cause
issues if it has side-effects.
Fixes GL CTS tests running via Zink:
KHR-GL46.shader_image_load_store.multiple-uniforms
KHR-GL46.texture_cube_map_array.image_op_geometry_sh
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6940
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17771>
Danylo Piliaiev [Thu, 28 Jul 2022 07:23:46 +0000 (10:23 +0300)]
ir3/ra: Always insert interval for precolored inputs
insert_dst checked whether dst is unused, however for precolored
inputs we always want to reserve a reg for them. Input could be
unused only if we explicitly want it.
Suggested-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17771>
Marek Olšák [Fri, 29 Jul 2022 04:59:03 +0000 (00:59 -0400)]
radeonsi: move small prim precision computation out of si_emit_cull_state
to put it next to its only use and remove the structure fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Thu, 28 Jul 2022 21:18:04 +0000 (17:18 -0400)]
radeonsi: move the no-AA small prim precision cull constant into an SGPR
This reduces the scalar load from vec4 to vec2.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 25 Apr 2022 08:53:28 +0000 (04:53 -0400)]
radeonsi: add a randomized blit test
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 04:20:36 +0000 (00:20 -0400)]
radeonsi: allow texture_map to upload only 1 sample for MSAA instead of all
Reuse the level parameter to do that, which allows us to keep
the pipe_transfer size unchanged. It's kinda hacky, but it's the simplest
way to do it. This will be used by the blit test to initialize MSAA textures.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Fri, 10 Jun 2022 23:57:13 +0000 (19:57 -0400)]
radeonsi: make various blit functions non-static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 06:24:14 +0000 (02:24 -0400)]
radeonsi/gfx11: use a better workaround for the export conflict bug
This is recommended for better performance.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 04:57:09 +0000 (00:57 -0400)]
radeonsi/gfx11: enable shader prefetch except for initial chip revisions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 03:50:38 +0000 (23:50 -0400)]
radeonsi/gfx11: rename si_calc_inst_pref_size -> si_get_shader_prefetch_size
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 03:46:53 +0000 (23:46 -0400)]
radeonsi/gfx11: skip code in si_update_shaders that has no effect
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 03:25:24 +0000 (23:25 -0400)]
radeonsi/gfx11: use better PRIM_GRP_SIZE_GFX11 setting
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sun, 10 Jul 2022 19:28:38 +0000 (15:28 -0400)]
radeonsi/gfx11: set SAMPLE_MASK_TRACKER_WATERMARK = 15 and clean up
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 03:12:06 +0000 (23:12 -0400)]
radeonsi/gfx11: use correct VGT_TESS_DISTRIBUTION settings
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sat, 23 Jul 2022 16:29:05 +0000 (12:29 -0400)]
radeonsi: cosmetic changes around do_hardware_msaa_resolve
- move gfx_level checking into the function
- rename the function
- call it in si_blit later
- set the SQTT event
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sat, 23 Jul 2022 16:28:03 +0000 (12:28 -0400)]
radeonsi: fold async_copy into the preceding conditional in si_blit
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sat, 23 Jul 2022 16:19:08 +0000 (12:19 -0400)]
radeonsi: move compute-related code from si_blit.c to si_compute_blit.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sat, 23 Jul 2022 16:10:54 +0000 (12:10 -0400)]
radeonsi: check for 16-bit hw support instead of relying on options.fp16
options.fp16 can be true even when the hw doesn't support FP16.
options.fp16 should only affect the CAP because 16-bit ops can still be
used by internal shaders.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 08:29:30 +0000 (04:29 -0400)]
radeonsi: add need_fmask_expand parameter into si_decompress_subresource
This is required by MSAA image stores for internal compute blits.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 02:13:57 +0000 (22:13 -0400)]
radeonsi: follow shader_info.float_controls_execution_mode (mostly)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 01:34:03 +0000 (21:34 -0400)]
radeonsi: don't do image stores with RGBX, L, LA, I, and SRGB formats
The only change in behavior is that RGBX stores now overwrite X, which is
what CB does and it's faster.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 00:51:20 +0000 (20:51 -0400)]
radeonsi: remove compute-based DCC decompression because it's broken
The new blit test discovered that it doesn't always work.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 00:54:23 +0000 (20:54 -0400)]
radeonsi: add common helper si_launch_grid_internal_images that is more robust
It does things in the correct order, which isn't easy to get right.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 00:52:45 +0000 (20:52 -0400)]
radeonsi: make si_launch_grid_internal static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Wed, 20 Jul 2022 04:34:57 +0000 (00:34 -0400)]
radeonsi: call pipe->blit instead of util_blitter_blit after MSAA resolving
This fixes a problem where the destination has a DCC-incompatible view
format and triggers a DCC decompression using a custom u_blitter path, which
is disallowed inside u_blitter due to it being a u_blitter recursion that
always crashes.
This is also better because we'll get the best codepath (u_blitter or
compute) instead of just u_blitter,
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sun, 24 Jul 2022 12:15:50 +0000 (08:15 -0400)]
radeonsi: move SI_MAX_VRAM_MAP_SIZE to si_debug_options.h
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 03:12:06 +0000 (23:12 -0400)]
radeonsi: unify VGT_TESS_DISTRIBUTION programming
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Mon, 11 Jul 2022 03:33:42 +0000 (23:33 -0400)]
ac/surface: don't forbid 256KB swizzle modes on smaller gfx11 chips
let addrlib make the right choice
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Fri, 8 Jul 2022 05:56:02 +0000 (01:56 -0400)]
amd/addrlib: fix 3D texture allocation failures on gfx11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Tue, 19 Jul 2022 01:26:41 +0000 (21:26 -0400)]
util/format: add util_format_rgbx_to_rgba helper
Image stores don't like RGBX on AMD. This is required by compute blits.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
Marek Olšák [Sun, 24 Jul 2022 20:09:00 +0000 (16:09 -0400)]
glthread: don't sync on IsEnabled(GL_DEPTH_TEST) by tracking it in glthread
Discovered with viewperf.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17781>
Marek Olšák [Sun, 24 Jul 2022 20:06:22 +0000 (16:06 -0400)]
glthread: don't ignore glPushAttrib/glPopAttrib when tracking GL_CULL_FACE
Fixes:
f4348ef60d51b07 - glthread: don't sync for glIsEnabled with a few enums
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17781>
Gert Wollny [Tue, 2 Aug 2022 06:12:30 +0000 (08:12 +0200)]
r600: increase possible stack size in binary code
With the trace posted in #6969 we get a nesting level of 149,
so make it a round 256 of stack entries.
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6969
Fixes:
a4840e15ab77b44a72cabd7d503172e8357477eb
r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17849>
Rob Clark [Sat, 23 Jul 2022 22:15:10 +0000 (15:15 -0700)]
freedreno/registers/a6xx: Some reg64 conversion
Reduce the spurious delta from a7xx regs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 23 Jul 2022 21:17:00 +0000 (14:17 -0700)]
freedreno/registers: Move varset to <enum>
De-noisify the enum values that are generation specific.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 23 Jul 2022 21:15:20 +0000 (14:15 -0700)]
freedreno/registers: Allow varset to be specified on enum
It gets a bit repetitive to specify the same varset on each value. The
rnn decode already handles it when specified on the enum, we just need
to relax the schema to allow this.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 23 Jul 2022 21:12:45 +0000 (14:12 -0700)]
freedreno/registers: Whitespace fix for gen_header.py
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 23 Jul 2022 20:14:34 +0000 (13:14 -0700)]
freedreno/ci: Update unit test reference decodes
Apparently we aren't running unit tests in CI?
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sun, 17 Jul 2022 19:20:36 +0000 (12:20 -0700)]
freedreno: Use enum for primtypes table
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sun, 17 Jul 2022 18:05:15 +0000 (11:05 -0700)]
freedreno/a6xx: De-open-code CACHE_FLUSH enum
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 30 Jul 2022 15:12:21 +0000 (08:12 -0700)]
freedreno/drm: Combine upper and lower 32b of OR val
The original reason it was split was because of libdrm ABI. But that no
longer applies since we pulled it into mesa.
While we are at it, remove the c++ workaround.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sun, 17 Jul 2022 15:43:22 +0000 (08:43 -0700)]
freedreno/autotune: Make 'offset' macro "private"
Otherwise it conflicts with glsl_types.h DEFAULT_CONSTRUCTOR when
included from a c++ file.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sun, 17 Jul 2022 15:18:55 +0000 (08:18 -0700)]
freedreno/ir3: Remove unneeded forward declaration
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sun, 17 Jul 2022 15:11:49 +0000 (08:11 -0700)]
freedreno: Extract common helper macros
De-duplicate some macros that had been copy/pasta'd around, etc.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 16 Jul 2022 20:33:13 +0000 (13:33 -0700)]
freedreno/a6xx: Fix enum tag
This wasn't meant to be a variable.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Rob Clark [Sat, 16 Jul 2022 18:08:52 +0000 (11:08 -0700)]
freedreno/a6xx: Remove fd6_format.[ch]
Just use the fdl6 version of the one remaining helper.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
Alyssa Rosenzweig [Mon, 1 Aug 2022 22:56:49 +0000 (18:56 -0400)]
pan/decode: Fix overrun decoding planes
We need to calculate the # of descriptors like we do on Midgard.
Fixes:
ae9316f8128 ("pan/decode: Decode Valhall surface descriptor")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17842>
Jason Ekstrand [Tue, 2 Aug 2022 15:23:36 +0000 (10:23 -0500)]
vulkan: Improve the docs for vk_subpass_info
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17858>
Jason Ekstrand [Tue, 2 Aug 2022 15:22:52 +0000 (10:22 -0500)]
vulkan: Always populate vk_render_pass_state::render_pass
This way drivers can at least see whether dynamic rendering is being
used or not even if they use vk_render_pass. Dynamic rendering only
drivers are expected to ignore those fields anyway.
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17858>
Christian Gmeiner [Sun, 31 Jul 2022 11:50:57 +0000 (13:50 +0200)]
etnaviv: Move nir_shader_compiler_options to compiler
It fits there much better and is an other step to get the
compiler to common code.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17819>
David Heidelberg [Wed, 20 Jul 2022 13:21:37 +0000 (15:21 +0200)]
ci: set reasonable amount of wget retries for each download
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17655>
Filip Gawin [Mon, 25 Jul 2022 14:18:04 +0000 (16:18 +0200)]
r300: don't read from output transform_r300_vertex_SEQ/SNE
Native rewrite in current form doesn't check
type of register and may use output as a
temp.
Helps with 218 deqp-gles2 tests.
Cc: mesa-stable
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17736>
Konstantin Seurer [Sat, 30 Jul 2022 15:35:57 +0000 (17:35 +0200)]
radv: Use vk_descriptor_set_layout
Use the common ref counting and the common destroy entrypoint.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17818>
Konstantin Seurer [Sat, 30 Jul 2022 15:09:48 +0000 (17:09 +0200)]
vulkan: Handle descriptor set layout alloc fails
Fixes: 949ce92 ("vulkan: Add a base struct for descriptor set layouts")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17818>
Konstantin Seurer [Sat, 30 Jul 2022 15:07:02 +0000 (17:07 +0200)]
vulkan: Fix descriptor set layout allocation scope
Fixes: 949ce92 ("vulkan: Add a base struct for descriptor set layouts")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17818>
Mykhailo Skorokhodov [Mon, 1 Aug 2022 16:06:23 +0000 (19:06 +0300)]
anv: Move Wa_1806527549 and enable by default
Move Wa_1806527549 into `init_render_queue_state` and
set HIZ_CHICKEN (7018h) bit = 1 by default.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6717
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17778>
Mykhailo Skorokhodov [Sat, 30 Jul 2022 00:32:38 +0000 (03:32 +0300)]
iris: Move Wa_1806527549 and enable by default
Move Wa_1806527549 into `iris_init_render_context` and
set HIZ_CHICKEN (7018h) bit = 1 by default for TGL.
Cc: mesa-stable
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17778>
Danylo Piliaiev [Mon, 1 Aug 2022 12:45:20 +0000 (15:45 +0300)]
freedreno: WFI after PC_TESSFACTOR_ADDR update
Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it.
Don't know any failures in tests.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17833>
Danylo Piliaiev [Mon, 1 Aug 2022 12:36:43 +0000 (15:36 +0300)]
tu: WFI after PC_TESSFACTOR_ADDR update
Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it.
Fixes GL CTS tests running via Zink:
KHR-Single-GL46.enhanced_layouts.glsl_contant_values
KHR-GLES32.core.tessellation_shader.tessellation_shader_point_mode.point_rendering
KHR-GLES32.core.tessellation_shader.winding.quads_cw
KHR-GLES32.core.tessellation_shader.winding.triangles_cw
And probably more.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6815
Suggested-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17833>
Lionel Landwerlin [Tue, 2 Aug 2022 06:14:02 +0000 (09:14 +0300)]
intel/dev: remove INTEL_DEVID_OVERRIDE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
Lionel Landwerlin [Mon, 1 Aug 2022 10:59:48 +0000 (13:59 +0300)]
intel/dev: add a test verifying that device override works
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
Lionel Landwerlin [Tue, 2 Aug 2022 08:59:46 +0000 (11:59 +0300)]
intel/tools/stub: fixup parsing of --platform=
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
Lionel Landwerlin [Tue, 2 Aug 2022 06:13:34 +0000 (09:13 +0300)]
intel/tools/drm-shim: fixup eu_stride for topology
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
Lionel Landwerlin [Mon, 1 Aug 2022 10:59:19 +0000 (13:59 +0300)]
intel/dev: move verification function to a header
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
Lionel Landwerlin [Tue, 2 Aug 2022 09:26:27 +0000 (12:26 +0300)]
anv: decode init batch with INTEL_DEBUG=bat
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17852>
Feng Jiang [Fri, 27 May 2022 08:24:11 +0000 (16:24 +0800)]
virgl: do not share virgl_screen between different drm_files
Now, only one instance of virgl_screen exists for a device
(/dev/dri/cardX), and it is shared by different frontends (eg GLX,
GBM, etc.). There is a problem with this, as follows:
/* Init GLX */
...
glXCreateContext(...);
...
/* GBM */
gbm_fd = open("/dev/dri/card0", O_RDWR);
dev = gbm_create_device(gbm_fd);
bo = gbm_bo_create(dev, ...);
plane_handle = gbm_bo_get_handle_for_plane(bo, ...);
drmPrimeHandleToFD(gbm_fd, handle.u32, flags, &plane_fd);
The above drmPrimeHandleToFD() call will fail with ENOENT.
The reason is that GBM and GLX share the same virgl_screen (file
descriptor), and it is not gbm_fd that is used to create gbm_bo,
but other fd (opened during GLX initialization). Since the scope
of prime handle is limited to drm_file, the above plane_handle is
invalid under gbm_fd.
By canceling the sharing of virgl_screen between different drm_files,
GBM can use the correct fd to create resources, thereby avoiding the
problem of invalid prime handle.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16738>
Marcin Ślusarz [Mon, 18 Jul 2022 16:35:34 +0000 (18:35 +0200)]
intel/compiler: use NIR_PASS more
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17619>
Marcin Ślusarz [Wed, 18 May 2022 15:05:53 +0000 (17:05 +0200)]
intel/compiler: insert URB fence before task/mesh termination
Bspec 53421 says:
"A URB fence memory is typically performed prior the thread
exit message, so that the next thread dispatch that reads
that URB memory will see it."
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16665>
Marcin Ślusarz [Mon, 16 May 2022 10:26:51 +0000 (12:26 +0200)]
intel/compiler: there are 4 types of fences on gfx >= 12.5
Found by code inspection.
There's an assert later checking that we haven't overflown
this array, so this change probably doesn't matter for any
workload.
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16665>
Marcin Ślusarz [Mon, 16 May 2022 10:10:00 +0000 (12:10 +0200)]
intel/compiler: emit URB fences for TASK/MESH
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16665>
Kenneth Graunke [Mon, 6 Jun 2022 21:05:54 +0000 (14:05 -0700)]
intel/compiler: Delete unused Gfx8+ code in brw_find_live_channel()
We now handle this in fs_visitor::lower_find_live_channel().
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17530>
Kenneth Graunke [Mon, 6 Jun 2022 09:35:09 +0000 (02:35 -0700)]
intel/compiler: Lower FIND_[LAST_]LIVE_CHANNEL in IR on Gfx8+
This allows the software scoreboarding pass, scheduler, and so on
to handle the individual instructions and handle them, rather than
trusting in the generator to do scoreboarding correctly when expanding
the virtual instruction to multiple actual instructions.
By using SHADER_OPCODE_READ_SR_REG, we also correctly handle the
software scoreboarding workaround when reading DMask/VMask.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17530>
Mark Janes [Mon, 1 Aug 2022 22:46:24 +0000 (15:46 -0700)]
intel/dev: drop warning for unhandled hwconfig keys
The hwconfig api may change unexpectedly prior to public release of
new platforms. Also, public documentation of the hwconfig api
sometimes lags the release.
For these reasons, warnings about unhandled hwconfig keys are noisy,
likely to occur, and unhelpful to most users. This commit drops those
warnings, in favor of a separate internal process for tracking
hwconfig api changes.
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17846>
Gert Wollny [Mon, 1 Aug 2022 18:38:34 +0000 (20:38 +0200)]
r600/sfn: Handle R600 class sin/cos
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre EG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17840>
Jiang Feng [Mon, 18 Jul 2022 06:53:26 +0000 (14:53 +0800)]
virgl: Set res->maybe_busy to true when creating resources
Currently, res->maybe_busy is false by default. If wait immediately
after the resource is created, virgl_drm_resource_wait() will return
directly without checking the actual state of the kernel, which will
cause synchronization problems, such as:
On Guest:
pipe_buffer_create [mesa]
virgl_drm_winsys_resource_create
virtio_gpu_resource_create_ioctl [kernel]
virtio_gpu_fence_alloc
virtio_gpu_object_create
virtio_gpu_cmd_resource_create_3d
VIRTIO_GPU_CMD_RESOURCE_CREATE_3D
virtio_gpu_object_attach
virtio_gpu_cmd_resource_attach_backing
VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING
resource_wait [mesa]
virgl_drm_resource_wait /* return directly without fence waiting */
pipe_buffer_map [mesa]
virgl_drm_resource_map
virtio_gpu_map_ioctl [kernel]
os_mmap
memcpy /* <== here */
On Host (with QEMU):
VIRTIO_GPU_CMD_RESOURCE_CREATE_3D
virgl_cmd_create_resource_3d [qemu]
virgl_renderer_resource_create [virglrenderer]
VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING
virgl_resource_attach_backing [qemu]
virtio_gpu_create_mapping_iov
virgl_renderer_resource_attach_iov [virglrenderer]
virgl_resource_attach_iov
vrend_pipe_resource_attach_iov
vrend_write_to_iovec /* <== here */
virtio_gpu_cleanup_mapping_iov [qemu]
In the example above, there is a race condition between memcpy and
vrend_write_to_iovec.
Signed-off-by: Jiang Feng <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17592>
Guilherme Gallo [Tue, 19 Jul 2022 03:22:15 +0000 (00:22 -0300)]
ci/lava: Remove MINIO_RESULTS_UPLOAD if requested
When we don't want to communicate with minio, e.g. running
lava_job_submitter script locally, MINIO_RESULTS_UPLOAD should be unset.
But this variable is already set by generate-env script, so we need to
remove it from the /set-job-env-vars.sh to avoid declaring it in
unexpected scenarios.
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17645>
Rob Clark [Sat, 23 Jul 2022 19:52:11 +0000 (12:52 -0700)]
libsync: Fix compiler warning
../src/util/libsync.h:134:33: warning: suggest braces around initialization of subobject [-Wmissing-braces]
struct sync_merge_data data = {0};
^
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17816>
Rob Clark [Sun, 17 Jul 2022 18:17:47 +0000 (11:17 -0700)]
util: Fix c++ enum casting pickiness
Fix problems when included from c++
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17816>
Jordan Justen [Thu, 28 Jul 2022 23:15:31 +0000 (16:15 -0700)]
intel/dev: Fill in system memory info when using INTEL_DEVID_OVERRIDE
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17828>
Guilherme Gallo [Mon, 25 Jul 2022 20:56:51 +0000 (17:56 -0300)]
ci/lava: Only parse result within testcase section
This commit fixes an issue related to leftover between jobs in the same
device under test in LAVA.
There is a possibility of having the resulting output being dumped just
after the boot, such as this job:
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
25674303#L155
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17752>
Jason Ekstrand [Wed, 1 Jun 2022 16:02:42 +0000 (11:02 -0500)]
nir/from_ssa: Ignore undef sources
Is a phi source is an undef, there's no point in copying it or really
caring about it at all. We would just end up inserting a mov from an
undef to a register. Instead, treat phi sources which point to an undef
as if the phi source doesn't exist.
This also prevents them from being included in phi webs which should
reduce the overall interference seen in the shader. Currently, if two
phis share an undef, their phi webs are consdiered to interfere. By
ignoring undefs we can get rid of this false interference and reduce the
size of phi webs. Reducing the number of things being copied by the
parallel copy instructions should also free up the paralle copy
algorithm and reduce the over-all churn of movs.
Shader-db results on Haswell:
total instructions in shared programs: 8156608 -> 8155406 (-0.01%)
instructions in affected programs: 164838 -> 163636 (-0.73%)
Shader-db results on Skylake:
total instructions in shared programs:
18227370 ->
18227359 (<.01%)
instructions in affected programs: 519 -> 508 (-2.12%)
helped: 6
HURT: 0
Shader-db results on Tigerlake:
total instructions in shared programs:
21167987 ->
21168025 (<.01%)
instructions in affected programs: 23701 -> 23739 (0.16%)
helped: 21
HURT: 27
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16817>
Jason Ekstrand [Wed, 1 Jun 2022 19:43:18 +0000 (14:43 -0500)]
lima: Lower undefs to zero and run DCE after from_ssa
Undefs can happen even in real GLSL shaders so it's best to handle them.
Lowering to zero is a perfectly valid implementation. Also, run DCE
because some of the undefs may be dead after from_ssa and there's no
point in processing those in the back-end.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16817>
Dave Airlie [Mon, 1 Aug 2022 02:01:48 +0000 (12:01 +1000)]
lavapipe: enable VK_FORMAT_R5G5B5A1_UNORM_PACK16
Doesn't cause any cts regressions here.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17826>
Adam Jackson [Tue, 26 Jul 2022 17:22:57 +0000 (13:22 -0400)]
gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control
This was disabled ages ago because it provoked bugs between us and
xserver about context creation attributes, hopefully those servers are
out of circulation by now, let's find out.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17756>
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