radv/ci: add a Van Gogh dEQP runner

Vangogh is the codename of the custom APU found in the Steam Deck.
As it only has 4 Zen2 cores and a 15W TDP, don't expect fast runs
until we get more of them in CI :)

Just like the Renoir and one of the NAVI10 runners, this VanGogh
runner is hosted in my CI farm, behind a couple of UPSes.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Charlie Turner <cturner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15555>

ci/b2c: update b2c to enable monitoring support

By enabling monitoring, we can collect all kind of metrics such as
CPU/Memory/Disk usage during execution, allowing us to detect
bottlenecks.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Charlie Turner <cturner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15555>

ci/b2c: bump the kernel to 5.17.1

This new kernel also brings support for sensors, which makes will
enable us to monitor metrics during the execution of tests.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Charlie Turner <cturner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15555>

ci/b2c: fix the generation of the IMAGE_UNDER_TEST variable

The `IMAGE_UNDER_TEST` variable set in `.b2c-test` got broken with
the merge of 7d474c1 (ci: Move most stuff out of root .gitlab-ci.yml).

During the shuffling, the `MESA_BASE_TAG` and `MESA_IMAGE_TAG`
variables were dropped, leading to `IMAGE_UNDER_TEST` being an
unexisting container.

To make this issue less likely to happen in the future, this patch
drops the code duplication that led to `IMAGE_UNDER_TEST` to be
the same as `MESA_IMAGE` and instead re-uses .use-debian/x86_test-vk
to generate `MESA_IMAGE`, which we then use verbatim in
`IMAGE_UNDER_TEST`.

The renaming is `MESA_IMAGE` into `IMAGE_UNDER_TEST` there to make the
distinction clear between the image run by gitlab-runner (what is
usually called `MESA_IMAGE` but we instead hardcode to valve-infra's
trigger container), and the image we are running on the test machines.

Fixes: 7d474c1 (ci: Move most stuff out of root .gitlab-ci.yml)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Charlie Turner <cturner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15555>

misc: replace `#ifdef\s\s__cplusplus` with `#ifdef\s__cplusplus`

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15762>

misc: Replace `#ifdef\t__cplusplus` with `#ifdef\s\s__cplusplus`

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15762>

nir/lower_int64: do not try to clamp floats to int-range

The clamping isn't correct, because the exact values ended up getting
rounded off a bit when converting back to floats.

But, converting floats to integers have undefined results when the
float value doesn't fit in the integer. So let's not try to clamp the
value here.

This was caught by digging at a Clang warning, see this thread for
details:

https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15547#note_1329769

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16022>

spirv: fix OpBranchConditional when both branches are the same

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6246

Signed-off-by: Bozhenko Alexey <oleksii.bozhenko@globallogic.com>
Fixes: 64cb143b922 ("spirv: Fix handling of OpBranchConditional with same THEN and ELSE")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15929>

util/stencil: fix stencil fallback blit shader texture types.

src/gallium/auxiliary/tgsi/tgsi_scan.c:287: scan_src_operand: Assertion `info->sampler_targets[index] == target' failed.
assert was being triggered by
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit
using the stencil fallback with zink.

Fixes: f05dfddeb1ad ("u_blitter: fix stencil blit fallback for crocus.")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16069>

u_blitter/stencil: take dstbox x/y into accounts for dst fb width

When setting the dst framebuffer width height, it might be silly
to constrain this beyond the dst resource, but at least constrain
it correctly to take account of x/y offsets.

This fixes some uses of this as a fallback for zink with
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit

Fixes: b4c07a8a87d0 ("gallium/util: allow scaling blits for stencil-fallback")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16069>

pvr: replace p_compiler.h boolean with stdbool

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16037>

ci/windows: Eliminate duplicate script definition

We already get this from the base we extend from.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16077>

ci: Also disable Windows container builds when down

Unlike all the other test configurations, we also want to drop the
Windows container build when our Windows machines aren't available.
Missed in !16055.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16077>

ci: Allow lima jobs to be globally disabled

This is useful in situations like right now, where the boards are dead.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16077>

dzn: remove stale cpp_args

We no longer use C++, so we don't need to set cpp_args here.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16076>

dzn: fixup indent

This seems to be all tab-indents we have in our code-base.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16076>

dzn: drop needless enum-casts

After rewriting to C, we also don't need these casts.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16076>

anv: Fix geometry flickering issue when compute and 3D passes are combined

Call flush_pipeline_select_3d in CmdBeginRendering() to emit a dummy MEDIA_VFE_STATE
before switching from GPGPU to 3D.

Original commit with the fix:
bc612536 ("anv: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3D")

Fixes: 3501a3f9ed92 ("anv: Convert to 100% dynamic rendering")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6201
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15954>

dzn: add space before += operator

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16052>

dzn: clean up pointer syntax

The code-style we use have a space before the first asterisk for
pointers. Fix a few inconsistencies.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16052>

dzn: remove some needless casts

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16052>

dzn: Add support for KHR_descriptor_update_template

Create update templates where the offset in the descriptor heap is
pre-calculated.

Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15691>

dzn: Split the write desc helpers in two halves

Split the write desc helpers in two halves, one taking a descriptor
offset directly, and the other one taking a descriptor set pointer.

This will allow us to pre-calculate descriptor offsets when creating
a descriptor_update template and speed up a bit the write step in that
case.

Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15691>

dzn: Pass layout objects to various dzn_descriptor_set_ptr_xxx helpers

Needed if we want to support KHR_descriptor_update_template, since
we won't have access to the final descriptor set when calculating heap
offsets in that case.

Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15691>

dzn: Rename a bunch of dzn_descriptor_set helpers

Let's be consistent with other helpers taking a dzn_descriptor_set_ptr
object and prefix all such functions with dzn_descriptor_set_ptr_.

We also rename dzn_descriptor_set_ptr_get_desc_vk_type() into
dzn_descriptor_set_ptr_get_vk_type() to shorten it a bit.

Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15691>

intel/dev: Add device info for RPL-P

Cc: mesa-stable
Ref: https://patchwork.freedesktop.org/series/102701/
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16054>

dzn: Add support for EXT_vertex_attribute_divisor

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15915>

ci/windows: Split the windows-related tests

Should help with the timeouts we see in CI right now.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16042>

d3d12: Move the D3D12ResourceState code to the gallium driver

It's only used there, and we don't plan to use it in Dozen, so let's move
the code to src/gallium/drivers/d3d12/ and get rid of the static
d3d12_resource_state library.

Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16042>

crocus: export GEM handle with RDWR access rights

Without this, it is impossible to export gem handles with write access.

This was fixed the same way for
i965 (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10850) and
iris (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10851).

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>`
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16057>

zink: unset PIPE_CAP_MULTI_DRAW_INDIRECT_PARTIAL_STRIDE

by the time this gets to the driver, it's really awful to solve,
so have the frontend solve it

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15963>

gallium: add PIPE_CAP_MULTI_DRAW_INDIRECT_PARTIAL_STRIDE

GL spec states that the stride for indirect multidraws:
* cannot be negative
* can be zero
* must be a multiple of 4

some drivers can't support strides which are not a multiple of the
size of the indirect struct being used, however, so rewrite those to
direct draws

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15963>

util/draw: fix indirect draw count readback

if there is an indirect count, always use it

Fixes: 3eb99323172 ("aux/draw: add a util function for reading back indirect draw params")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15963>

util/draw: handle draw_count=0 when reading indirect parameters

Fixes: 3eb99323172 ("aux/draw: add a util function for reading back indirect draw params")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15963>

util/draw: fix map size of indirect buffer in util_draw_indirect_read

this was incorrectly calculating too small of a map region if
the stride was less than the size of the struct

Fixes: 3eb99323172 ("aux/draw: add a util function for reading back indirect draw params")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15963>

venus: use linear modifier for legacy common wsi path

Towards the renderer, venus better uses VK_EXT_image_drm_format_modifier
to force linear with tiling modifier and mod_linear. Doing so won't make
any difference on the mesa implementations we care about given we have
required VK_EXT_image_drm_format_modifier for wsi support.

A lucky side effect of this is to allow common wsi to work with host
implementations not supporting dma_buf export.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15993>

venus: override aspectMask for internal tiling modifier

WSI images and Android AHBs can have tiling modifier overrides, thus we
must override the aspectMask upon image subresource layout query.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15993>

zink: handle device-local unsynchronized maps

this is only possible when tc determines the buffer is not in use
and decides to return a pointer immediately, so just give back a staging
buffer

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15979>

zink: remove xfb_barrier flag

this was an attempt to minimize the number of xfb barriers being emitted,
but really xfb barriers need to always be emitted in order for xfb to work

cc: mesa-stable

fixes (nv):
KHR-GL46.texture_view.reference_counting
KHR-GL46.transform_feedback_overflow_query_ARB.multiple-streams-multiple-buffers-per-stream
KHR-GL46.transform_feedback_overflow_query_ARB.multiple-streams-one-buffer-per-stream

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16065>

zink: fix xfb counter buffer barriers

a read barrier is needed for resume, yes, but the counter buffer
is always being written to, so write access must always be set

cc: mesa-stable

fixes (nv):
KHR-GL46.transform_feedback.draw_xfb_test

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16065>

zink: fix synchronization when drawing from streamout

this was well-documented, but ultimately wrong: the synchronization
being used was for binding streamout buffers (not counter buffers) as
vertex buffers, which was already handled just fine in the normal
vertex buffer binding

drawing from streamout ONLY uses the counter buffer, which means
the counter buffer needs to be synchronized for reading

cc: mesa-stable

fixes (nv):
KHR-GL46.transform_feedback.draw_xfb_feedbackk_test
KHR-GL46.transform_feedback.draw_xfb_instanced_test
KHR-GL46.transform_feedback.draw_xfb_stream_instanced_test

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16065>

zink: nv ci update

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16065>

zink: NV_linear_color_attachment

this fixes staging blits on nvidia

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16016>

zink: set VK_QUERY_RESULT_WAIT_BIT when copying to qbo

according to spec, this ensures that drivers will accurately
return results relative to when the query was ended

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16049>

nir_to_tgsi: Make vec_to_movs avoid unsupported coalescing for 64-bit.

I had some workarounds in ALU op emits trying to fix up when we were asked
to store to unsupported channels when the ALU op had 64bit srcs (so only
vec2 supported) but a 32-bit dest with a >vec2 writemask.

Those workarounds had some bugs breaking 64-bit uniform initializer tests
on virgl, and also set up too wide of a writemask such that they triggered
assertion failures on nvc0.  We can avoid the need for those workarounds
at emit time by just having nir_lower_vec_to_movs not generate unsupported
writemasks in the first place.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15934>

ci/dzn: Cut the runtime by running 1/3 of the enabled tests.

Marge jobs are failing at their 1 hour timeout regularly because windows
CI lacks capacity.  In the job I looked at, this test took 18 minutes,
which is surely contributing to the load.  Cut it down to get us some hope
of getting MRs through that run windows jobs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16062>

dzn: Report actual device limits

Report actual device limits instead of pseudo-random numbers.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15911>

dzn: Use core helpers to fill physical device features/properties

The core provide generic helpers to turn Vulkan minor version
features/properties into their KHR counterparts. Let's declare those
core features/properties structs and use those helpers so we get
ready to support newer spec versions without too much pain.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15911>

gallium/ddebug: implement pipe_vertex_state callbacks

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15964>

nouveau/nir: Set the input for vertex/instance ID like TGSI does.

Doesn't seem to help tests, but clears a TODO about differences between
them.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nir: Fix edgeflag input detection.

VERT_ATTRIB_EDGEFLAG is above GENERIC0, so it was being offset and thus
not recognized by vert_attrib_to_tgsi_semantic().

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nir: Fix the inverted sense of usesSampleMaskIn.

Fixes: 9f3d5e99ea60 ("compiler: Use util/bitset.h for system_values_read")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nv50: Set the primid sysval flag if it's in the sysval list, too.

It's declared an input in TGSI, even though it's an SV in the backend.  In
NIR, it shows up as an SV, so it's in this list.  Fixes NIR regressions in
primitive-id-in and primitive-id-restart.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nv50: Enable mesa/st alpha test lowering on nv50 with NIR.

With TGSI, the driver allocates space for the alpha ref as a uniform and
adds a conditional discard to the shader.  We could either replicate that
with NIR, or just set the flag saying we need the shader lowering and get
the same thing.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nir: Disable bitfield ops pre-nvc0.

There's no hardware instructions for them until then.  These chips don't
expose the extension provinding the GLSL builtins for operations like
bfrev, but NIR can recognize the construct and optimize it to
bitfield_reverse, which pre-nvc0 would then fail to codegen.  Prevents a
regression when moving to nir-to-tgsi.  Other lower_bitfield flags are set
as well for when someone comes along and adds optimizations for them too.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

ci/nouveau: Add nv92 xfails.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

ci/nouveau: Add expectations files for GM206.

I'm using this in place of jetson for regression testing NTT on nvc0+.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nir: Split fewer 64-bit loads

Also adjust the lowering pass to handle wide SSBO loads that we now emit
for the nir case.

This improves generated code quality since memoryopt can't
merge SSBO loads that end up predicated on a bounds check.

This also happens to fix a few test cases, only because the simpler generated
IR is less likely to trigger other compiler bugs. Eg on kepler with
NV50_PROG_USE_NIR=1, this fixes
arb_gpu_shader_fp64-fs-non-uniform-control-flow-ubo

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

nouveau/nv50: Print the number of loops in shader-db output.

This is important so you don't go comparing the number of instructions
emitted when you unrolled loops differently.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.

For !8044 I'm working on getting all drivers to accept NIR.  The NIR
compiler in the driver is apparently not quite ready, so use NIR-to-TGSI
instead.  This is a net win in testcases working on my RV770 and Turks
cards (especially in some important piglit tests involving YUV dma-buf
decode), though it's not regression-free.

shader-db (R600):
total dw in shared programs: 8553412 -> 8358918 (-2.27%)
dw in affected programs: 7476702 -> 7282208 (-2.60%)
total gprs in shared programs: 217286 -> 213217 (-1.87%)
gprs in affected programs: 72747 -> 68678 (-5.59%)
total loops in shared programs: 398 -> 330 (-17.09%)
loops in affected programs: 68 -> 0
total cf in shared programs: 558835 -> 332768 (-40.45%)
cf in affected programs: 420475 -> 194408 (-53.76%)

shader-db (Turks):
total dw in shared programs: 14104598 -> 13556782 (-3.88%)
dw in affected programs: 12161972 -> 11614156 (-4.50%)
total gprs in shared programs: 321068 -> 313690 (-2.30%)
gprs in affected programs: 114899 -> 107521 (-6.42%)
total loops in shared programs: 736 -> 651 (-11.55%)
loops in affected programs: 111 -> 26 (-76.58%)
total cf in shared programs: 925771 -> 581226 (-37.22%)
cf in affected programs: 678600 -> 334055 (-50.77%)
total stack in shared programs: 27853 -> 27855 (<.01%)
stack in affected programs: 5 -> 7 (40.00%)

glmark2 terrain: 0.137649% +/- 0.0511938% (n=6)
glmark2 jellyfish: no change (n=8)
unigine valley (extreme) 5.36 -> 5.45 (n=1 it takes so long to run)
unigine heaven (basic) 16.13 -> 16.15 (n=1)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14319>

r600/sb: Avoid causing an exception when getting the reciprocal of 0u.

I'm not sure what the hardware would return in this circumstance, so just
don't fold it.  Avoids regressions on transition to NIR.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14319>

r600: Fix reading back from a temp array immediately after writing on RV770.

KHR-GL33.shaders.indexing.tmp_array.vertexid regressed with the switch to
NIR-to-TGSI because the shader got optimized enough to emit a read just
after writing to the array (the kind of situation where a non-rel write
would have been followed by a PV/PS read).  The R600 and EG docs say you
always need to do this, but apparently some hardware gives you the right
answer anyway so we don't flag it on all of them.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14319>

ci/r600: Manual run updates.

Various fixes have happened, update status.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14319>

r600: Fix up some mis-indentation of blocks.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14319>

nir/copy_prop_vars: fix non-vector shader call payloads

Fixes RADV+Q2RTX.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Fixes: ff05137c2db ("nir: introduce and use nir_component_mask")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16029>

CI: Disable Windows jobs

We are underprovisioned for Windows, almost certainly not running wide
enough on the insufficient number of slots we do have, and there are
also indications that the machine itself is having physical issues.

Disable it until it's fixed.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16055>

ci/windows: Add a variable to globally disable jobs using windows runners

Suggested-by: Daniel Stone <daniels@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16055>

util: Remove util_cpu_detect

util_cpu_detect is an anti-pattern: it relies on callers high up in the call
chain initializing a local implementation detail. As a real example, I added:

...a Mali compiler unit test
...that called bi_imm_f16() to construct an FP16 immediate
...that calls _mesa_float_to_half internally
...that calls util_get_cpu_caps internally, but only on x86_64!
...that relies on util_cpu_detect having been called before.

As a consequence, this unit test:

...crashes on x86_64 with USE_X86_64_ASM set
...passes on every other architecture
...works on my local arm64 workstation and on my test board
...failed CI which runs on x86_64
...needed to have a random util_cpu_detect() call sprinkled in.

This is a bad design decision. It pollutes the tree with magic, it causes
mysterious CI failures especially for non-x86_64 developers, and it is not
justified by a micro-optimization.

Instead, let's call util_cpu_detect directly from util_get_cpu_caps, avoiding
the footgun where it fails to be called.  This cleans up Mesa's design,
simplifies the tree, and avoids a class of a (possibly platform-specific)
failures. To mitigate the added overhead, wrap it all in a (fast) atomic
load check and declare the whole thing as ATTRIBUTE_CONST so the
compiler will CSE calls to util_cpu_detect.

Co-authored-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15580>

nir/lower_alu_to_scalar: don't set the nir_builder cursor

This ensures recursive lowering in a single pass.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15977>

dzn/ci: Don't spam conformance warnings

We know it's not conformant and that's OK.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16031>

nine: Disable optional use of TTN when MUL_ZERO_WINS is available.

NIR doesn't have that knob currently, so we end up throwing errors about
it being ignored.

This should fix cases of "tgsi_to_nir: unhandled TGSI property 23 = 1",
and presumably do better at DX9 muls on nv50 and r600.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14883>

tgsi_to_nir: Emit load_ubo_vec4 instead of load_ubo on non-integer HW.

Otherwise, we get an ishl that the HW can't support, and a ushr if the NIR
ends up being lowered to ubo_vec4, which may not get constant-folded if
the offset was non-constant.

This matches what mesa/st uses for this arg to uniform lowering.

Fixes: #5971
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14883>

ntt: Add option to not optimized register allocation

On virglrenderer it is of interest to not re-use temporaries when we
want to handle precise, invariant, and highp/mediump with better
possibility for optimization.

v2: Force optimized RA if the number of registers is too large
    (Emma: only 16 bit signed int are reserved for register indices)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16051>

lavapipe: run nir_fold_16bit_sampler_conversions

big cleanup for all shaders coming from zink

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15852>

nir/fold_16bit_sampler_conversions: add a mask for supported sampler dims

AMD might not support cubes, but that doesn't mean cubes can't be used
on other drivers

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15852>

radv: Enable rt primitive culling for spirv2nir

Fixes: c8fe408fcc7 ("radv: Advertise ray primitive culling")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16028>

radv: Do not discard hits with t=tmax

Fixes dEQP-VK.ray_tracing_pipeline.inside_aabbs.chit.ray_end_tmax_zero.*

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16034>

anv: implement VK_EXT_primitives_generated_query

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15638>

tgsi: Emit ureg HW_ATOMIC decls in range order.

It turns out r600 has a dependency on it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>

nir_to_tgsi: Allocate the primid sysval to num_inputs, not num_outputs.

r600 would end up looking for it past the end of its array of inputs
(which expected 1:1 ordering from declarations to driver locations).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>

nir_to_tgsi: Avoid swizzling from undefined channels in load_output.

virglrenderer emits GLSL referencing all the swizzles, even if the write
mask doesn't contain them.  This is a problem when the output is
TessLevelInner, which has only 2 elements.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>

nir_to_tgsi: Don't forget to split 64-bit store_per_vertex_output.

Same splitting method as store_output.  Fixes regressions in virgl
with nir-to-tgsi.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>

nir_to_tgsi: Fix assertion failures handling 64-bit vec3/vec4 ssa undefs.

Found in virgl, where a glslparsertest accidentally gets its inputs
lowered to undefs, and 64-bit undefs don't get split by the normal
alu/intrinsic splitter (and would be hard to split because other passes
would see reconstruction of the vec4 from undefs and turn it back into
vec3/vec4 undef).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>

nir_to_tgsi: Add a workaround for virglrenderer TG4.

I've tried to keep virglrenderer workarounds out of ntt, but this one
would be bothersome to do with tgsi_translate and TG4 is pretty low-stakes
for NTT consumers.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>

win32: Do not use BUILD_GL32, we use def file to export win32 dll symbols.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14041>

win32: Fixes 32 bits visual studio module definition files by add script gen_vs_module_defs.py

Getting opengl32*.def consistence with Windows SDK.
Getting osmesa.mingw.def's gl* functions consistence with Windows SDK.
stw_* functions are cdecl, not stdcall, so there is no need mangling the symbol.
Fixes egl.def for x86
d3d10sw: Move the place of d3d10_sw.def to d3d10_sw.def.in
Fixes vulkan_lvp.def for x86
Fixes #5552
Remove stdcall-fixup

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14041>

turnip: Don't disable LRZ in subpasses after the first in the easy case.

If it's the same depth/stencil attachment, then there's no need to turn
off LRZ just because the subpass changed.  Doesn't help gfxbench perf yet,
but will with !16014.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15982>

turnip: Ignore TOP/BOTTOM_OF_PIPE bits in subpass src/dst dep flags.

gfxbench sets these between the gbuffer subpass and the following ones.
They should be no-ops as subpass dependencies.  gfxbench vk-5-debug perf
12.8 -> 14.6 fps thanks to getting gmem on the gbuffer rendering.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15982>

freedreno/ir3: Call nir_opt_find_array_copies().

gfxbench vk-5-normal has a shader that sampels into a texels[] array at
the top, then in a loop calls a GLSL function passing texels[] in by
value.  This resulted in a copy to a temp inside the loop, which got
lowered to scratch stores since it was pretty big.

By doing find_array_copies(), we notice that it's equivalent to
copy_deref, then get to copy-propagate from the array at the top.  Then we
only have to set up the scratch array outside of the loop and load_scratch
from it in the called function inside the loop.  This also causes there to
be less spilling, stps 1144 -> 354 and ldps 826->36.

However, it doesn't seem to change performance on the test.  So, while
this seems to be an improvement for the shader, and we could maybe even do
better by rematerializing the txl samples inside the loop instead of
storing the texture fetches to scratch in the first place, it doesn't
currently seem worth pursuing more optimization of this shader.

No change on freedreno shader-db.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15982>

turnip: Add nir_opt_conditional_discard.

We can easily do discard_if in the backend without control flow, but it
wasn't done in ir3 because the GL frontend already did it for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15982>

freedreno/ir3: Make sched nodes before adding deps.

The mark_kill_path() during dep setup follows SSA srcs, which when a phi
is involved may include a def from later in the same block, that we hadn't
created yet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15982>

turnip: Add TU_DEBUG=layout for dumping image layouts.

This was useful for comparing image allocations between gfxbench
gl_5_normal and vk_5_normal to see if rendering was generally equivalent
(formats, MSAA, UBWC choices, and notably gfxbench vk was choosing DXT5
instead of ASTC on non-android builds!)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15982>

turnip: Try harder to keep LRZ valid and fix a few edge cases

Refactored tu6_calculate_lrz_state and added comments.

1) If there is no depth write we could keep LRZ valid with any
compare op, we just have to temporary disable LRZ for incompatible
ops in such case.

2) Found that VK_COMPARE_OP_EQUAL is not compatible with LRZ,
and since it doesn't change LRZ buffer - LRZ could be just
temporary disabled. This fixes rendering of grass/trees in
PUBG mobile on angle.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6127

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16014>

nouveau: Skip cctl for atomic counters in tgsi

The tgsi path already marked all aliasing loads of atomic counters with
CACHE_CG, so we don't need to emit a cctl. This patch uses the cache
flag on the atomic to model whether the L1 cache needs the stale
values to be flushed or not.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14386>

nouveau: Emit cctl to flush L1 cache for atomics

We were previously only emitting these for CAS, but all of the atomics
seem to need it.

Fixes spec@glsl-es-3.10@execution@fs-simple-atomic-counter-inc-dec-read
on kepler with NV50_PROG_USE_NIR=1

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14386>

dzn: refactor error-handling

Here's a couple of cleanups to the error-handling code, now that we're
no longer using ComPtr<T>.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15816>

dzn: remove needless defines

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15816>

dzn: merge util sources

There, no more C and C++ sources of the same base-name. We can do both
in one source.

This is our last C++ source file, so let's also clean away the C++20
mess in meson.build.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15816>

dzn: port code to plain c

This does quite a lot in one go, simply because C and C++ are too
different to cleanly move from one language to another. But hopefully
this won't create too many rebase-issues.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15816>

dzn: do not set unused default member initializer

These objects aren't allocated using C++ constructors, so these default
member initializers does nothing.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15816>