Mike Blumenkrantz [Sun, 4 Apr 2021 17:25:51 +0000 (13:25 -0400)]
zink: implement sparse buffer creation/mapping
sparse buffers are not cpu-readable, so any mapping requires that they
use a staging buffer, either the stream uploader for writes or a manual
copy for readback
future work here should attempt to resolve two perf issues:
* sparse allocations should be allocated dynamically using a suballocator
or some other, more useful strategy
* readback shouldn't allocate a huge staging buffer
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Mike Blumenkrantz [Sun, 4 Apr 2021 17:17:23 +0000 (13:17 -0400)]
zink: add a pipe_context::resource_commit hook
so many structs
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Mike Blumenkrantz [Sun, 4 Apr 2021 17:10:40 +0000 (13:10 -0400)]
zink: use new ctx device lost checker function
make this handling more consistent
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Mike Blumenkrantz [Sun, 4 Apr 2021 17:09:59 +0000 (13:09 -0400)]
zink: add a ctx function for handling device lost resets
ensure the reset function is only called once when the screen flag is set
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Mike Blumenkrantz [Sun, 4 Apr 2021 17:02:40 +0000 (13:02 -0400)]
zink: use zink_screen_handle_vkresult() for fence and timeline waiting
more consistent handling and some code size reduction
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Mike Blumenkrantz [Sun, 4 Apr 2021 16:59:41 +0000 (12:59 -0400)]
zink: add a screen util function for handling VkResults
enforce device lost status always
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Mike Blumenkrantz [Sun, 4 Apr 2021 16:55:34 +0000 (12:55 -0400)]
zink: minor refactoring of buffer map for read case
make this a little more flexible for the non-DONTBLOCK case
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Alyssa Rosenzweig [Mon, 3 May 2021 23:39:59 +0000 (19:39 -0400)]
pan/bi: Use nir_lower_to_bit_size
Last holdout of the backend algebraic pass. Delete it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Mon, 3 May 2021 23:00:35 +0000 (19:00 -0400)]
pan/bi: Switch to 1-bit bools
In prep for FP16.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Tue, 4 May 2021 16:01:06 +0000 (12:01 -0400)]
pan/bi: Don't swizzle scalars
Pointless, already replicated.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Wed, 14 Apr 2021 00:21:03 +0000 (20:21 -0400)]
pan/bi: Track scalarness of 16-bit ALU
Needed for optimal swizzle lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Mon, 3 May 2021 22:37:41 +0000 (18:37 -0400)]
pan/bi: Handle b2i8/16
Missing from the algebraic rules, get it right this time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Mon, 3 May 2021 22:33:57 +0000 (18:33 -0400)]
pan/bi: Handle b2f ourselves
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Mon, 3 May 2021 22:29:35 +0000 (18:29 -0400)]
pan/bi: Handle ineg
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Mon, 3 May 2021 22:23:54 +0000 (18:23 -0400)]
pan/bi: Handle integer min/max ourselves
total instructions in shared programs: 158197 -> 158181 (-0.01%)
instructions in affected programs: 169 -> 153 (-9.47%)
helped: 3
HURT: 0
total nops in shared programs: 116393 -> 116397 (<.01%)
nops in affected programs: 60 -> 64 (6.67%)
helped: 0
HURT: 2
total clauses in shared programs: 28628 -> 28627 (<.01%)
clauses in affected programs: 10 -> 9 (-10.00%)
helped: 1
HURT: 0
total quadwords in shared programs: 124146 -> 124140 (<.01%)
quadwords in affected programs: 127 -> 121 (-4.72%)
helped: 3
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Alyssa Rosenzweig [Mon, 3 May 2021 23:00:23 +0000 (19:00 -0400)]
pan/bi: Add imm_uintN helper
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>
Mike Blumenkrantz [Wed, 21 Apr 2021 17:20:40 +0000 (13:20 -0400)]
zink: support PIPE_CAP_QUERY_MEMORY_INFO
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10511>
Mike Blumenkrantz [Wed, 21 Apr 2021 17:20:13 +0000 (13:20 -0400)]
zink: hook up VK_EXT_memory_budget
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10511>
Mike Blumenkrantz [Wed, 21 Apr 2021 17:19:47 +0000 (13:19 -0400)]
zink: grab GetPhysicalDeviceMemoryProperties2 from instance
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10511>
Eric Anholt [Tue, 4 May 2021 19:42:16 +0000 (12:42 -0700)]
ci/freedreno: Mark a5xx texture gather as flaky.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10633>
Jason Ekstrand [Tue, 4 May 2021 18:59:54 +0000 (13:59 -0500)]
nir/builder: Move clamp helpers to nir_builder.h
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10631>
Erik Kurzinger [Mon, 3 May 2021 12:18:03 +0000 (08:18 -0400)]
vulkan/device_select: avoid segfault on Wayland if wl_drm is unavailable
On Wayland, if the wl_drm interface is not available, for example if the
compositor is using the proprietary NVIDIA driver along with their egl-wayland
library, the device_select layer will fail to initialize. However, the failure
path will unconditionally call wl_drm_destroy even though info.wl_drm would be
NULL in that case. This can cause a segfault in libwayland-client.so.
To fix this, check if info.wl_drm is NULL before calling wl_drm_destroy. This
way, initialization will fail gracefully even if that interface is not present.
Signed-off-by: Erik Kurzinger <ekurzinger@nvidia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10598>
Caio Marcelo de Oliveira Filho [Thu, 29 Apr 2021 19:10:13 +0000 (12:10 -0700)]
nir: Move shared_memory_explicit_layout bit into common shader_info
Move it out of the "cs" sub-struct, since the bit can be used for
other shader stages in the future.
This also removes a subtle issue in spirv_to_nir:
info.cs.shared_memory_explicit_layout was used without checking for
the CS shader stage. It ended up being "harmless" since the effects
also depended on presence of shared variables.
Fixes:
5de6c5973a6 ("spirv: Implement SPV_KHR_workgroup_memory_explicit_layout")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10529>
Eric Anholt [Mon, 3 May 2021 18:28:50 +0000 (11:28 -0700)]
tunrip: Add support for VK_EXT_separate_stencil_usage.
We were implictly including it in exposing VK 1.2, but we weren't making
use of the supplied struct. Actually enabling it gives us a chance to do
slightly better at Z/S UBWC, and means we won't lose the separate usage
test coverage when switching back to exposing VK 1.1.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10594>
Erik Faye-Lund [Mon, 19 Apr 2021 10:36:59 +0000 (12:36 +0200)]
zink: cache SpvId for aggregate glsl_types
This should reduce the amount of types we re-emit while producing
SPIR-V.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10372>
Erik Faye-Lund [Mon, 19 Apr 2021 10:24:49 +0000 (12:24 +0200)]
zink: handle matrix-types after vectors
This makes us handle all non-aggregate types before we handle aggregate
types. This is going to matter in the next commit.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10372>
Alyssa Rosenzweig [Tue, 4 May 2021 16:46:26 +0000 (12:46 -0400)]
pan/mdg: Don't print zero
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:42:17 +0000 (12:42 -0400)]
pan/mdg: Reduced printed parens
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:41:30 +0000 (12:41 -0400)]
pan/mdg: Don't print mem addr brackets
Already comma separated.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:36:36 +0000 (12:36 -0400)]
pan/mdg: Don't print explicit .rte
Default round mode.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:36:07 +0000 (12:36 -0400)]
pan/mdg: Suppress most attribute tables
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:33:15 +0000 (12:33 -0400)]
pan/mdg: Don't print zero shifts
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:30:13 +0000 (12:30 -0400)]
pan/mdg: More concise RMU name
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 16:29:38 +0000 (12:29 -0400)]
pan/mdg: Hide units behind MIDGARD_MESA_DEBUG=verbose
Not usually interesting unless debugging bundling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 19:37:26 +0000 (15:37 -0400)]
panfrost: Key blend shaders to the input types
On Bifrost, fragment shaders might output either FP16 or FP32. The blend
shader will access the output as-is within the register, so depending on
the precision of the blend shader's logic, it may need to insert a
f2f16 or f2f32 conversion. This requires expanding the blend shader key.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 19:06:04 +0000 (15:06 -0400)]
pan/blend: Emit explicit conversions for all types
Needed so we can mix and match.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Tue, 4 May 2021 15:08:42 +0000 (11:08 -0400)]
panfrost/lower_framebufffer: Don't use i2imp
Fails when converting from i2i8, which is possible.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 18:13:41 +0000 (14:13 -0400)]
panfrost: Assume lower_fragcolor has been called
Allows us to clean up quite a bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 18:13:04 +0000 (14:13 -0400)]
panfrost: Call nir_lower_fragcolor based on key
We only want it to trigger if MRT is actually in use. This is a cheap
key (only require multiple variants for an obscure edge case) and avoids
the perf regression of using this pass which is needed for conformance.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 19:33:53 +0000 (15:33 -0400)]
panfrost/blend: Prepare for lower_fragcolor
FRAG_RESULT_COLOR means something a bit different.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:30:09 +0000 (12:30 -0400)]
panfrost/blend: Distribute to_c_factor
Easier to understand, I think.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:25:45 +0000 (12:25 -0400)]
panfrost/blend: Workaround a v7 implementation-detail
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:21:38 +0000 (12:21 -0400)]
panfrost/blend: Fix outdated comments
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:20:42 +0000 (12:20 -0400)]
pan/lower_blend: Rename is_bifrost->scalar
Don't leak ISA details.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:16:45 +0000 (12:16 -0400)]
pan/lower_blend: Use NIR helpers
Deletes a bunch of indentations.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:09:20 +0000 (12:09 -0400)]
pan/lower_blend: Clean up type size handling
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Mon, 3 May 2021 16:37:59 +0000 (12:37 -0400)]
panfrost: Don't clobber RT0 if RTn is disabled
Fixes:
a124c47b9f9 ("panfrost: Fix NULL derefs in pan_cmdstream.c")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:04:09 +0000 (12:04 -0400)]
panfrost: Minor cleanup of blend CSO
No need to cast.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 16:02:12 +0000 (12:02 -0400)]
panfrost: Support alpha_to_one
Gets rid of a bogus assert in the blend CSO create.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 15:44:07 +0000 (11:44 -0400)]
panfrost: Make comment less confusing
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Mon, 3 May 2021 16:12:21 +0000 (12:12 -0400)]
pan/bi: Lower 8-bit fragment input
Same reasons/technique as fragment output lowering, just need the NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Mon, 3 May 2021 16:11:54 +0000 (12:11 -0400)]
pan/bi: Handle swizzles in i2i8
Otherwise they get copypropped away.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Mon, 3 May 2021 16:11:26 +0000 (12:11 -0400)]
pan/bi: Add single-component 8-bit mkvec lowering
So we can implement scalar i2i8.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 21:42:54 +0000 (17:42 -0400)]
pan/bi: Handle different sizes of LD_TILE
v2: Fix overflow.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Alyssa Rosenzweig [Wed, 21 Apr 2021 19:01:49 +0000 (15:01 -0400)]
pan/bi: Track dual-src blend type
Will be needed for fp16 outputs. I am acutely aware dual-src blending is
broken on Bifrost right now anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Yiwei Zhang [Fri, 30 Apr 2021 17:20:54 +0000 (17:20 +0000)]
venus: query extended resource info from gralloc
Creating Android swapchain image from gralloc buffer requires to use
VkImageDrmFormatModifierExplicitCreateInfoEXT. To fill the struct info,
we need to query extended resource info from gralloc.
With the queried modifier from gralloc, we can ask the driver for the
plane count of the given format and modifier pair.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10553>
Eric Anholt [Mon, 3 May 2021 22:19:46 +0000 (15:19 -0700)]
tgsi: Mark the tgsi_exec_channel and tgsi_double_channel ALIGN16.
We allocate them all align16, so mark the unions (and their container
structs) that way so the compiler can do aligned SSE load/stores.
glmark2 -b loop FPS +0.197265% +/- 0.117633% (n=1906)
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10604>
Charlie Turner [Tue, 27 Apr 2021 09:10:28 +0000 (10:10 +0100)]
radv: Add a STONEY baseline for dEQP.
See:
https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9286188
https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297109
https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297110
v2.
- Clarify that the dEQP-VK.texture.explicit_lod.2d tests are skipped
due to slow APU-based STONEY test devices.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10559>
Iago Toral Quiroga [Thu, 29 Apr 2021 07:25:05 +0000 (09:25 +0200)]
v3d: choose a larger CSD supergroup size if possible
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Iago Toral Quiroga [Thu, 29 Apr 2021 07:23:28 +0000 (09:23 +0200)]
broadcom/common: move CSD supergroup sizing to a common helper
We want to use this in GL too.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Iago Toral Quiroga [Wed, 28 Apr 2021 12:48:13 +0000 (14:48 +0200)]
v3dv: limit supergroup size in presence of TSY barriers
When a TSY barrier is hit, the entire supergroup will be synchronized.
If the supergoup is large and uses all available QPU threads it would
mean that we would sychronize and stall all running threads until all
of them reach the barrier, which may be inefficient.
This patch makes it so that if the compute shader has any such barriers
we limit the supergroup size so each supergroup only takes half of the
QPU threads available at most, so that if one supergroup hits a
barrier we have at least one other supergroup we can run, reducing
idle QPU time.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Iago Toral Quiroga [Wed, 28 Apr 2021 10:17:46 +0000 (12:17 +0200)]
broadcom/compiler: track if a shader has control barriers in prog_data
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Iago Toral Quiroga [Wed, 28 Apr 2021 09:09:04 +0000 (11:09 +0200)]
v3dv: choose a larger CSD supergroup size if possible
Each supergroup executes a number batches. Each batch has 16 elements
(one per QPU lane), except possibly the last batch which might be
incomplete. Until now, we packed a single workgroup in each supergroup,
which can lead to more incomplete batches and less efficient use
of the QPUs depending on the configuration of workgroups being dispatched.
This patch computes a number of workgroups per supergroup so that
we reduce or completely eliminate incomplete batches if possible.
It should be noted however, that TSY barriers act on supergroups,
so larger supergroups lead to larger syncpoints on barriers too.
A follow-up patch will try to find a good balance for compute shaders
that use such barriers.
This improves performance of the Sascha Willem's computecloth demo
by ~13%.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Iago Toral Quiroga [Thu, 29 Apr 2021 09:10:32 +0000 (11:10 +0200)]
compiler/nir: add a divergence analysis option for non-uniform workgroup id
The V3D hardware allows us to pack multiple workgroups together to avoid
wasting execution lanes in shader cores.
For example, if we dispatch 16 workgroups with a local size of 1 element, we
can pack all 16 workgroups in a single 16-wide dispatch where each lane
executes a different workgroup, instead of 16 1-wide dispatches.
When we do this, we don't have a uniform workgroup id any more.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Caio Marcelo de Oliveira Filho [Wed, 28 Apr 2021 17:59:20 +0000 (10:59 -0700)]
intel/compiler: Remove unused exported functions
Now that all drivers are using brw_cs_get_dispatch_info() we can
remove one function (which is now unused) and reduce the scope of the
other.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
Caio Marcelo de Oliveira Filho [Wed, 28 Apr 2021 17:57:14 +0000 (10:57 -0700)]
i965: Use brw_cs_get_dispatch_info()
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
Caio Marcelo de Oliveira Filho [Wed, 28 Apr 2021 17:56:58 +0000 (10:56 -0700)]
anv: Use brw_cs_get_dispatch_info()
And since right_mask is already provided as part of dispatch_info,
just use that instead of storing it.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
Caio Marcelo de Oliveira Filho [Wed, 28 Apr 2021 17:56:28 +0000 (10:56 -0700)]
iris: Use brw_cs_get_dispatch_info()
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
Caio Marcelo de Oliveira Filho [Wed, 28 Apr 2021 17:54:53 +0000 (10:54 -0700)]
intel/compiler: Add common function for CS dispatch info
We have this small calculations repeated in each Intel driver, so move
them to a single place to be reused. Also includes "right_mask" since
is always used in the same context and depends on the dispatch info
values.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
Caio Marcelo de Oliveira Filho [Thu, 29 Apr 2021 21:16:46 +0000 (14:16 -0700)]
nir: Remove now unnecessary conditions from emit_load/store helpers
The mode one was used before
0bc5a829dd6 ("nir: Remove shared support from
lower_io").
The others were used before
5f7c7c9a7f7 ("nir: add src and dest types
to all IO loads and stores for mediump").
All conditions now are always true, so drop them.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10533>
Boris Brezillon [Tue, 4 May 2021 10:37:03 +0000 (12:37 +0200)]
panfrost/ci: Run the full deqp-gles3 testsuite
We recently added 5 more VIM3s to the lavalab, this should be more than
enough to run the full GLES 3.0 testsuite on G52.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10614>
Erik Faye-Lund [Mon, 26 Apr 2021 11:32:08 +0000 (13:32 +0200)]
docs: update gallium doxygen docs
Gallium's background as a Tungstend Graphics technology is no longer
significant; it's a historical detail. Besides, since Tungsten Graphics
were acquired by VMware more than a decade ago, the website no longer
exists.
While we're at it, replace the docs link with a link to the mesa docs,
and point to archive.org copy of the Tungsten Graphics paper.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2770
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10452>
Gert Wollny [Sun, 2 May 2021 21:48:05 +0000 (23:48 +0200)]
nir/opt_algebraic: optimizations for add umax/umin with zero
For unsigned comparisons with zero these ops can be eliminated.
v2: Add comparison optimizations with -1 (Rhys Perry)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10583>
Erik Faye-Lund [Mon, 3 May 2021 09:42:35 +0000 (11:42 +0200)]
lavapipe: consistently use nir macros
NIR provides two helper macros to run transformation passes correctly,
NIR_PASS() and NIR_PASS_V(). So far we've seemingly been a bit haphazard
about when to use them.
Let's correct that, and consistently use the NIR helpers here. This
helps us in two ways:
1. We now run nir_validate_shader after each pass, ensuring we didn't
break the shader
2. We now respect the NIR_PRINT environment variable for all NIR passes,
making debugging much less surprising.
In addition, we had an OPT()-macro that doesn't seem to provide much
help other than to hiding some trivial details. But they make our code
different to other users of NIR, which doesn't seem ideal. So let's drop
that macro while we're at it.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10585>
Samuel Pitoiset [Fri, 23 Apr 2021 12:03:04 +0000 (14:03 +0200)]
radv: implement RADV_FORCE_VRS for the LLVM backend
Just to make it consistent compared to ACO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10432>
Marek Olšák [Thu, 29 Apr 2021 01:27:02 +0000 (21:27 -0400)]
util: fix (re-enable) L3 cache pinning
cores_per_L3 was uninitialized, so it was always disabled.
Remove the variable and do it differently.
Fixes:
11d2db17c52 - util: rework AMD cpu L3 cache affinity code.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>
Marek Olšák [Thu, 29 Apr 2021 01:28:15 +0000 (21:28 -0400)]
util: print CPU caps in release builds too
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>
Dave Airlie [Fri, 19 Mar 2021 20:32:37 +0000 (06:32 +1000)]
i965: drop old brw ff gs code.
This isn't needed anymore.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
Dave Airlie [Fri, 19 Mar 2021 20:31:29 +0000 (06:31 +1000)]
i965: port fixed function geom shader to use compiler paths
This just moves to the common code in the compiler.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
Dave Airlie [Fri, 19 Mar 2021 20:23:32 +0000 (06:23 +1000)]
intel/compiler: add support for compiling fixed function gs
This is ported from i965, but the interface is cleaned up
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
Dave Airlie [Tue, 4 May 2021 01:05:19 +0000 (11:05 +1000)]
intel: move brw_ff_gs_prog_key/data to compiler.
Step one to moving the ff_gs emitter to compiler for sharing,
move BRW_MAX_SOL_BINDINGS up so the keys are in same area
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
Eric Anholt [Mon, 3 May 2021 22:46:50 +0000 (15:46 -0700)]
ci/freedreno: Add another db820c flake that's appeared in the last few months.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10597>
Eric Anholt [Mon, 3 May 2021 19:30:29 +0000 (12:30 -0700)]
ci/freedreno: Fix the recent-a5xx-texture-flakes matches.
We've had about 1/day of the texelfetch group in the IRC flake reports
since apr 23, and tex-miplevel-selection that I marked before is actually
all the subtests it looks like. Also, you can't include the ",Fail" if
you want to actually match a test name.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10597>
Ian Romanick [Thu, 29 Apr 2021 20:55:30 +0000 (13:55 -0700)]
gallivm: Remove unused GALLIVM_NAN_RETURN_NAN
In the review, Roland says, "I think the unused nan behaviors was there
just for completeness, so it can easily go."
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
Ian Romanick [Wed, 28 Apr 2021 22:34:13 +0000 (15:34 -0700)]
gallivm: Use GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN for norm clamping
Since the second source is always a constant that is known to be a
number, this should have the same performance as
GALLIVM_NAN_BEHAVIOR_UNDEFINED.
A lofty goal is to eventually remove GALLIVM_NAN_BEHAVIOR_UNDEFINED.
There's still a lot of (mostly implicit) users, and I don't feel like
tackling that right now. :)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
Ian Romanick [Wed, 28 Apr 2021 22:41:56 +0000 (15:41 -0700)]
gallivm: Use range analysis to generate better fmin and fmax code
If it is known that one of the source must be a number, then the (more
efficient) GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN path can be used.
v2: s/know to be/known to be/. Noticed by Roland.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
Ian Romanick [Wed, 28 Apr 2021 22:30:41 +0000 (15:30 -0700)]
gallivm: Fix NaN behavior of min and max
Like softpipe in mesa!10419, llvmpipe suffers from improper handling
of NaN in nir_op_fmax and nir_op_fmin. nir_op_fsat is already handled
correctly. OpenCL strictly requires the "NaN cleansing" behavior, so
all of the functionality is in place. Just make the graphics APIs use
the OpenCL path.
The majority of the possible performance penalty incurred here should
be resolved in the next commit.
v2: Add updated checksum for bgfx/39-assao.rdc trace. Rendering goes
from mostly garbage to looking correct to me.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
Ian Romanick [Wed, 28 Apr 2021 22:43:48 +0000 (15:43 -0700)]
tgsi_exec: Use C99 functions for min and max instead of open coding
I don't know what I was thinking when I wrote
939bf7a4198 ("tgsi_exec:
Fix NaN behavior of min and max") and
d1c0f62b429 ("tgsi_exec: Fix NaN
behavior of saturate"). I knew that C99 had fmin and fmax... I just
forgot to use them.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
Jason Ekstrand [Fri, 30 Apr 2021 04:05:08 +0000 (23:05 -0500)]
intel/nir: Set lower txs with non-zero LOD
There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes. The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds. Fortunately, not many shaders
actually use textureSize() with LOD.
Shader-db results on Ice Lake:
total instructions in shared programs:
19948537 ->
19948564 (<.01%)
instructions in affected programs: 3859 -> 3886 (0.70%)
helped: 0
HURT: 7
One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>
Jason Ekstrand [Mon, 3 May 2021 18:59:30 +0000 (13:59 -0500)]
intel/fs: Don't use pixel_z for Gen4-5 source_depth_to_render_target
The source_depth_to_render_target flag can get set on old gen4-5 HW in a
few cases which are independent of the app writing gl_FragDepth. It
should be safe to just use fetch_payload_reg in that case instead of
depending in interpolation setup. This fixes a bug with certain very
simple shaders where we might end up not including the depth when we
should have.
While we're here, rework the logic around setting src_depth and add a
comment so it's more clear what's going on.
Fixes:
6d4070f3ddb5 "intel/compiler: add support for fragment coordinate..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10596>
Rob Clark [Mon, 3 May 2021 20:28:21 +0000 (13:28 -0700)]
freedreno/query/acc: Set needs_flush
Somehow this was missed, but when we emit a query start/stop we need
have something that will need to be flushed in the batch.
Detected due to TC assert, but this had the potential to cause problems
in the non-TC case as well.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10599>
Rob Clark [Mon, 3 May 2021 20:27:14 +0000 (13:27 -0700)]
freedreno: Consolidate needs_flush and clearing last_fence
Add a helper to both set batch->needs_flush and clear ctx->last_fence so
that the two related bits of state do not get out of sync.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10599>
Adam Jackson [Fri, 30 Apr 2021 18:43:23 +0000 (14:43 -0400)]
i915c: Add a symlink for i830_dri.so
The gallium driver doesn't support gen2, so let's make it possible to
keep both i915g and i830 drivers installed in parallel.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10554>
Adam Jackson [Fri, 30 Apr 2021 18:26:04 +0000 (14:26 -0400)]
include: Remove unused i810_pci_ids.h
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10554>
Antonio Caggiano [Fri, 9 Apr 2021 15:27:12 +0000 (17:27 +0200)]
panfrost: Meson dependency
Declare a meson dependency for libpanfrost and wrap some key functions
within an extern C block allowing proper compilation by C++ compilers.
Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10462>
Chia-I Wu [Fri, 30 Apr 2021 19:53:41 +0000 (12:53 -0700)]
venus: clean up vn_device_fix_create_info
The extension list should be more correct now.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>
Chia-I Wu [Fri, 30 Apr 2021 19:52:52 +0000 (12:52 -0700)]
venus: add extension check for ANDROID_native_buffer
We only do it on Android for now, to keep the driver working with older
renderers on X11.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>
Chia-I Wu [Fri, 30 Apr 2021 18:05:11 +0000 (11:05 -0700)]
venus: init supported extensions in one place
This also guarantees that physical_dev->extension_spec_versions[X] is
set when extension X is supported.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>
Chia-I Wu [Fri, 30 Apr 2021 16:46:49 +0000 (09:46 -0700)]
venus: refactor vn_physical_device_init_supported_extensions
Native extensions are those do not require direct renderer support.
Passthrough extensions are those require direct renderer support.
Native extensions usually require translation to other extensions that
the renderer supports.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>
Chia-I Wu [Fri, 30 Apr 2021 17:33:32 +0000 (10:33 -0700)]
venus: avoid strcmp for spec version override
Add VN_EXTENSION_TABLE_INDEX for use with VK_ANDROID_native_buffer spec
version override.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>
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