Shraiysh Vaishay [Mon, 20 Jun 2022 14:10:44 +0000 (19:40 +0530)]
[flang][OpenMP] Fix firstprivate with barrier
This patch fixes the unintentional data race in firstprivate
implementation. There is a Read-Write race when one thread tries
to copy the value inside the omp.parallel region while other
thread modifies it from inside the region (using pointers or
some other form of indirect access).
For detailed discussion please refer to [[ https://discourse.llvm.org/t/issues-with-the-current-implementation-of-privatization-in-openmp-with-fortran/62335 | discourse ]].
Reviewed By: kiranchandramohan, peixin, NimishMishra
Differential Revision: https://reviews.llvm.org/D125689
Argyrios Kyrtzidis [Sun, 19 Jun 2022 05:32:57 +0000 (22:32 -0700)]
[Support/BLAKE3] Enable the SIMD implementations for macOS universal builds
To accomodate macOS universal configuration include the assembly files
and `blake3_neon.c` without a CMake check but instead guard their source
with architecture "#ifdef" checks.
Differential Revision: https://reviews.llvm.org/D128132
Craig Topper [Tue, 21 Jun 2022 03:56:20 +0000 (20:56 -0700)]
[RISCV] Add RISCVISD opcode for PseudoAddTPRel.
Use it along with RISCVISD::HI and ADD_LO to avoid emitting
MachineSDNodes during lowering.
Craig Topper [Tue, 21 Jun 2022 03:20:00 +0000 (20:20 -0700)]
Recommit "[RISCV] Enable subregister liveness tracking for RVV."
The failure that caused the previous revert has been fixed
by https://reviews.llvm.org/D126048
Original commit message:
RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of the register allocation.
I've added a command line that can be used to turn it off if it causes compile
time or functional issues. I used the command line to keep the old behavior
for one interesting test case that was testing register allocation.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D128016
Serguei Katkov [Wed, 8 Jun 2022 12:14:20 +0000 (19:14 +0700)]
[AARCH64 folding] Do not fold any copy with NZCV
There is no instruction to fold NZCV, so, just do not do it.
Without the fix the added test case crashes with an assert
"Mismatched register size in non subreg COPY"
Reviewed By: danilaml
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D127294
Kazu Hirata [Tue, 21 Jun 2022 03:26:05 +0000 (20:26 -0700)]
Don't use Optional::hasValue (NFC)
Kazu Hirata [Tue, 21 Jun 2022 03:17:57 +0000 (20:17 -0700)]
Don't use Optional::hasValue (NFC)
Kazu Hirata [Tue, 21 Jun 2022 03:05:16 +0000 (20:05 -0700)]
Don't use Optional::hasValue (NFC)
LLVM GN Syncbot [Tue, 21 Jun 2022 02:57:40 +0000 (02:57 +0000)]
[gn build] Port
a71fe49bb534
Chen Zheng [Fri, 8 Apr 2022 07:16:05 +0000 (03:16 -0400)]
[PowerPC] add a new pass to expand ctr loop pseudos
This patch implements a new way to generate the CTR loops. Now the
intrinsics inserted in hardware loop pass will be mapped to pseudo
instructions and these pseudo instructions will be expanded to CTR
loop or normal compare+branch loop in this post ISEL pass.
Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D122125
Craig Topper [Tue, 21 Jun 2022 01:58:23 +0000 (18:58 -0700)]
[RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.
Use it in place of VSELECT_VL+VRGATHER*_VL.
This simplifies the isel patterns.
Overall, I think trying to match select+op to create masked instructions
in isel doesn't scale. We either need to do it in DAG combine, pre-isel
peepole, or post-isel peephole. I don't yet know which is the right
answer, but for this case it seemed best to be able to request the
masked form directly from lowering.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D128023
chenglin.bi [Mon, 20 Jun 2022 10:27:49 +0000 (18:27 +0800)]
[SelectionDAG][DAGCombiner] Reuse exist node by reassociate
When already have (op N0, N2), reassociate (op (op N0, N1), N2) to (op (op N0, N2), N1) to reuse the exist (op N0, N2)
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D122539
Luo, Yuanke [Tue, 21 Jun 2022 00:10:16 +0000 (08:10 +0800)]
[fastregalloc] Enhance the heuristics for liveout in self loop.
For below case, virtual register is defined twice in the self loop. We
don't need to spill %0 after the third instruction `%0 = def (tied %0)`,
because it is defined in the second instruction `%0 = def`.
1 bb.1
2 %0 = def
3 %0 = def (tied %0)
4 ...
5 jmp bb.1
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D125079
Mogball [Tue, 21 Jun 2022 00:59:05 +0000 (00:59 +0000)]
[mlir][ods] Remove StructAttr
Depends on D127373
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D127375
Phoebe Wang [Tue, 21 Jun 2022 00:40:32 +0000 (08:40 +0800)]
[X86] Make sure SF is updated when optimizing for `jg/jge/jl/jle`
This fixes issue #56103.
Reviewed By: mingmingl
Differential Revision: https://reviews.llvm.org/D128122
Brad Smith [Tue, 21 Jun 2022 01:02:56 +0000 (21:02 -0400)]
[Driver] Pass -X to ld for riscv64-fuchsia
D127826, add support for Fuchsia which uses lld on riscv64
Reviewed By: MaskRay, phosek
Differential Revision: https://reviews.llvm.org/D128134
Jeffrey Tan [Tue, 21 Jun 2022 00:21:18 +0000 (17:21 -0700)]
Fix build break introduced by https://reviews.llvm.org/D127702
Fix build break introduced by https://reviews.llvm.org/D127702
Differential Revision: https://reviews.llvm.org/D128234
archsaxe [Mon, 20 Jun 2022 23:53:03 +0000 (16:53 -0700)]
[test][AlwaysInline]:Correct comment and file check for always-inline.ll
This fixes a useless filecheck and wrong comment for always-inline.ll. Testing
has been done using ninja check-llvm and llvm-lit always-inline.ll --show-all.
Reviewed By: modimo, hoy
Differential Revision: https://reviews.llvm.org/D127815
Pengxuan Zheng [Mon, 20 Jun 2022 22:14:44 +0000 (15:14 -0700)]
[LLD][COFF] Ignore /pdbcompress flag
Microsoft does not seem to document the flag. Ignoring it for now is probably
better than getting an unknown flag error.
Reviewed By: thakis
Differential Revision: https://reviews.llvm.org/D128231
lewuathe [Mon, 20 Jun 2022 23:29:02 +0000 (08:29 +0900)]
[mlir][math] Lower cos,sin to libm
Lower math.cos and math.sin to libm
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D128028
Jeffrey Tan [Fri, 13 May 2022 18:31:23 +0000 (11:31 -0700)]
Support logpoints in lldb-vscode
This patch implements VSCode DAP logpoints feature (also called tracepoint
in other VS debugger).
This will provide a convenient way for user to do printf style logging
debugging without pausing debuggee.
Differential Revision: https://reviews.llvm.org/D127702
Nico Weber [Mon, 20 Jun 2022 23:15:57 +0000 (19:15 -0400)]
Revert "[lld-macho] Show source information for undefined references"
This reverts commit
cd7624f15369f0d395c1edee1a0b9592083d2fe0.
See https://reviews.llvm.org/D128184#3597534
Daniel Bertalan [Mon, 20 Jun 2022 22:49:42 +0000 (18:49 -0400)]
[lld-macho] Show source information for undefined references
The error used to look like this:
ld64.lld: error: undefined symbol: _foo
>>> referenced by /path/to/bar.o:(symbol _baz+0x4)
If DWARF line information is available, we now show where in the source
the references are coming from:
ld64.lld: error: unreferenced symbol: _foo
>>> referenced by: bar.cpp:42 (/path/to/bar.cpp:42)
>>> /path/to/bar.o:(symbol _baz+0x4)
Differential Revision: https://reviews.llvm.org/D128184
Kazushi (Jam) Marukawa [Sat, 18 Jun 2022 14:16:38 +0000 (23:16 +0900)]
[Clang][VE] Add missing intrinsics
Add missing intrinsics and tests for them. An expanding macro
from _vel_pack_f32p to __builtin_ve_vl_pack_f32p and others is
already defined in clang/lib/Headers/velintrin.h.
Reviewed By: efocht
Differential Revision: https://reviews.llvm.org/D128120
Maksim Panchenko [Mon, 20 Jun 2022 21:20:22 +0000 (14:20 -0700)]
[BOLT][TEST] Fix stack alignment in section-reloc-with-addend.s
Misaligned stack can cause a runtime crash.
Reviewed By: Amir
Differential Revision: https://reviews.llvm.org/D128227
Martin Storsjö [Mon, 20 Jun 2022 21:19:09 +0000 (00:19 +0300)]
[lldb] Fix building with GCC 7
Ruiling Song [Wed, 9 Mar 2022 14:12:42 +0000 (22:12 +0800)]
[AMDGPU] Mark GFX11 dual source blend export as strict-wqm
The instructions that generate the source of dual source blend export
should run in strict-wqm. That is if any lane in a quad is active,
we need to enable all four lanes of that quad to make the shuffling
operation before exporting to dual source blend target work correctly.
Differential Revision: https://reviews.llvm.org/D127981
Piotr Sobczak [Thu, 11 Mar 2021 16:52:11 +0000 (17:52 +0100)]
[AMDGPU] Tag GFX11 LDS loads as using strict_wqm
LDS_PARAM_LOAD and LDS_DIRECT_LOAD use EXEC per quad
(if any pixel is enabled in the quad, data is written
to all 4 pixels/threads in the quad).
Tag LDS_PARAM_LOAD and LDS_DIRECT_LOAD as using strict_wqm
to enforce this and avoid lane clobbering issues.
Note that only the instruction itself is tagged.
The implicit uses of these do not need to be set WQM.
The reduces unnecessary WQM calculation of M0.
Differential Revision: https://reviews.llvm.org/D127977
Jay Foad [Thu, 16 Jun 2022 14:02:06 +0000 (15:02 +0100)]
[AMDGPU] Add support for GFX11 LDSDIR hazards
Detect LDS direct WAR/WAW hazards and compute values for
wait_vdst (va_vdst) parameter. Where appropriate this
raises wait_vdst from the default 0 to allow concurrent
issue of LDS direct with VALU execution.
Also detect LDS direct versus VMEM source VGPR hazards
and insert vm_vsrc=0 waits using s_waitcnt_depctr.
Differential Revision: https://reviews.llvm.org/D127963
Philip Reames [Mon, 20 Jun 2022 20:16:15 +0000 (13:16 -0700)]
[BasicTTI] Return Invalid for scalable vectors reaching getScalarizationOverhead
If we would scalarize a fixed vector, we know we can't do so for a scalable one. However, there's no need to crash, we can instead simply return a invalid cost which will work its way through the computation (since invalid is sticky), and the client should bail out.
Sorry for the lack of test here. The particular codepath I saw this reached on was the result of another bug.
Amir Ayupov [Mon, 20 Jun 2022 19:58:31 +0000 (12:58 -0700)]
[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE
Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.
In effect, this makes debugging generated `getOperandType` possible.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D127931
Philip Reames [Mon, 20 Jun 2022 19:13:24 +0000 (12:13 -0700)]
[RISCV] Fix crash when costing scalable gather/scatter of pointer
This was a bug introduced in d764aa. A pointer type is not a primitive type, and thus we were ending up dividing by zero when computing VLMax.
Differential Revision: https://reviews.llvm.org/D128219
Mehdi Chinoune [Mon, 20 Jun 2022 19:39:00 +0000 (12:39 -0700)]
[CMake][MSVC] Compile with `/permissive-`
This turns off a bunch of non-standard behaviors in MSVC. LLVM, as a
portable codebase, should build correctly without those behaviors. Note
that `/permissive-` implies `/Zc:strictStrings` and `/Zc:rvalueCast`.
See also:
https://docs.microsoft.com/en-us/cpp/build/reference/permissive-standards-conformance
Differential Revision: https://reviews.llvm.org/D125263
Amir Ayupov [Mon, 20 Jun 2022 19:40:52 +0000 (12:40 -0700)]
Revert "[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE"
This reverts commit
4cd416193cc126355a22b2c9e5c1df3a49b59e50.
Florian Hahn [Mon, 20 Jun 2022 19:33:45 +0000 (21:33 +0200)]
[ConstraintElimination] Move logic to get a constraint to helper (NFC).
Nemanja Ivanovic [Mon, 20 Jun 2022 13:45:24 +0000 (08:45 -0500)]
[PowerPC] Disable automatic generation of STXVP
There are instances where using paired vector stores leads to significant
performance degradation due to issues with store forwarding.To avoid falling
into this trap with compiler - generated code, we will not emit these
instructions unless the user requests them explicitly(with a builtin or by
specifying the option).
Reviewed By : lei, amyk, saghir
Differential Revision: https://reviews.llvm.org/D127218
Amir Ayupov [Mon, 20 Jun 2022 19:23:39 +0000 (12:23 -0700)]
[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE
Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.
In effect, this makes debugging generated `getOperandType` possible.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D127931
Jakob Johnson [Fri, 17 Jun 2022 20:37:07 +0000 (13:37 -0700)]
Add LoadTraceFromFile to SBDebugger and SBTrace
Add trace load functionality to SBDebugger via the `LoadTraceFromFile` method.
Update intelpt test case class to have `testTraceLoad` method so we can take advantage of
the testApiAndSB decorator to test both the CLI and SB without duplicating code.
Differential Revision: https://reviews.llvm.org/D128107
Kazu Hirata [Mon, 20 Jun 2022 18:49:10 +0000 (11:49 -0700)]
Don't use Optional::hasValue (NFC)
Kazu Hirata [Mon, 20 Jun 2022 18:33:56 +0000 (11:33 -0700)]
Don't use Optional::hasValue (NFC)
Kazu Hirata [Mon, 20 Jun 2022 18:22:37 +0000 (11:22 -0700)]
[mlir] Don't use Optional::hasValue (NFC)
David Green [Mon, 20 Jun 2022 18:11:57 +0000 (19:11 +0100)]
[AArch64] Known bits for AArch64ISD::DUP
An AArch64ISD::DUP is just a splat, where the known bits for each lane
are the same as the input. This teaches that to computeKnownBitsForTargetNode.
Problems arise for constants though, as a constant BUILD_VECTOR can be
lowered to an AArch64ISD::DUP, which SimplifyDemandedBits would then
turn back into a constant BUILD_VECTOR leading to an infinite cycle.
This has been prevented by adding a isTargetCanonicalConstantNode node
to prevent the conversion back into a BUILD_VECTOR.
Differential Revision: https://reviews.llvm.org/D128144
Kazu Hirata [Mon, 20 Jun 2022 17:51:34 +0000 (10:51 -0700)]
[clang] Don't use Optional::hasValue (NFC)
Simon Pilgrim [Mon, 20 Jun 2022 17:16:49 +0000 (18:16 +0100)]
[X86] LowerINSERT_VECTOR_ELT - always lower v32i8/v16i16 allones insertions on AVX1 as OR ops
v32i8/v16i16 blend shuffles on AVX1 will expand to OR(AND,ANDN) patterns which can be easily broken by other combines
Michał Górny [Fri, 17 Jun 2022 10:25:26 +0000 (12:25 +0200)]
[lldb] [test] Fix test_platform_file_fstat to account for negative ints
Fix test_platform_file_fstat to correctly truncate/max out the expected
value when GDB Remote Serial Protocol specifies a value as an unsigned
integer but the underlying platform type uses a signed integer.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D128042
Michał Górny [Fri, 17 Jun 2022 09:45:49 +0000 (11:45 +0200)]
[lldb] [test] Make AVX/MPX register tests more robust and fix on BSD
Make the AVX/MPX register tests more robust by checking for the presence
of actual registers rather than register sets. Account for the option
that the respective registers are defined but not available, as is
the case on FreeBSD and NetBSD. This fixes test regression on these
platforms.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D128041
Michał Górny [Fri, 17 Jun 2022 07:41:47 +0000 (09:41 +0200)]
[lldb] [test] Disable gmodules testing on FreeBSD
The -gmodule tests currently fail on FreeBSD due to include bugs:
https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=264730
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D128034
Michał Górny [Thu, 9 Jun 2022 16:54:50 +0000 (18:54 +0200)]
[lldb] [llgs] Refactor SendStopReasonForState for multiprocess
Refactor GDBRemoteCommunicationServerLLGS::SendStopReasonForState()
to accept process as an argument rather than hardcoding
m_current_process, in order to make it work correctly for multiprocess
scenarios.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D127497
Michał Górny [Tue, 7 Jun 2022 15:04:01 +0000 (17:04 +0200)]
[lldb] [llgs] Refactor SendStopReplyPacketForThread for multiprocess
Refactor SendStopReplyPacketForThread() to accept process instance
as a parameter rather than use m_current_process. This future-proofs
it for multiprocess support.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D127289
Philip Reames [Mon, 20 Jun 2022 17:36:53 +0000 (10:36 -0700)]
[BasicTTI] Allow generic handling of scalable vector fshr/fshl
This change removes an explicit scalable vector bailout for fshl and fshr. This bailout was added in
60e4698b9aba8, when sinking a unconditional bailout for all intrinsics into selected cases. Its not clear if the bailout was originally unneeded, or if our cost model infrastructure has simply matured in the meantime. Either way, the generic code appears to handle scalable vectors without issue.
Note that the RISC-V cost model changes here aren't particularly interesting. They do probably better match the current lowering, but the main point is to have coverage of the BasicTTI path and simply show lack of crashing.
AArch64 costing was changed to preserve legacy behavior. There will most likely be an upcoming change to use the generic costs there too, but I didn't want to make that change not being particularly familiar with the target.
Differential Revision: https://reviews.llvm.org/D127680
Kazu Hirata [Mon, 20 Jun 2022 17:38:12 +0000 (10:38 -0700)]
[llvm] Don't use Optional::hasValue (NFC)
Stanislav Gatev [Mon, 20 Jun 2022 11:02:51 +0000 (11:02 +0000)]
[clang][dataflow] Extend flow condition in the body of a do/while loop
Extend flow condition in the body of a do/while loop.
Differential Revision: https://reviews.llvm.org/D128183
Reviewed-by: gribozavr2, xazax.hun
Arthur Eubanks [Mon, 20 Jun 2022 17:26:47 +0000 (10:26 -0700)]
Revert "[GlobalOpt] Perform store->dominated load forwarding for stored once globals"
This reverts commit
6f348b146b69a50d5fb1b9fbfd14bc1d204e45c4.
Am seeing internal test failures plus a linux kernel breakage reported due to this.
Arthur Eubanks [Mon, 20 Jun 2022 17:25:10 +0000 (10:25 -0700)]
Revert "[GlobalOpt] Preserve CFG analyses"
This reverts commit
cc65f3e167144c39ef9ca3a69c3148b71dcab496.
Causes crashes: https://github.com/llvm/llvm-project/issues/56131
Philip Reames [Mon, 20 Jun 2022 17:11:06 +0000 (10:11 -0700)]
[RISCV] Delete unexercised VL=0 vsetvli compatibility logic
The code being removed is technically correct; if we end up with two VL=0 instructions next to each other, we can avoid a state transition if the second is a scalar move. However, since both ops are also nops, we should simply delete them instead. As such, this compatibility rule simply complicates the code for no purpose.
David Candler [Mon, 20 Jun 2022 15:03:59 +0000 (16:03 +0100)]
[ConstantFolding] Respect denormal handling mode attributes when folding instructions
Depending on the environment, a floating point instruction should
treat denormal inputs as zero, and/or flush a denormal output to zero.
Denormals are not currently accounted for when an instruction gets
folded to a constant, which can lead to differences in output between
a folded and a unfolded instruction when running on the target. The
denormal handling mode can be set by the function level attribute
denormal-fp-math, which this patch uses to determine whether any
denormal inputs to or outputs from folding should be zero, and that
the sign is set appropriately.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D116952
Fraser Cormack [Mon, 20 Jun 2022 10:03:19 +0000 (11:03 +0100)]
Update usage comments in Printable.h. NFC.
The example wouldn't compile, and used an invalid case style for a
function.
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D128176
Guillaume Chatelet [Mon, 20 Jun 2022 15:02:59 +0000 (15:02 +0000)]
[Alignment] Remove alignTo version taking a MaybeAlign
Guillaume Chatelet [Mon, 20 Jun 2022 15:01:41 +0000 (15:01 +0000)]
[NFC] Simplify alignment code in MemorySanitizer
Guillaume Chatelet [Mon, 20 Jun 2022 15:00:45 +0000 (15:00 +0000)]
[NFC] Simplify alignment code in CoroFrame
Guillaume Chatelet [Mon, 20 Jun 2022 14:48:53 +0000 (14:48 +0000)]
[NFC] Simplify code
Florian Hahn [Mon, 20 Jun 2022 15:08:35 +0000 (17:08 +0200)]
[ConstraintElimination] Move logic to add constraint to helper (NFC).
Krzysztof Drewniak [Fri, 17 Jun 2022 18:31:05 +0000 (18:31 +0000)]
[mlir][ROCDL] Define MLIR wrappers around new MFMA intrinsics
In order to support newer hardware, define wrappers around MFMA
intrinsics that have not previously been exposed in the ROCDL dialect.
A `amdgpu.mfma` wrapper around these instructions is in development
and will provide a more user-friendly interface to them.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D128079
Krzysztof Drewniak [Fri, 17 Jun 2022 20:39:59 +0000 (20:39 +0000)]
[mlir][Arith] Make --unsigned-when-equivalent use dialect conversion
Reviewed By: Mogball
Differential Revision: https://reviews.llvm.org/D128096
Philip Reames [Mon, 20 Jun 2022 14:46:46 +0000 (07:46 -0700)]
[RISCV] Fold prepass back into InsertVSETVLI data flow [nfc-ish]
When working through correctness issues in this pass, I moved a number of transforms which were phrased as mutating prior vsetvli instructions out of the main data flow because mutating prior instructions can invalidate the running dataflow results in subtle ways. We ended up creating both a prepass and a post-pass.
After consideration, I believe the prepass to be redundant, and this change removes it by folding it back into the data flow via a key conceptual change. Instead of phrasing the mutations on instructions, we can phrase them on abstract states. This avoids the dataflow inconsistency problem mentioned above by simply propagating the potential change forward, and thus reflecting its results in the dataflow. Critically, we do so without modifying existing VSETVLI instructions; some of the data flow steps include non-local IR analysis.
Compile time wise, this removes a linear pass, but has the potential to increase the number of iterations for the data flow to converge. That's not a algorithmic complexity change, the needVSETVLI mechanism has the same effect. In practice, I don't see this triggering more iterations, so I think it's likely to be a net win overall. (I didn't do any careful analysis here; just an impression from glancing at a couple tests.)
This has the potential to produce better results, so this isn't strictly speaking NFC.
Differential Revision: https://reviews.llvm.org/D127870
Jan Svoboda [Mon, 20 Jun 2022 14:56:03 +0000 (16:56 +0200)]
[support][ci] Fix modular build on GreenDragon
This is to fix the following error on https://green.lab.llvm.org/green/job/clang-stage2-Rthinlto:
BranchProbability.h:236:34: error: declaration of 'distance' must be imported from module 'std.iterator.__iterator.distance' before it is required
Philip Reames [Mon, 20 Jun 2022 14:41:18 +0000 (07:41 -0700)]
[RISCV] Assert initial load/store SEW is the EEW
In D127983, I had flipped from using the computed EEW to using the SEW value pulled from the VSETVLI when checking compatibility. This wasn't intentional, though thankfully it appears to be a non-functional difference. The new code does make a unchecked assumption that the initial SEW operand on the load/store is the EEW. This patch clarifies the assumption, and adds an assert to make sure this remains true.
Differential Revision: https://reviews.llvm.org/D128085
Kadir Cetinkaya [Mon, 20 Jun 2022 13:23:32 +0000 (15:23 +0200)]
[clangd] Handle initializers that contain =
Differential Revision: https://reviews.llvm.org/D128197
Florian Hahn [Mon, 20 Jun 2022 14:25:53 +0000 (16:25 +0200)]
[ConstraintElimination] Move StackEntry up, to allow use earlier (NFC).
David Candler [Mon, 20 Jun 2022 14:24:27 +0000 (15:24 +0100)]
[ConstantFolding] Pre-commit tests showing denormal handling during folding
These tests demonstrate cases where the constant produced by folding
a floating point instruction should differ based on the denormal
handling mode set in function attributes.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D125807
Guillaume Chatelet [Mon, 20 Jun 2022 14:09:55 +0000 (14:09 +0000)]
[NFC] Implement alignTo with skew in terms of alignTo
Valentin Clement [Mon, 20 Jun 2022 13:43:44 +0000 (15:43 +0200)]
[flang][NFC] Unify todo messages
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D128186
Co-authored-by: Peter Steinfeld <psteinfeld@nvidia.com>
Jay Foad [Mon, 20 Jun 2022 13:30:02 +0000 (14:30 +0100)]
[AMDGPU] Reorder cases. NFC.
Ye Luo [Mon, 20 Jun 2022 13:29:08 +0000 (08:29 -0500)]
[libomptarget] Make libomptarget.devicertl.a built in all cases.
Make libomptarget.device.a built when using -DLLVM_ENABLE_PROJECTS=openmp
Use add_custom_command.
Reviewed By: jhuber6
Differential Revision: https://reviews.llvm.org/D128130
David Sherwood [Tue, 14 Jun 2022 15:59:40 +0000 (16:59 +0100)]
[AArch64][SME] Add the zero intrinsic
The SME zero instruction takes a mask as an input declaring which
64-bit element tiles should be zeroed. There is a 1:1 mapping
between the zero intrinsic and the instruction, however we also
want to make the register allocator aware that some tile
registers are being written to.
We can actually just use the custom inserter for a pseudo instruction
to correctly mark all the appropriate registers in the mask as
implicitly defined by the operation.
Differential Revision: https://reviews.llvm.org/D127843
Jay Foad [Wed, 10 Mar 2021 09:13:43 +0000 (09:13 +0000)]
[AMDGPU] Increase instruction cache line size to 128 bytes for GFX11
Differential Revision: https://reviews.llvm.org/D128189
Jay Foad [Mon, 20 Jun 2022 13:08:38 +0000 (14:08 +0100)]
[AMDGPU] Remove a duplicate atomic fadd pattern
This was left over after D124538.
Jonas Paulsson [Mon, 20 Jun 2022 12:20:03 +0000 (14:20 +0200)]
[SystemZ] Remove unnecessary casts to SystemZInstrInfo (NFC).
Review: Ulrich Weigand
Jonas Paulsson [Mon, 20 Jun 2022 12:16:42 +0000 (14:16 +0200)]
[SystemZ] Remove stray enum value in SystemZInstrInfo.h (NFC).
Review: Ulrich Weigand
Nabeel Omer [Mon, 20 Jun 2022 10:24:13 +0000 (10:24 +0000)]
[SLP] Add a test for llvm.powi.*
This patch introduces a test for the issue discovered in #53887.
Differential Revision: https://reviews.llvm.org/D128178
Joachim Priesner [Mon, 20 Jun 2022 12:30:02 +0000 (13:30 +0100)]
[clang-tidy] bugprone-argument-comment: Ignore calls to user-defined literals
Without this change, code such as "f(/*param=*/1_op)" will check the
comment twice, once for the parameter of f (correct) and once for
the parameter of operator""_op (likely incorrect). The change removes
only the second check.
Reviewed By: njames93, LegalizeAdulthood
Differential Revision: https://reviews.llvm.org/D125885
Jay Foad [Mon, 20 Jun 2022 12:13:45 +0000 (13:13 +0100)]
[AMDGPU] Add GFX11 coverage to one more test
Kristof Beyls [Fri, 3 Jun 2022 09:31:16 +0000 (11:31 +0200)]
[docs] More clearly document that the CoC applies to online sync-ups and office hours.
* Also removes the code of conduct document listed as a "proposal".
Fixes #55430
Differential Revision: https://reviews.llvm.org/D126954
Michał Górny [Mon, 6 Jun 2022 16:17:59 +0000 (18:17 +0200)]
[lldb] [llgs] Include process ID in stop responses
Include the process identifier in the `T` stop responses when
multiprocess extension is enabled (i.e. prepend it to the thread
identifier). Use the exposed identifier to simplify the fork-and-follow
tests.
The LLDB client accounts for the possible PID since the multiprocess
extension support was added in
b601c6719226fb83c43dae62a581e5ee08bfb169.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D127192
Michał Górny [Mon, 6 Jun 2022 13:21:12 +0000 (15:21 +0200)]
[lldb] [llgs] Include process id in W/X stop reasons
Include the process identifier in W/X stop reasons when multiprocess
extensions are enabled.
The LLDB client does not support process identifiers there at the moment
but it parses packets in such a way that their presence does not cause
any problems.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D127191
Ben Dunbobbin [Mon, 20 Jun 2022 10:43:38 +0000 (11:43 +0100)]
[windows][support] Improve backtrace emitted in crash report without llvm-symbolizer
Currently the backtrace emitted on windows when llvm-symbolizer is not
available includes addresses which cannot be easily decoded because
the addresses have the containing module's run-time base address added
into them, but we don't know what those base addresses are. This
change emits a module offset rather than an address.
There are a couple of related changes which were included as a result
of the review discussion for this patch:
- I have also removed the parameter printing as it adds noise to the
dump and doesn't seem useful.
- I have added the exception code to the backtrace.
Differential Review: https://reviews.llvm.org/D127915
Dmitry Preobrazhensky [Mon, 20 Jun 2022 11:21:25 +0000 (14:21 +0300)]
[AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes
Fix bugs https://github.com/llvm/llvm-project/issues/56091, https://github.com/llvm/llvm-project/issues/56065.
Differential Revision: https://reviews.llvm.org/D128075
Florian Hahn [Mon, 20 Jun 2022 11:19:27 +0000 (13:19 +0200)]
[LoopPeel] Forget SCEV for updated exit phi values.
LoopPeel add new incoming values to exit phi nodes which can change the
SCEV for the phi after
20d798bd47ec51.
Forget SCEVs for such phis.
Fixes #56044.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D128164
Guillaume Chatelet [Mon, 20 Jun 2022 09:33:09 +0000 (09:33 +0000)]
[Alignment] Use 'previous()' method instead of scalar division
This is in preparation of integration with D128052.
Differential Revision: https://reviews.llvm.org/D128169
Pavel Labath [Mon, 20 Jun 2022 10:58:27 +0000 (12:58 +0200)]
[lldb] Relax backtrace checks in TestDyldLaunchLinux
Newer versions of glibc (2.34) have an extra frame inside the `raise`
function.
Valentin Clement [Mon, 20 Jun 2022 10:32:23 +0000 (12:32 +0200)]
[flang][NFC] Fix file name typos
Mirko Brkusanin [Mon, 20 Jun 2022 09:57:07 +0000 (11:57 +0200)]
[AMDGPU][GlobalISel] Legalize G_FSUB for s16
Differential Revision: https://reviews.llvm.org/D128066
Alex Bradbury [Mon, 20 Jun 2022 09:56:55 +0000 (10:56 +0100)]
[WebAssembly][NFC] Update reftype and table tests to use opaque pointers
Differential Revision: https://reviews.llvm.org/D126535
Guillaume Chatelet [Mon, 20 Jun 2022 09:47:18 +0000 (09:47 +0000)]
[NFC][Alignment] Remove dead code
David Green [Mon, 20 Jun 2022 09:08:21 +0000 (10:08 +0100)]
[ARM] Allow distributing postinc with PHI uses
Although this doesn't usually come up, we can have uses of the
BaseAccess of a distributed postinc being a PHI. This doesn't need the
usual dominance check as we will dominate along the phi edge, allowing
us to still create a postinc load/store.
Differential Revision: https://reviews.llvm.org/D127676
Sven van Haastregt [Mon, 20 Jun 2022 09:07:34 +0000 (10:07 +0100)]
[OpenCL][TableGen] Fix type extension guard emission
For certain cases (such as for the double subtype of AGenType), the
OpenCLBuiltinFileEmitterBase would not emit the extension #if-guard.
Fix that by looking at the extension of the actual type instead of the
argument type (which could be a GenType that does not carry any
extension information).
Alex Richardson [Mon, 20 Jun 2022 08:57:12 +0000 (08:57 +0000)]
[libunwind] Ensure test/libunwind_01.pass is not completely inlined
By adding noinline and calling fprintf before returning we ensure that
every function will have a distinct call frame and that the return address
will always be saved instead of saving the target in main as the result.
Before this change all backtraces were always backtrace -> main -> _start,
i.e. always exactly three entries. This happenend because all calls were
inlined in main() and the test just happenend to pass because there is at
least _start before main.
I found this while fixing some bugs in libunwind for CHERI and noticed that
the test was passing even though the code was completely broken.
Obtained from: https://github.com/CTSRD-CHERI/llvm-project
Reviewed By: #libunwind, ldionne, MaskRay
Differential Revision: https://reviews.llvm.org/D126611
Jan Svoboda [Wed, 8 Jun 2022 11:40:14 +0000 (13:40 +0200)]
[clang][sema] Generate builtin operator overloads for (volatile) _Atomic types
We observed a failed assert in overloaded compound-assignment operator resolution:
```
Assertion failed: (Result.isInvalid() && "C++ binary operator overloading is missing candidates!"), function CreateOverloadedBinOp, file SemaOverload.cpp, line 13944.
...
frame #4: clang` clang::Sema::CreateOverloadedBinOp(..., Opc=BO_OrAssign, ..., PerformADL=true, AllowRewrittenCandidates=false, ...) at SemaOverload.cpp:13943
frame #5: clang` BuildOverloadedBinOp(..., Opc=BO_OrAssign, ...) at SemaExpr.cpp:15228
frame #6: clang` clang::Sema::BuildBinOp(..., Opc=BO_OrAssign, ...) at SemaExpr.cpp:15330
frame #7: clang` clang::Sema::ActOnBinOp(..., Kind=pipeequal, ...) at SemaExpr.cpp:15187
frame #8: clang` clang::Parser::ParseRHSOfBinaryExpression(..., MinPrec=Assignment) at ParseExpr.cpp:629
frame #9: clang` clang::Parser::ParseAssignmentExpression(..., isTypeCast=NotTypeCast) at ParseExpr.cpp:176
frame #10: clang` clang::Parser::ParseExpression(... isTypeCast=NotTypeCast) at ParseExpr.cpp:124
frame #11: clang` clang::Parser::ParseExprStatement(...) at ParseStmt.cpp:464
```
A simple reproducer is:
```
_Atomic unsigned an_atomic_uint;
enum { an_enum_value = 1 };
void enum1() { an_atomic_uint += an_enum_value; }
```
This patch fixes the issue by generating builtin operator overloads for (volatile) _Atomic types.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D125349
Guillaume Chatelet [Sat, 18 Jun 2022 14:34:11 +0000 (14:34 +0000)]
[NFC][Alignment] Remove max functions between Align and MaybeAlign
`llvm::max(Align, MaybeAlign)` and `llvm::max(MaybeAlign, Align)` are
not used often enough to be required. They also make the code more opaque.
Differential Revision: https://reviews.llvm.org/D128121
Guillaume Chatelet [Mon, 20 Jun 2022 08:02:09 +0000 (08:02 +0000)]
[Alignment] Remove multiply by MaybeAlign