Timm Bäder [Mon, 31 Oct 2022 11:58:27 +0000 (12:58 +0100)]
[clang][Interp][NFC] Avoid a getSource() call in the common case
In the common (successful) case, we don't need the getSource() call, so
move it to the two if statement bodies instead.
Nathan Ridge [Mon, 31 Oct 2022 07:22:29 +0000 (03:22 -0400)]
[clangd] Fix a small inconsistency in system-include-extractor.test
Also add an explanatory comment
Differential Revision: https://reviews.llvm.org/D137056
Adrian Kuegel [Mon, 7 Nov 2022 08:23:07 +0000 (09:23 +0100)]
[mlir] Apply two ClangTidy findings.
- argument name 'isLastOutput' in comment does not match parameter name
'hasOutput'.
- override is redundant since the function is already declared 'final'.
Timm Bäder [Sun, 30 Oct 2022 09:05:42 +0000 (10:05 +0100)]
[clang][Interp][NFCI] Cleanup emitConst()
Before, when emitting a regular integer constant, we went:
Int -> APInt -> int -> emit
Fix this by using regular integer constants in emitConst() and instead
converting APInt to those once.
Serguei Katkov [Mon, 7 Nov 2022 07:37:54 +0000 (14:37 +0700)]
[Greedy RegAlloc] Add a test for single block split with statepoint uses.
The test shows redundant usage of callee saved register in case
basic block has only one non-statepoint use.
Timm Bäder [Sat, 22 Oct 2022 07:27:21 +0000 (09:27 +0200)]
[clang][Interp][NFC] Handle discarded ArraySubscriptExprs
This is not exactly a common case, so just pop the pointer at the end if
necessary.
Tobias Hieta [Mon, 7 Nov 2022 07:34:40 +0000 (08:34 +0100)]
[clang-format] Handle object instansiation in if-statements
Before this patch code like this:
```
if (Class* obj{getObject()}) { }
```
would be mis-formated since the * would be annotated as a
binaryoperator.
This patch changes the * to become a PointerOrReference instead
and fixes the formatting issues.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D137327
Timm Bäder [Fri, 21 Oct 2022 13:43:42 +0000 (15:43 +0200)]
[clang][Interp][NFC] Make InitField() not pop the pointer
This was confusing. InitElem peeks a pointer, while InitElemPop will
pop the pointer. However, for fields, InitField would pop the pointer
and no InitFieldPop exists. At least make InitField and InitElem behave
the same.
Chen Zheng [Mon, 7 Nov 2022 07:03:48 +0000 (02:03 -0500)]
[PowerPC][NFC] use script to generate check lines
Timm Bäder [Fri, 21 Oct 2022 10:26:05 +0000 (12:26 +0200)]
[clang][Interp][NFC] Use StorePop for assignments with DiscardResult
If we don't need the result anyway, use StorePop, instead of a Store+Pop
combination. That way we save one instruction and not using the result
is the common case anyway.
Timm Bäder [Thu, 13 Oct 2022 08:09:36 +0000 (10:09 +0200)]
[clang][Interp] Support pointer arithmethic in binary operators
Differential Revision: https://reviews.llvm.org/D135858
Timm Bäder [Mon, 7 Nov 2022 06:22:30 +0000 (07:22 +0100)]
[clang][Interp] Add a test case for #58754
This works in the new interpreter but is rejected by the current one.
Make sure it keeps working.
Matt Arsenault [Sat, 5 Nov 2022 18:23:27 +0000 (11:23 -0700)]
AMDGPU: Fix faulty divergence analysis tests
These were supposed to be checking that atomics were treated
as divergence sources. However, they were using function arguments
which are always treated as divergent, so they could have
been found divergent for the wrong reason.
Matt Arsenault [Sat, 5 Nov 2022 18:20:41 +0000 (11:20 -0700)]
AMDGPU: Fix missing divergence tests for csub intrinsics
Matt Arsenault [Sat, 5 Nov 2022 19:33:43 +0000 (12:33 -0700)]
GlobalISel: Pass through AA metadata for target memory intrinsics
The corresponding change for the DAG was done in
fa4aac7335ac7ecabbb634d134bd4897783bf62b
Matt Arsenault [Sat, 5 Nov 2022 19:16:56 +0000 (12:16 -0700)]
AMDGPU: Add new test for target intrinsic aliasing metadata
The intrinsic used for the test will soon be removed, so move
the test to use another one.
Replaces test added in
fa4aac7335ac7ecabbb634d134bd4897783bf62b
Timm Bäder [Fri, 4 Nov 2022 10:55:18 +0000 (11:55 +0100)]
[clang][Interp][NFC] Remove an unused include
And an unnecessary private marker.
Kazu Hirata [Mon, 7 Nov 2022 05:09:20 +0000 (21:09 -0800)]
[clang] Use llvm::reverse (NFC)
Kazu Hirata [Mon, 7 Nov 2022 04:48:55 +0000 (20:48 -0800)]
[clang-tidy] Use structured bindings (NFC)
Kazu Hirata [Mon, 7 Nov 2022 04:04:53 +0000 (20:04 -0800)]
[Sema] Use llvm::is_contained (NFC)
Kazu Hirata [Mon, 7 Nov 2022 03:58:51 +0000 (19:58 -0800)]
[flang] Use llvm::is_contained (NFC)
Kazu Hirata [Mon, 7 Nov 2022 03:56:15 +0000 (19:56 -0800)]
[mlir] Use llvm::is_contained (NFC)
Kazu Hirata [Mon, 7 Nov 2022 03:53:02 +0000 (19:53 -0800)]
[PowerPC] Use llvm::is_contained (NFC)
Sean Cross [Mon, 7 Nov 2022 03:02:08 +0000 (19:02 -0800)]
[builtins] Check __SIZEOF_INT128__ for CRT_HAS_128BIT
When building libstd on Rust for a riscv32 target, `compiler-rt` fails to build with the following error:
```
running: "riscv-none-elf-gcc" "-O3" "-ffunction-sections" "-fdata-sections" "-fPIC" "-march=rv32imac" "-mabi=ilp32" "-mcmodel=medany" "-fno-builtin" "-fvisibility=hidden" "-ffreestanding" "-fomit-frame-pointer" "-ffile-prefix-map=E:\\Code\\Xous\\rust-next\\src\\llvm-project\\compiler-rt=." "-DVISIBILITY_HIDDEN" "-o" "E:\\Code\\Xous\\rust-next\\target\\riscv32imac-unknown-xous-elf\\release\\build\\compiler_builtins-
b0d7dd25c6999904\\out\\absvdi2.o" "-c" "E:\\Code\\Xous\\rust-next\\src\\llvm-project\\compiler-rt\\lib/builtins\\absvdi2.c"
cargo:warning=In file included from E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\int_lib.h:99,
cargo:warning= from E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\absvdi2.c:13:
cargo:warning=E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\int_types.h:79:1: error: unable to emulate 'TI'
cargo:warning= 79 | typedef int ti_int __attribute__((mode(TI)));
cargo:warning= | ^~~~~~~
cargo:warning=E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\int_types.h:80:1: error: unable to emulate 'TI'
cargo:warning= 80 | typedef unsigned tu_int __attribute__((mode(TI)));
cargo:warning= | ^~~~~~~
exit code: 1
```
This is because 128-bit support is gated on the `__riscv` compiler macro which is valid for both rv32 and rv64. However, only rv64 has 128-bit support, so this fails when building for rv32.
Add a check for `__SIZEOF_INT128__` to ensure that 128-bit support is only enabled on targets that support it.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D137485
wangpc [Mon, 7 Nov 2022 02:40:19 +0000 (10:40 +0800)]
[RISCV] Support -mcpu/mtune=native
We may need hosted Clang/LLVM to compile and `getHostCpuName`
can be used for native detection.
Tests are added in riscv-cpus.c just like what AArch64/PPC
have done.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D136930
Fangrui Song [Mon, 7 Nov 2022 01:38:57 +0000 (17:38 -0800)]
[test] Canonicalize PowerPC detection macros to __powerpc__
Fangrui Song [Mon, 7 Nov 2022 01:34:04 +0000 (17:34 -0800)]
[builtins] Canonicalize PowerPC detection macros to __powerpc__
The lowercase __ppc__ is not defined by Linux GCC, therefore it lures
users to write code which is not portable to GCC. Migrate to __powerpc__ in
preparation for undefining __ppc__. __powerpc__ is much more common than
__PPC__.
Fangrui Song [Mon, 7 Nov 2022 01:29:44 +0000 (17:29 -0800)]
Canonicalize PowerPC detection macros to __powerpc__
Fangrui Song [Mon, 7 Nov 2022 00:16:50 +0000 (16:16 -0800)]
[PowerPC] Replace __ppc64__ with __powerpc64__
The lowercase __ppc64__ is not defined by non-darwin GCC, therefore it lures
users to write code which is not portable to GCC. Migrate to __powerpc64__ in
preparation for undefining __ppc64__. __powerpc64__ is much more common than
__PPC64__.
Andreas Hollandt [Sun, 6 Nov 2022 23:13:32 +0000 (15:13 -0800)]
[ELF] Add gdb index time trace
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D135659
Zhouyi Zhou [Sun, 6 Nov 2022 23:07:42 +0000 (15:07 -0800)]
Add boundary check for ASTUnresolvedSet::erase
When compile following code with clang (Debug build), Assertion will be triggered.
```
struct A
{
struct Nested {};
operator Nested*() {return 0;};
};
struct B : A
{
using A::operator typename A::Nested*;
operator typename A::Nested *() {
struct A * thi = this;
return *thi;
};
};
```
The assertion fail is caused by: `void erase(unsigned I) { Decls[I] = Decls.pop_back_val(); }` when size of `Decls` is 1 before erase.
Reviewed By: rjmccall, MaskRay
Differential Revision: https://reviews.llvm.org/D137263
Mehdi Amini [Sun, 6 Nov 2022 20:23:05 +0000 (20:23 +0000)]
Add missing dependent FuncDialect for `convert-async-to-llvm` pass
Fixes #58805
Mehdi Amini [Thu, 3 Nov 2022 20:07:33 +0000 (20:07 +0000)]
Apply clang-tidy fixes for readability-simplify-boolean-expr in GPUDialect.cpp (NFC)
Mehdi Amini [Thu, 3 Nov 2022 19:52:16 +0000 (19:52 +0000)]
Apply clang-tidy fixes for llvm-else-after-return in VectorToGPU.cpp (NFC)
Kazu Hirata [Sun, 6 Nov 2022 16:39:41 +0000 (08:39 -0800)]
[lld] Use llvm::reverse (NFC)
v1nh1shungry [Sun, 6 Nov 2022 17:30:41 +0000 (18:30 +0100)]
[clangd] Fix the code action `RemoveUsingNamespace`
Avoid adding qualifiers before C++ operators declared in a non-class context
Reviewed By: tom-anders
Differential Revision: https://reviews.llvm.org/D137494
Alexey Bader [Sun, 6 Nov 2022 16:16:36 +0000 (08:16 -0800)]
Online sync-ups: add SYCL working group sync details.
luxufan [Sun, 6 Nov 2022 02:44:50 +0000 (10:44 +0800)]
[IndVars] Forget the SCEV when the instruction has been sunk.
In the past, the SCEV expression of the sunk instruction was not
forgetted. This led to the incorrect block dispositions after the
instruction be sunk.
Fixes https://github.com/llvm/llvm-project/issues/58662
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D137060
Simon Pilgrim [Sun, 6 Nov 2022 14:32:00 +0000 (14:32 +0000)]
[X86] Schedule scalar movsx/movzx load+extend ops as WriteLoad instead of WriteALULd
Although some very old x86 hardware would perform the extension as a later stage, every target we have a scheduler for always performs this as part of the load-op (avoid ALU pipes etc.). If anyone wants to model very old hardware they can always override this.
This patch just tags these as WriteLoad directly and removes unnecessary overrides - this cleans up some latency/throughput tests as they aren't being badly modelled as folded ALU ops
Sanjay Patel [Sun, 6 Nov 2022 14:00:04 +0000 (09:00 -0500)]
[SimplifyLibCalls] improve code readability for AttributeList propagation; NFC
It is possible that we can do better on some of these transforms
by passing some subset of attributes, but we were not doing that
in any of the changed code. So it's better to give that a name
to indicate we're clearing attributes or make that more obvious
by using the default-constructed empty list.
Sanjay Patel [Sun, 6 Nov 2022 13:26:39 +0000 (08:26 -0500)]
[InstCombine] reduce multi-use casts+masks
As noted in the code comment, we could generalize this:
https://alive2.llvm.org/ce/z/N5m-eZ
It saves an instruction even without a constant operand,
but the 'and' is wider. We can do that as another step
if it doesn't harm anything.
I noticed that this missing pattern with a constant operand
inhibited other transforms in a recent bug report, so this
is enough to solve that case.
Sanjay Patel [Fri, 4 Nov 2022 15:17:44 +0000 (11:17 -0400)]
[InstCombine] add tests for zext of and of trunc; NFC
The basic one-use version of this sequence is reduced,
but we don't transform these currently.
Simon Pilgrim [Sun, 6 Nov 2022 14:03:59 +0000 (14:03 +0000)]
[X86] Fix scalar load latencies for WriteLoad scheduler class
Znver1/Znver2 were using vector load latency values (which is what WriteFLoad*/WriteVecLoad* are for) instead of the scalar load latency value
TBH I'm not sure clflush/clzero/prefetch ops should be tagged as WriteLoad but at least this makes us more consistent
Simon Pilgrim [Sun, 6 Nov 2022 13:35:46 +0000 (13:35 +0000)]
[X86] Regenerate atom-pad-short-functions.ll test checks
Simon Pilgrim [Sun, 6 Nov 2022 13:16:23 +0000 (13:16 +0000)]
Revert rG244331ae833aaf33503bbd36890e704afb66a237 "[X86] Fix scalar load latencies for WriteLoad scheduler class"
Forgot to update tests outside the llvm-mca test folder :-(
Simon Pilgrim [Sun, 6 Nov 2022 12:22:05 +0000 (12:22 +0000)]
[X86] Fix scalar load latencies for WriteLoad scheduler class
Atom was missing a load latency value (so was defaulting to 1cy)
Znver1/Znver2 were using vector load latency values (which is what WriteFLoad*/WriteVecLoad* are for) instead of the scalar load latency value
TBH I'm not sure clflush/clzero/prefetch ops should be tagged as WriteLoad but at least this makes us more consistent
David Green [Sun, 6 Nov 2022 12:06:12 +0000 (12:06 +0000)]
[SLP][AArch64] Add a test case for SLP phi ordering of scalable vectors. NFC
David Green [Sun, 6 Nov 2022 11:40:08 +0000 (11:40 +0000)]
Revert "[SLP] Extend reordering data of tree entry to support PHI nodes"
This reverts commit
87a20868eb2043420d48f591c3437472f7137834 as it has
problems with scalable vectors and use-list orders. Test to follow.
Valentin Clement [Sun, 6 Nov 2022 08:56:19 +0000 (09:56 +0100)]
[flang] Fix controlSuccessor chain for select rank construct
Represent the select rank statement + select rank case statement
the same way the select case statement and case statement are represented.
controlSuccessor was not correctly attributed to the next type guard stmt.
Similar to D137460 for select type construct.
Reviewed By: vdonaldson
Differential Revision: https://reviews.llvm.org/D137490
Kazu Hirata [Sun, 6 Nov 2022 08:10:02 +0000 (00:10 -0800)]
[llvm] Remove redundaunt typename (NFC)
Michał Górny [Sun, 6 Nov 2022 08:06:16 +0000 (09:06 +0100)]
Revert "[llvm] [cmake] Set EXCLUDE_FROM_ALL on gtest and TestingSupport"
This reverts commit
b6be37b0be5e1b524456c375700c76b7dae5171c. Still
breaks flang.
Michał Górny [Sun, 30 Oct 2022 06:37:15 +0000 (07:37 +0100)]
[llvm] [cmake] Set EXCLUDE_FROM_ALL on gtest and TestingSupport
Exclude building googletest and LLVMTestingSupport libraries from
the `all` target. If unittests are being built, these libraries will
be built as a dependency anyway. If they are not being built, building
them makes little sense as they are not installed or used otherwise.
This will also make standalone builds of other projects easier, as it
makes it possible to include these directories without having to cover
them with additional conditions to prevent them from being built
unconditionally.
Differential Revision: https://reviews.llvm.org/D137035
Kazu Hirata [Sun, 6 Nov 2022 07:52:42 +0000 (23:52 -0800)]
[mlir] Fix a warning
This patch fixes:
llvm-project/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp:1855:17:
error: comparison of integers of different signs: 'int64_t' (aka
'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare]
Arnab Dutta [Sun, 6 Nov 2022 06:59:10 +0000 (12:29 +0530)]
[MLIR] Fix bug in the method constructing semi affine expression from flattened form
Set proper offset to the second element of the index pair when either
lhs or rhs of a local expression is a dimensional identifier, so that
we do not have same index values for more than one local expression.
Reviewed By: springerm, hanchung
Differential Revision: https://reviews.llvm.org/D137389
Argyrios Kyrtzidis [Sun, 6 Nov 2022 03:58:41 +0000 (20:58 -0700)]
[llvm/cmake/config-ix.cmake] If `LD64_EXECUTABLE` is already set, avoid the need to look up `ld64`
This provides option to set the `LD64_EXECUTABLE` variable to a path at CMake configure time directly.
River Riddle [Sat, 5 Nov 2022 23:36:17 +0000 (16:36 -0700)]
[mlir][SubElements] Re-add null guards to better enable downstream adoption
We used to allow this, and it can break clients that still rely on it.
River Riddle [Sat, 5 Nov 2022 23:35:25 +0000 (16:35 -0700)]
[mlir][SubElementInterfaces] Prefer calling the derived get if possible
This allows for better supporting attributes/types that override the
default builders.
Jeff Niu [Fri, 4 Nov 2022 01:40:28 +0000 (18:40 -0700)]
[mlir] Drop `const` from `SymbolTableCollection::lookupSymbolIn`
This function didn't work because it was marked const but both functions
it could dispatch to are not.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D137380
Paul Robinson [Sat, 5 Nov 2022 21:36:40 +0000 (14:36 -0700)]
Change a 'default_triple' to 'object-emission'
as pointed out in post-commit review on D136612 by Igor Kudrin.
Sylvestre Ledru [Sat, 5 Nov 2022 21:35:54 +0000 (22:35 +0100)]
Add support of the next Ubuntu (Ubuntu 23.04 - Lunar Lobster)
LLVM GN Syncbot [Sat, 5 Nov 2022 20:26:22 +0000 (20:26 +0000)]
[gn build] Port
59ef4b3686e4
Nikolas Klauser [Thu, 22 Sep 2022 19:53:13 +0000 (21:53 +0200)]
[libc++] Split __allocator_destructor out of shared_ptr.h
Reviewed By: ldionne, huixie90, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D134479
Nikolas Klauser [Wed, 2 Nov 2022 19:27:42 +0000 (20:27 +0100)]
[libc++] Granularize <concept> includes
Reviewed By: ldionne, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D137283
Simon Pilgrim [Sat, 5 Nov 2022 19:06:55 +0000 (19:06 +0000)]
[X86] Replace unnecessary int2float and float2double overrides with better base class defs
Broadwell/Haswell were completely overriding the class defs - we can remove those overrides entirely by just choosing better class defs (plus a fix for missing mmx folded load).
Michał Górny [Mon, 31 Oct 2022 14:28:32 +0000 (15:28 +0100)]
[flang] Add one missing "llvm_" prefix to gtest_main
The `target_link_libraries()` call operates on `gtest_main` rather than
`llvm_gtest_main`. I think it was missed while prefixing all the tools
in
38151a08c21e0cdacd52af03e4bdff258f0bac6f.
Differential Revision: https://reviews.llvm.org/D137080
Simon Pilgrim [Sat, 5 Nov 2022 17:28:23 +0000 (17:28 +0000)]
[MCA][X86] Add more avx512 cvt instructions test coverage
Amaury Séchet [Sat, 5 Nov 2022 16:44:42 +0000 (16:44 +0000)]
[NFC] Refactor DAGCombiner::foldSelectOfConstants to reduce nesting 2.0
Florian Hahn [Sat, 5 Nov 2022 16:55:09 +0000 (16:55 +0000)]
[SimpleLoopUnswitch] Forget block & loop dispos during trivial unswitch.
Unswitching adjusts the CFG in ways that may invalidate cached loop
dispositions. Clear all cached block and loop dispositions during
trivial unswitching. The same is already done for non-trivial
unswitching.
Fixes #58751.
Amaury Séchet [Sat, 5 Nov 2022 16:11:13 +0000 (16:11 +0000)]
[NFC] Refactor DAGCombiner::foldSelectOfConstants to reduce nesting
Simon Pilgrim [Sat, 5 Nov 2022 15:45:45 +0000 (15:45 +0000)]
[X86] Cleanup WriteCvtSD2SS/WriteCvtPD2PS overrides
The WriteCvtSD2SS/WriteCvtPD2PS* classes were mostly unused as the models were needlessly overriding all instructions - in some cases the folded pattern overrides were entirely missing (but I've confirmed they just have an additional Port23 use)
There were a couple of typos (confirmed with Agner/uops.info) - Skylake/Icelake uses Port5+Port01 for XMM/YMM, Skylake uses Port5+Port05 for ZMM but Icelake uses Port5+Port0
Nikolas Klauser [Tue, 1 Nov 2022 19:06:11 +0000 (20:06 +0100)]
[libc++] Add [[nodiscard]] extensions to ranges algorithms
This mirrors what we have done in the classic algorithms
Reviewed By: ldionne, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D137186
Simon Pilgrim [Sat, 5 Nov 2022 14:35:41 +0000 (14:35 +0000)]
[X86] Fix cvtss2si64/cvttss2si64 typo in SkylakeClient
SS2SI64 conversions use Port0/Port01/Port5 (with/without truncation), but SS2SI32 only uses Port0/Port01 like SD2SI32/SD2SI64
Valentin Clement [Sat, 5 Nov 2022 14:10:40 +0000 (15:10 +0100)]
[flang] Fix controlSuccessor chain for select type construct
Represent the select type statement + type guard statement
the same way the select case statement and case statement are represented.
controlSuccessor was not correctly attributed to the next type guard stmt.
Reviewed By: PeteSteinfeld, vdonaldson
Differential Revision: https://reviews.llvm.org/D137460
Simon Pilgrim [Sat, 5 Nov 2022 13:57:07 +0000 (13:57 +0000)]
[X86] Fix override for CVTPD2PS/CVTPD2DQ/CVTTPD2DQ AVX variants
These were lost when they were converted from instregex to instrs
Simon Pilgrim [Sat, 5 Nov 2022 12:41:45 +0000 (12:41 +0000)]
[X86] Add SchedWriteVecTruncate scheduler per-width wrapper
Replaces hard coded uses of WriteVPMOV256 for all the vector truncations instructions
We still need to work out how to fix folded stores (see Issue #36236)
Simon Pilgrim [Sat, 5 Nov 2022 11:31:53 +0000 (11:31 +0000)]
[X86] Add missing ReadAfterFold attributes from CVTSD2SSrm/CVTSS2SDrm to match the AVX + _Int equivalents
This was never added in D52886, probably because the defs were already missing the old ReadAfterLd attribute, but they do exhibit the same behaviour of reading the dst reg after the load.
Simon Pilgrim [Sat, 5 Nov 2022 11:19:36 +0000 (11:19 +0000)]
[X86] Remove SandyBridge CVTSS2SIrm/CVTSD2SIrm overrides
Just use the default WriteCvtSS2I/WriteCvtSD2I folded variants (already used by the VCVTSS2SI/VCVTSD2SI AVX variants).
Confirmed with agner and uops.info - there should be no difference between the SSE/AVX1 variants in folded load latency
Simon Pilgrim [Sat, 5 Nov 2022 11:27:46 +0000 (11:27 +0000)]
[X86] Replace unnecessary int2double overrides with a better WriteCvtI2PD def
Broadwell, Haswell and SkylakeClient were completely overriding the WriteCvtI2PD defs - we can remove those overrides entirely by replacing the unused WriteCvtI2PD values
There's plenty more of these in the scheduler models - I'm looking at improving warnings in llvm-tblgen to catch them all
Ivan Butygin [Fri, 4 Nov 2022 22:26:02 +0000 (23:26 +0100)]
[mlir] Add `populateFunctionOpInterfaceTypeConversionPattern` version which operates on any `FunctionOpInterface`
Exisitng version is always limited to some specific op.
Differential Revision: https://reviews.llvm.org/D137469
Siva Chandra Reddy [Sat, 5 Nov 2022 07:58:16 +0000 (00:58 -0700)]
[libc][docs] Add a build and test document.
Siva Chandra Reddy [Sat, 5 Nov 2022 07:21:09 +0000 (00:21 -0700)]
[libc][docs] Fix typos.
Siva Chandra Reddy [Fri, 4 Nov 2022 19:53:24 +0000 (12:53 -0700)]
[libc][docs] Move links to internal developer guides out of the main side bar.
The links are all now from a "Developer Guides" page which is linked from the
main side bar.
Uday Bondhugula [Sat, 5 Nov 2022 05:38:21 +0000 (11:08 +0530)]
MLIR. NFC. Remove trailing whitespaces in MemRefOps.td
Remove trailing whitespaces in MemRefOps.td. NFC.
Med Ismail Bennani [Sat, 5 Nov 2022 04:58:51 +0000 (21:58 -0700)]
[lldb/crashlog] Standardize file path key in the ScriptedProcess Dictionary
This patch replaces the backing file path key to "file_path" to keep it
consistent.
rdar://
101652618
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Med Ismail Bennani [Sat, 5 Nov 2022 04:57:31 +0000 (21:57 -0700)]
[lldb/test] Fix StructuredDataTest::GetDescriptionEmpty warning (NFC)
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Med Ismail Bennani [Fri, 4 Nov 2022 21:49:52 +0000 (14:49 -0700)]
[lldb/crashlog] Fix frame parser regex for when there is no source info
It can happen that the originator of a crash report doesn't have access
to certain images. When that's the case, ReportCrash won't show the
source info in the crash report stack frames, but only the stack address
and image name.
This patch fixes a bug in the crashlog stackframe parser regular
expression to optionally match the source info group.
rdar://
101934135
Differential Revision: https://reviews.llvm.org/D137466
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
chenglin.bi [Sat, 5 Nov 2022 04:58:14 +0000 (12:58 +0800)]
[InstCombine] fold `sub + and` pattern with specific const value
`C1 - ((C3 - X) & C2) --> (X & C2) + (C1 - (C2 & C3))`
when:
(C3 - ((C2 & C3) - 1)) is pow2 &&
((C2 + C3) & ((C2 & C3) - 1)) == ((C2 & C3) - 1) &&
C2 is negative pow2 || (C3 - X) is nuw
https://alive2.llvm.org/ce/z/HXQJV-
Fix: #58523
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D136582
Tue Ly [Fri, 4 Nov 2022 18:22:35 +0000 (14:22 -0400)]
[libc] Add add_with_carry to builtin wrapper.
Add add_with_carry to builtin wrapper to be used by UInt class.
Reviewed By: orex
Differential Revision: https://reviews.llvm.org/D137453
River Riddle [Sat, 5 Nov 2022 01:53:50 +0000 (18:53 -0700)]
[mlir] Attempt to fix windows build after D137374
River Riddle [Fri, 4 Nov 2022 02:12:53 +0000 (19:12 -0700)]
[mlir:LLVM] Fix translation of DISubRangeAttr to LLVM
We were missing DISubRangeAttr in the type switch. This
also updates a few of the range parameters to be optional.
River Riddle [Thu, 3 Nov 2022 23:06:59 +0000 (16:06 -0700)]
[mlir] Infer SubElementInterface implementations using the storage KeyTy
The KeyTy of attribute/type storage classes provide enough information for
automatically implementing the necessary sub element interface methods. This
removes the need for derived classes to do it themselves, which is both much
nicer and easier to handle certain invariants (e.g. null handling). In cases where
explicitly handling for parameter types is necessary, they can provide an implementation
of `AttrTypeSubElementHandler` to opt-in to support.
This tickles a few things alias wise, which annoyingly messes with tests that hard
code specific affine map numbers.
Differential Revision: https://reviews.llvm.org/D137374
Quentin Colombet [Thu, 3 Nov 2022 19:14:52 +0000 (19:14 +0000)]
[mlir][MemRef] Fix the lowering of extract_strided_metadata
The first result of the extract_strided_metadata operation is a MemRef,
not a naked pointer.
This patch fixes the lowering of this operation in MemRefToLLVM so that
we properly materialize the full MemRef structure and not just the base,
naked, pointer.
Differential Revision: https://reviews.llvm.org/D137364
Craig Topper [Sat, 5 Nov 2022 00:49:08 +0000 (17:49 -0700)]
[RISCV] Add isel pattern for (and X, 0xffffffff << C) with Zba.
We can use SRLI by C to clear LSBs followed by a SLLI_UW.
Craig Topper [Sat, 5 Nov 2022 00:26:16 +0000 (17:26 -0700)]
[RISCV] Remove duplicate SDNodeXForm. NFC
Jennifer Yu [Sat, 5 Nov 2022 00:15:14 +0000 (17:15 -0700)]
Back out test that failed.
But I can not reproduce the problem on my local machine. My local machine run:
222 0x5a6780
222 0x7fffbef9400e
222 0x5a677e 0x5a6780 0x7fffbef936c8
222 0x376f8e 0x376f90 0x7fffbef94008
222 0x281f20
222 0x7fffbef9400e
PASSED
Matthew Voss [Sat, 5 Nov 2022 00:08:54 +0000 (17:08 -0700)]
[llvm-profdata] Check for all duplicate entries in MemOpSize table
Previously, we only checked for duplicate zero entries when merging a
MemOPSize table (see D92074), but a user recently provided a reproducer
demonstrating that other entries can also be duplicated. As demonstrated
by the test in this patch, PGOMemOPSizeOpt can potentially generate
invalid IR for non-zero, non-consecutive duplicate entries. This seems
to be a rare case, since the duplicate entry is often below the
threshold, but possible. This patch extends the existing warning to
check for any duplicate values in the table, both in the optimization
and in llvm-profdata.
Differential Revision: https://reviews.llvm.org/D136211
Craig Topper [Fri, 4 Nov 2022 19:59:55 +0000 (12:59 -0700)]
[RISCV] Rename isAllUsesReadW to hasAllWUsers in RISCVSExtWRemoval. NFC
Peiming Liu [Fri, 4 Nov 2022 19:35:29 +0000 (19:35 +0000)]
[mlir][sparse] fix sparse tensor rewriting patterns that do not propagate sparse tensor SSA properly.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137468
David Blaikie [Fri, 4 Nov 2022 23:35:05 +0000 (23:35 +0000)]
Peiming Liu [Fri, 4 Nov 2022 17:52:21 +0000 (17:52 +0000)]
[mlir][sparse] extend foreach operation to accept reduction arguments.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137463