Gert Wollny [Tue, 23 Aug 2022 13:46:36 +0000 (15:46 +0200)]
r600/sfn: Use a heuristic to keep SSBO setup and store close
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
v2: do handling in shader block to be thread save (hinted to by Filip)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:35:06 +0000 (15:35 +0200)]
r600/sfn: Don't scan the whole block for ready instructions
Limit the number of tested instructions and the number of
ready instructions that might be taken into account.
This reduces the time needed to run the scheduler significantly.
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:30:23 +0000 (15:30 +0200)]
r600/sfn: Don't schedule GDS instructions early
Atomic GDS instructions like inc, dec, or read will increase the
register pressure, therefore we shouldn't prioritize scheduling them.
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 13:03:48 +0000 (15:03 +0200)]
r600/sfn: Don't tag mem-ring and stream instructions as exports
Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.
When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.
This fixes
spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Gert Wollny [Tue, 23 Aug 2022 07:27:10 +0000 (09:27 +0200)]
r600/sfn: Handle color0 writes all on R700 like on EG
Fixes:
069f3869ac3a140898224c8c37d5b3b6349361a4
r600/sfn: Fix color outputs when color0 writes all
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
Lucas Stach [Thu, 25 Aug 2022 12:16:37 +0000 (14:16 +0200)]
etnaviv: add debug option to disable linear PE feature
Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to disable
the feature, so users can more easily check if some issue is caused by this
feature.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
Lucas Stach [Wed, 24 Aug 2022 14:26:52 +0000 (16:26 +0200)]
etnaviv: use linear PE rendering only on properly aligned surfaces
When linear rendering is used together with TS, the color tiles must be fully
contained in a single row of pixels. When wrapping around to the next row
TS gets confused and records wrong tile status information, leading to visual
corruption when the surface is resolved/decompressed.
The corruption can be fixed by increasing the stride alignment for linear
render targets, but that would break some existing use-cases, as some display
engines used together with Vivante GPUs currently don't support strides that
don't match the horizontal display resolution.
For now only enable linear PE rendering when the surface is properly aligned
already. This allows to use the optimization in a lot of common use-cases, but
falls back to the proven tiled rendering with subsequent resolve into linear
for the problematic cases.
CC: mesa-stable #22.2
Fixes:
53445284a42 ("etnaviv: add linear PE support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
Lucas Stach [Wed, 13 Jul 2022 17:58:23 +0000 (19:58 +0200)]
etnaviv: move checking for MC2.0 for TS into screen init
The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.
Instead of checking two separate feature bits to determine if TS can be used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
Samuel Pitoiset [Wed, 24 Aug 2022 15:41:42 +0000 (17:41 +0200)]
radv: stop emitting RMW context registers for updating sample locations
RMW context registers have been removed in RadeonSI a while ago
because they don't seem good for performance.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Samuel Pitoiset [Wed, 24 Aug 2022 15:14:53 +0000 (17:14 +0200)]
radv: cleanup dynamic states in radv_emit_graphics_pipeline()
Some dynamic states always need to be emitted when the first pipeline
is emitted, some others depend on pipeline state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Samuel Pitoiset [Wed, 24 Aug 2022 15:10:33 +0000 (17:10 +0200)]
radv: stop clearing bitfields for registers that are emitted dynamically
These fields aren't set at pipeline creation, so clearing them is
just useless.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Samuel Pitoiset [Wed, 24 Aug 2022 15:09:42 +0000 (17:09 +0200)]
radv: stop setting CB_COLOR_CONTROL.ROP3 from the pipeline
This is useless because logic op is a dynamic state and it's already
emitted from the cmdbuf.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
Qiang Yu [Wed, 15 Jun 2022 09:51:25 +0000 (17:51 +0800)]
ac/llvm: cast tes_u/v_replaced to float
Otherwise LLVM float ops fail to operate on them.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Fri, 8 Jul 2022 13:35:18 +0000 (21:35 +0800)]
ac/nir/ngg: support clipdist culling
Port from radeonsi.
Besides vertex position based primitive culling, clipdist
attribute can also be used to cull a primitive. Normally
it's used by fixed-pipeline, but when NGG we can treate it
as a culling condition to filter out invisible primitive
before fixed-pipeline.
There are two kinds of clipdist:
1. user define a clip plane explicitly by glClipPlane(),
fixed-pipeline calculate with vertex position to get
clipdist, then cull. This is the legacy way.
2. Now GLSL define gl_ClipDistance/gl_CullDiatance so that
user can calculate clipdist in any way he like.
This implementation support both way.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Mon, 13 Jun 2022 09:29:06 +0000 (17:29 +0800)]
ac/nir/ngg: support component position store
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Thu, 9 Jun 2022 01:11:10 +0000 (09:11 +0800)]
ac/nir/ngg: add gs culling
Port from radeonsi.
Cull primitive after GS thread and before final vertex/primitive
export. GS culling is like VS/TES culling which read out saved
vertex positions of a primitive from LDS then call the primitive
culling algorithm to check whether it's visiable or not, only
passed primitives will be exported.
Unlike the VS/TES culling that read vertex index of a primitive
from VGPRs as shader args, GS will set a primitive complete flag
for each last vertex of a primitive in LDS, so that vertex thread
know the previous 1/2/3 vertex can form a primitive and do primitive
culling.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Fri, 22 Jul 2022 12:34:34 +0000 (20:34 +0800)]
ac/nir/ngg: save and restore position output base for nogs
radeonsi has different driver_location and io location.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Sat, 23 Jul 2022 08:22:49 +0000 (16:22 +0800)]
ac/nir/ngg: save and restore output bit size for gs
radeonsi does not have io nir variables, so need to save output
bit size when lower store_output intrinsic.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Wed, 13 Jul 2022 00:55:20 +0000 (08:55 +0800)]
ac/nir/ngg: use same driver location for gs output
driver_location and io location are different for radeonsi,
and radeonsi llvm rely on the correct driver_location to
index output variables.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Tue, 12 Jul 2022 14:11:48 +0000 (22:11 +0800)]
ac/nir/ngg: fix and simplify gs store output lower
Simplify: 64bit IO has been lowered by nir_lower_io with
nir_lower_io_lower_64bit_to_32, so no need to handle in the
ngg lower.
Fix: we need to increase io_sem.location by base_offset for
correct gs_output_info.
radeonsi has different driver_location and io location, so
also change the output variable index to io location.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Mon, 6 Jun 2022 09:06:41 +0000 (17:06 +0800)]
ac/nir/ngg: support line culling
Port from ac_llvm_cull.c
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Tue, 9 Aug 2022 13:47:11 +0000 (21:47 +0800)]
ac/nir/cull: support caller react when primitive is rejected
Make accept_func optional, and return accpect result for caller
react when primitive is rejected.
This is for GS culling.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Wed, 3 Aug 2022 09:56:36 +0000 (17:56 +0800)]
ac/nir/ngg,radv: use nir_load_viewport_xy_scale_and_offset
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Wed, 3 Aug 2022 08:45:36 +0000 (16:45 +0800)]
nir,ac/llvm: add nir_intrinsic_load_viewport_xy_scale_and_offset
Used by RADV/Radeonsi NGG culling. Pack them into a single vec4
load for radeonsi to reduce const buffer load.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Qiang Yu [Mon, 6 Jun 2022 08:37:16 +0000 (16:37 +0800)]
nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd
Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
Dave Airlie [Thu, 11 Aug 2022 02:57:12 +0000 (12:57 +1000)]
gallivm: don't indirect image/sampler destroy.
These are pointless indirections, just call direct the destroy
functions.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
Dave Airlie [Mon, 8 Aug 2022 19:28:06 +0000 (05:28 +1000)]
gallivm/sample: remove unused base parameter from dynamic callbacks.
This parameters was never used anywhere, so just remove it.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
Dave Airlie [Mon, 8 Aug 2022 19:19:52 +0000 (05:19 +1000)]
gallivm: drop unused parameter to lp_build_sample_aos
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
Emma Anholt [Fri, 26 Aug 2022 02:40:38 +0000 (19:40 -0700)]
ci: disable the freedreno farm.
It seems to have gone down at the end of the day today. I'm off tomorrow,
someone else can debug.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18263>
Emma Anholt [Sun, 10 Jul 2022 03:28:42 +0000 (20:28 -0700)]
ci: Move 'never' rules includes above "on_success" rules includes.
The farm online-ness filters were listed after some of the checks for
whether code changed, so an offline farm might still be used in that case.
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18263>
Kenneth Graunke [Wed, 24 Aug 2022 22:11:32 +0000 (15:11 -0700)]
iris: Use linear for exported resources if we can't convey tiling
If we have modifiers, we can use those to convey the tiling of exported
resources. If we have the deprecated i915 GET/SET_TILING uAPI, we can
use that to convey the tiling.
If we have neither, then we have to fall back to linear.
Fixes:
e6588354360 ("iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6938
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18240>
Jesse Natalie [Thu, 11 Aug 2022 21:02:18 +0000 (14:02 -0700)]
dzn: Get max supported shader model
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:51:26 +0000 (13:51 -0700)]
d3d12: Get max supported shader model
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:40:49 +0000 (13:40 -0700)]
microsoft/compiler: Support SM6.7
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:02:27 +0000 (13:02 -0700)]
microsoft/compiler: SM6.6 is supported
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 20:00:39 +0000 (13:00 -0700)]
microsoft/compiler: Handle SM6.6 handles
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 19:48:12 +0000 (12:48 -0700)]
microsoft/compiler: Pass lower_bound, upper_bound, space to createhandle
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 19:37:56 +0000 (12:37 -0700)]
microsoft/compiler: Delete double-assignment of sampler metadata field
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 19:37:44 +0000 (12:37 -0700)]
microsoft/compiler: Add getters for res bind/props structs
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 17:23:22 +0000 (10:23 -0700)]
microsoft/compiler: Add dynamic create handle helper
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 16:46:42 +0000 (09:46 -0700)]
microsoft/compiler: Add struct and function defs for SM6.6 handle funcs
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 16:38:45 +0000 (09:38 -0700)]
microsoft/compiler: Support up to shader model 6.5
We don't actually use any of the new features, but that's okay, it's
still valid DXIL at the higher shader models.
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Jesse Natalie [Thu, 11 Aug 2022 16:35:58 +0000 (09:35 -0700)]
microsoft/compiler: Always emit a shader at the max-supported shader model
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
Chia-I Wu [Thu, 25 Aug 2022 16:11:53 +0000 (09:11 -0700)]
turnip: improve tracing of secondary cmd buffers
This visualizes secondary cmd buffers in perfetto. I did not test
dynamic rendering, which appears to call tu_clone_trace_range already.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 23:37:28 +0000 (16:37 -0700)]
turnip: add cmd_buffer tracepoint
It is only used for primary cmd buffers for the moment.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 18:04:39 +0000 (11:04 -0700)]
turnip: rename some tracing stages
Rename SURFACE_STAGE_ID to RENDER_PASS_STAGE_ID. Indicate whether gmem
or bypass is used in the stage name.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 20:09:35 +0000 (13:09 -0700)]
turnip: clean up tu_perfetto.h
Move enums, stages, queues, and some function declarations to
tu_perfetto.cc.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 19:30:29 +0000 (12:30 -0700)]
turnip: convert tu_perfetto_state to a stack
A stage does not end until its nested stages end. tu_perfetto_state can
be a stack.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 22:54:42 +0000 (15:54 -0700)]
turnip: add tu_clone_trace_range helper
Remove some duplicated code.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 17:06:31 +0000 (10:06 -0700)]
util/u_trace: add PERFETTO HeaderScope
Headers with the PERFETTO scope will be included by the generated
perfetto utils header. This is needed because to_prim_type may have
header dependencies.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 17:23:17 +0000 (10:23 -0700)]
util/u_trace: include the generated header first
This is a good practice to make sure the generated header is
self-contained (no missing includes, declarations, etc.).
Remove unnecessary SOURCE header scope from the default.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 17:23:20 +0000 (10:23 -0700)]
turnip: tidy up tracepoint header includes
Remove unused util/u_dump.h. Add missing forward declarations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Wed, 24 Aug 2022 01:18:02 +0000 (18:18 -0700)]
turnip: fix gem_store tracepoint
Set cmd->trace_renderpass_end after tu6_emit_tile_store in case of gmem.
To be able to do that, we push the update of cmd->trace_renderpass_end
down into tu_cmd_render_tiles/tu_cmd_render_sysmem.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Thu, 25 Aug 2022 15:47:50 +0000 (08:47 -0700)]
turnip: move trace_start_gmem_store before cond exec
Suggested by Danylo.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 21:03:04 +0000 (14:03 -0700)]
turnip: fix a missing trace_end_gmem_clear
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Chia-I Wu [Tue, 23 Aug 2022 01:15:24 +0000 (18:15 -0700)]
turnip: improve perfetto sync_timestamp
tu_device_get_gpu_timestamp takes >100us on my otherwise idle sc7180.
Read the cpu block again after the call returns.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18238>
Yiwei Zhang [Fri, 19 Aug 2022 19:45:05 +0000 (19:45 +0000)]
venus: avoid scrubing wsi/external sempahores
When the renderer supports sync_fd import for the binary semaphore,
venus can import the special signaled payload to the semaphore instead
of scrubing it. This avoids the bugs w.r.t timeline semaphore and device
group submission in the legacy scrub path.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 18 Aug 2022 21:57:47 +0000 (21:57 +0000)]
venus: re-implement sync_fd external sempahore
sync_wait is deferred to a submission that waits on the semaphore.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 18 Aug 2022 16:55:06 +0000 (16:55 +0000)]
venus: re-implement sync_fd external fence
Instead of waiting for signal before importing, we are able to retain
the imported sync file and handle the fence related commands on the
driver side.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Sat, 13 Aug 2022 06:55:38 +0000 (06:55 +0000)]
venus: query renderer sync_fd props to fill the feature stubs
This change enables the fixed code paths.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 22:20:09 +0000 (22:20 +0000)]
venus: fix vn_GetSemaphoreFdKHR
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 17:09:43 +0000 (17:09 +0000)]
venus: fix vn_GetFenceFdKHR
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 18:31:13 +0000 (18:31 +0000)]
venus: put android wsi on the sub-optimal path
Simplify Android wsi to only use performant path if fixed sync_fd fence
support is enabled. This removes hacky codes and allows us to deprecate
a special ring wait code path as well.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 05:55:34 +0000 (05:55 +0000)]
venus: stub out renderer sync_fd fencing features
With syncFdFencing feature, venus starts forwarding renderer sync_fd
fencing support. The driver side now can track the renderer sync_fd
fencing features. This change adds the initial stubs.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Fri, 12 Aug 2022 05:45:44 +0000 (05:45 +0000)]
venus: sync to latest venus protocol headers for syncFdFencing
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 11 Aug 2022 22:38:20 +0000 (22:38 +0000)]
venus: avoid pre-allocating the feedback pool
Now that we don't create fence upon device creation, let's also defer
the feedback pool grow to the first event or non-external fence
creation. This makes venus device creation lighter and is good for CI.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 11 Aug 2022 22:33:26 +0000 (22:33 +0000)]
venus: lazily create queue wait fence and make it non-external
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 11 Aug 2022 22:08:43 +0000 (22:08 +0000)]
venus: use a separate sync fence for Android wsi
Also refactors the codes a bit.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Sat, 6 Aug 2022 05:18:49 +0000 (05:18 +0000)]
venus: avoid feedback for external fence
Sync fd fence export implies a payload reset operation, and application
can immediately do another submission with the same fence after export.
Concurrent use of the same feedback slot is incorrect. Keeping a list of
feedback slots for sync_fd external fence is a bit over designed given
those fences are usually not checked or waited by the app, but will hand
off the ownership via sync fd to an external client.
Fixes:
d7f2e6c8d03 ("venus: add fence feedback")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Thu, 4 Aug 2022 21:15:48 +0000 (21:15 +0000)]
venus: require necessary extensions for common wsi support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Yiwei Zhang [Mon, 8 Aug 2022 18:19:03 +0000 (18:19 +0000)]
venus: fix external memory ext filtering
Fixes:
390722620e1 ("venus: clean up vn_device_fix_create_info")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
Dawn Han [Mon, 11 Jul 2022 19:25:29 +0000 (19:25 +0000)]
Update venus-protocol to add extension `VK_VALVE_mutable_descriptor_type`
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
José Roberto de Souza [Tue, 23 Aug 2022 17:49:59 +0000 (10:49 -0700)]
anv: Return earlier in anv_gem_get_tiling() when not supported
Tiling set and get UAPIs has the same support level.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18251>
José Roberto de Souza [Tue, 23 Aug 2022 17:36:23 +0000 (10:36 -0700)]
anv: Nuke dead code
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18251>
Jesse Natalie [Tue, 23 Aug 2022 19:14:56 +0000 (12:14 -0700)]
mesa: Expose GL_NV_ES1_1_compatibility
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18217>
Jesse Natalie [Wed, 24 Aug 2022 21:57:25 +0000 (14:57 -0700)]
meson: Add an option to specify the WGL gallium megadriver filename
Specifying the name at build time, as opposed to renaming after
the build, serves two purposes:
1. The link from Mesa's OpenGL32.dll and (and EGL/GLES) to the
megadriver is done by filename. If using these frontends, the
megadriver can't be renamed afterwards. And Windows doesn't
have very good symlink support, so that's not really an option
either.
2. The symbol (PDB) filename is also embedded in the DLL using the
build-time expected filename. Renaming can produce odd artifacts
while debugging.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7115
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18239>
Jesse Natalie [Wed, 24 Aug 2022 21:49:29 +0000 (14:49 -0700)]
gallium/windows: Delete OpenGLOn12.dll target
This is pretty much identical to libgallium_wgl.dll except for the
DLL name.
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18239>
Rhys Perry [Thu, 18 Aug 2022 13:31:06 +0000 (14:31 +0100)]
aco: fix long-jump version of discard early exit
It isn't safe to modify the exec mask before the discard block, and the
definition interferes with GFX11 NOP insertion.
Just use s[0:1] instead, since we won't be using it.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18125>
Karmjit Mahil [Wed, 10 Aug 2022 08:38:32 +0000 (09:38 +0100)]
pvr: Fix calculation in rogue_max_compute_shared_registers().
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18224>
Karmjit Mahil [Wed, 10 Aug 2022 08:36:44 +0000 (09:36 +0100)]
pvr: Compete pvr_calc_fscommon_size_and_tiles_in_flight().
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18224>
Qiang Yu [Tue, 23 Aug 2022 08:14:56 +0000 (16:14 +0800)]
winsys/amdgpu: fix non-page-aligned sparse buffer creation
ARB_sparse_buffer does not require sparse buffer size to be
page aligned. So we need to align it before VM ops as KMD
will check whether it's aligned and return EINVAL if not.
Fixes:
667da4eaed3 ("winsys/amdgpu: sparse buffer creation / destruction / commitment")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7104
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18206>
Eric Engestrom [Mon, 15 Aug 2022 21:37:30 +0000 (22:37 +0100)]
v3d: introduce V3D_DBG() macro to make V3D_DEBUG checks consistent
The main issue was the inconsistent use of `unlikely()`, but the macro
also simplifies the code a little bit.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18086>
Eric Engestrom [Mon, 15 Aug 2022 21:38:26 +0000 (22:38 +0100)]
vc4: introduce VC4_DBG() macro to make VC4_DEBUG checks consistent
The main issue was the inconsistent use of `unlikely()`, but the macro
also simplifies the code a little bit.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18086>
Chad Versace [Tue, 2 Aug 2022 00:46:06 +0000 (17:46 -0700)]
venus: Enable VK_EXT_pipeline_creation_cache_control
The extension disrupts assumptions in venus. It gives
vkCreateFooPipelines an additional success code,
VK_PIPELINE_COMPILE_REQUIRED, which allows some pipelines to succeed
creation and others fail.
Tested with 'dEQP-VK.*cache_control*' at vulkan-cts-1.3.3.1.
pass/fail/skip/warn = 15/0/0/3
Warnings were from long pipeline compiles on a full debug build in host
and guest.
See: https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/890
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17847>
Chad Versace [Fri, 12 Aug 2022 22:57:05 +0000 (15:57 -0700)]
venus: Fix failure path on pipeline creation
It's not sufficient to vk_free() the pipeline. We must also
vn_object_base_fini().
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17847>
Chad Versace [Fri, 12 Aug 2022 21:56:31 +0000 (14:56 -0700)]
venus: Dedupe pipeline handle creation
Refactor the code into new function vn_create_pipeline_handles().
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17847>
Eric Engestrom [Mon, 22 Aug 2022 20:03:15 +0000 (21:03 +0100)]
meson: replace manual compiler flags with meson arguments
These would only have worked in GCC and Clang, which so far wasn't an
issue, but let's clean it up anyway.
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18190>
Dave Airlie [Wed, 24 Aug 2022 20:03:45 +0000 (06:03 +1000)]
vulkan: update rest of the headers to v1.3.225
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18237>
Alyssa Rosenzweig [Tue, 2 Aug 2022 15:36:41 +0000 (11:36 -0400)]
pan/mdg: Use correct idiv lowering
Rip off the bandaid. We can't tolerate straight-up wrong results. We have an
efficient umul_high implementation so it's not so bad.
total instructions in shared programs: 1537404 -> 1537204 (-0.01%)
instructions in affected programs: 143299 -> 143099 (-0.14%)
helped: 89
HURT: 283
helped stats (abs) min: 1.0 max: 41.0 x̄: 5.87 x̃: 6
helped stats (rel) min: 0.39% max: 6.67% x̄: 1.41% x̃: 1.44%
HURT stats (abs) min: 1.0 max: 7.0 x̄: 1.14 x̃: 1
HURT stats (rel) min: 0.24% max: 5.71% x̄: 0.35% x̃: 0.27%
95% mean confidence interval for instructions value: -0.96 -0.12
95% mean confidence interval for instructions %-change: -0.17% 0.03%
Inconclusive result (%-change mean confidence interval includes 0).
total bundles in shared programs: 647521 -> 648154 (0.10%)
bundles in affected programs: 45833 -> 46466 (1.38%)
helped: 92
HURT: 228
helped stats (abs) min: 1.0 max: 13.0 x̄: 3.10 x̃: 3
helped stats (rel) min: 0.69% max: 7.14% x̄: 2.11% x̃: 1.99%
HURT stats (abs) min: 1.0 max: 7.0 x̄: 4.03 x̃: 5
HURT stats (rel) min: 0.59% max: 7.22% x̄: 2.93% x̃: 3.40%
95% mean confidence interval for bundles value: 1.58 2.38
95% mean confidence interval for bundles %-change: 1.21% 1.76%
Bundles are HURT.
total quadwords in shared programs: 1135141 -> 1138268 (0.28%)
quadwords in affected programs: 101064 -> 104191 (3.09%)
helped: 30
HURT: 342
helped stats (abs) min: 1.0 max: 30.0 x̄: 4.97 x̃: 3
helped stats (rel) min: 0.24% max: 5.99% x̄: 1.72% x̃: 1.06%
HURT stats (abs) min: 1.0 max: 16.0 x̄: 9.58 x̃: 10
HURT stats (rel) min: 0.73% max: 17.14% x̄: 3.64% x̃: 3.80%
95% mean confidence interval for quadwords value: 7.84 8.97
95% mean confidence interval for quadwords %-change: 2.99% 3.43%
Quadwords are HURT.
total registers in shared programs: 91938 -> 92265 (0.36%)
registers in affected programs: 2639 -> 2966 (12.39%)
helped: 0
HURT: 280
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.17 x̃: 1
HURT stats (rel) min: 9.09% max: 50.00% x̄: 12.75% x̃: 11.11%
95% mean confidence interval for registers value: 1.12 1.22
95% mean confidence interval for registers %-change: 12.05% 13.45%
Registers are HURT.
total threads in shared programs: 55280 -> 55268 (-0.02%)
threads in affected programs: 24 -> 12 (-50.00%)
helped: 0
HURT: 11
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.09 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.29 -0.89
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17860>
Alyssa Rosenzweig [Wed, 24 Aug 2022 16:21:37 +0000 (12:21 -0400)]
pan/mdg: Reexpress umul_high packing
There are a bunch of subtle details of how 32-bit sources are
zero-extended to 64-bit, how their swizzles work, how 64-bit
destinations are shrunk to 32-bit, and how those two interact. This
fixes the interactions... mostly.
Fixes umul_high, all such tests should be passing now. Unblocks idiv
lowering that depends on umul_high.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17860>
Alyssa Rosenzweig [Wed, 24 Aug 2022 16:20:04 +0000 (12:20 -0400)]
pan/mdg: Replicate swizzles for scalar sources
This works around issue packing 32-bit scalar swizzles zero-extended to
64-bit, seen with the umul_high implementation. I tried for a while
figuring out the root cause (even rewrote a big chunk of disassembler)
but am still a bit lost. Nevertheless this is a safe workaround with no
performance impact (and avoids relying on NIR undefined behaviour to
implement GPU undefined behaviour), so let's do this for now to fix
umul_high.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17860>
Marek Olšák [Wed, 24 Aug 2022 14:59:31 +0000 (10:59 -0400)]
ci: update pass/fail results for spec@!opengl 1.0@gl-1.0-dlist-bitmap
This is mostly positive.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
Marek Olšák [Mon, 25 Jul 2022 00:36:00 +0000 (20:36 -0400)]
st/mesa: fix potential use-after-free in draw_bitmap_quad
This is super unlikely to be freed before use, but let's fix it anyway.
setup_render_state calls set_sampler_views(take_ownership=true), which
means it takes ownership of the sampler view reference and is free to
unreference it, so we can't use sv after setup_render_state.
Fixes:
feda6e9c5d101 - st/mesa: set take_ownership = true in set_sampler_views
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
Marek Olšák [Mon, 25 Jul 2022 00:47:26 +0000 (20:47 -0400)]
mesa: create glBitmap textures while creating display lists
This makes glCallList just a textured draw, which is blazingly fast.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
Marek Olšák [Sun, 24 Jul 2022 23:35:28 +0000 (19:35 -0400)]
Revert "mesa: implement a display list / glBitmap texture atlas"
This reverts commit
b26ddda12fe7dbb6a4e6af3b47c1e837cc7ebb03 and
commit
06d3b0a006f35dc232d512d09f45a6cb4f13cfdf.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
Lionel Landwerlin [Mon, 1 Aug 2022 15:12:45 +0000 (18:12 +0300)]
intel/fs: bump max SIMD size for A64 atomics with LSC
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>.
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
Lionel Landwerlin [Sun, 24 Jul 2022 13:17:17 +0000 (16:17 +0300)]
intel/fs: port block a64/surface messages to use LSC
v2: Fixup block load/store on surfaces/shared-memory (Rohan)
v3: drop write specific size_written case (Rohan)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
Lionel Landwerlin [Mon, 18 Jul 2022 09:27:53 +0000 (12:27 +0300)]
intel/fs: switch register allocation spilling to use LSC on Gfx12.5+
v2: drop the hardcoded inst->mlen=1 (Rohan)
v3: Move back to LOAD/STORE messages (limited to SIMD16 for LSC)
v4: Also use 4 GRFs transpose loads for fills (Curro)
v5: Reduce amount of needed register to build per lane offsets (Curro)
Drop some now useless SIMD32 code
Unify unspill code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
Lionel Landwerlin [Sun, 24 Jul 2022 10:05:57 +0000 (13:05 +0300)]
intel/fs: fixup SEND validation check on overlapping src0/src1
With the following SEND instruction :
send(1) nullUD nullUD g0UD 0x4200c504 a0.1<0>UD
This instruction although valid but somewhat nonsensical (SEND message
to write at offset contained in NULL register), triggers an error in
the validator.
The restriction is that we cannot have overlapping sources. The
validator not checking the type of register incorrectly thinks that
the null register (offset 0) is the same as g0.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
Lionel Landwerlin [Sat, 23 Jul 2022 19:57:12 +0000 (22:57 +0300)]
intel/fs: remove unused opcode
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
projects / platform / upstream / mesa.git / log