Zakk Chen [Tue, 6 Apr 2021 14:57:41 +0000 (07:57 -0700)]
[RISCV][Clang] Add all RVV Reduction intrinsic functions.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D99964
Zakk Chen [Tue, 6 Apr 2021 14:23:30 +0000 (07:23 -0700)]
[RISCV][Clang] Add RVV merge intrinsic functions.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D99963
Zakk Chen [Thu, 1 Apr 2021 16:21:11 +0000 (09:21 -0700)]
[RISCV][Clang] Add RVV Type-Convert intrinsic functions.
Fix extension macro condition.
Support below instructions:
1. Single-Width Floating-Point/Integer Type-Convert Instructions
2. Widening Floating-Point/Integer Type-Convert Instructions
3. Narrowing Floating-Point/Integer Type-Convert Instructions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D99742
Zakk Chen [Thu, 8 Apr 2021 15:21:06 +0000 (08:21 -0700)]
[RISCV][Clang] Add some RVV Floating-Point intrinsic functions.
Support vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt instructions.
Reviewed By: craig.topper
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Differential Revision: https://reviews.llvm.org/D99741
Zakk Chen [Thu, 8 Apr 2021 15:09:42 +0000 (08:09 -0700)]
[RISCV][Clang] Add more RVV Floating-Point intrinsic functions.
Support below instructions.
1. Vector Widening Floating-Point Add/Subtract Instructions
2. Vector Widening Floating-Point Multiply
3. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
4. Vector Widening Floating-Point Fused Multiply-Add Instructions
5. Vector Floating-Point Compare Instructions
Reviewed By: craig.topper, HsiangKai
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Differential Revision: https://reviews.llvm.org/D99669
Zakk Chen [Thu, 8 Apr 2021 14:29:59 +0000 (07:29 -0700)]
[RISCV][Clang] Add some RVV Floating-Point intrinsic functions.
Support the following instructions which have the same class.
1. Vector Single-Width Floating-Point Subtract Instructions
2. Vector Single-Width Floating-Point Multiply/Divide Instructions
3. Vector Floating-Point MIN/MAX Instructions
4. Vector Floating-Point Sign-Injection Instructions
Reviewed By: craig.topper
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Differential Revision: https://reviews.llvm.org/D99668
Zakk Chen [Tue, 6 Apr 2021 10:26:44 +0000 (03:26 -0700)]
[RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.
Reviewed By: craig.topper
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Differential Revision: https://reviews.llvm.org/D99526
Jim Lin [Mon, 12 Apr 2021 02:15:35 +0000 (10:15 +0800)]
[RISCV][NFC] Remove unneeded explict XLenVT type on codegen patterns
Customized SDNode has been specified the explict XLenVT type.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D100190
Craig Topper [Mon, 12 Apr 2021 00:54:20 +0000 (17:54 -0700)]
[RISCV] Update computeKnownBitsForTargetNode to treat READ_VLENB as being 16 byte aligned.
According to the 0.10 spec, VLEN is at least 128 bits and is a
power of 2.
Craig Topper [Sun, 11 Apr 2021 18:57:52 +0000 (11:57 -0700)]
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
We don't need the sign extending behavior here and SLLI/SRLI
are able to compress to C.SLLI/C.SRLI.
Roman Lebedev [Sun, 11 Apr 2021 20:44:24 +0000 (23:44 +0300)]
[NFCI][SimplifyCFG] PerformValueComparisonIntoPredecessorFolding(): improve Dominator Tree updating
Same as with previous patches.
Roman Lebedev [Sun, 11 Apr 2021 20:25:40 +0000 (23:25 +0300)]
[NFCI][SimplifyCFG] mergeEmptyReturnBlocks(): improve Dominator Tree updating
Same as with previous patches.
Roman Lebedev [Sun, 11 Apr 2021 20:17:48 +0000 (23:17 +0300)]
[NFCI][Local] MergeBasicBlockIntoOnlyPred(): improve Dominator Tree updating
Same as with TryToSimplifyUncondBranchFromEmptyBlock()/MergeBlockIntoPredecessor() patch.
Roman Lebedev [Sun, 11 Apr 2021 20:08:19 +0000 (23:08 +0300)]
[NFCI][BasicBlockUtils] MergeBlockIntoPredecessor(): improve Dominator Tree updating
Same as with TryToSimplifyUncondBranchFromEmptyBlock() patch.
Roman Lebedev [Sun, 11 Apr 2021 19:39:22 +0000 (22:39 +0300)]
[NFCI][Local] TryToSimplifyUncondBranchFromEmptyBlock(): improve Dominator Tree updating
First, we don't need vector-ness for the predecessor lists.
Secondly, like elsewhere, do insertions before deletions.
Lastly, the check that we actually need to insert an edge,
that it doesn't exist already, is backwards. Instead of
looking at successors of every single 'PredOfBB',
just always look at predecessors of the 'Succ'.
The result is always the same, but we avoid *really* inefficient code.
Roman Lebedev [Sun, 11 Apr 2021 19:02:57 +0000 (22:02 +0300)]
[NFCI][DomTreeUpdater] applyUpdates(): reserve space for updates first
While, indeed, we may end up pushing less updates that we'd reserve space
for, self-dominating updates aren't often enough for that to matter.
But this should matter for normal updates.
Florian Hahn [Sat, 10 Apr 2021 14:23:47 +0000 (15:23 +0100)]
[LoopUnroll] Add AArch64 test case with large vector ops.
Add test case to illustrate over-eager unrolling on AArch64, due to the
cost-model not estimating the size of vector loads/stores accurately.
Florian Hahn [Sun, 11 Apr 2021 15:51:37 +0000 (16:51 +0100)]
[VectorCombine] Add tests for load/extract scalarization.
Add tests where scalarizing a vector load + extract is profitable.
Simon Pilgrim [Sun, 11 Apr 2021 19:06:53 +0000 (20:06 +0100)]
[X86][AVX512] Fold not(kmov(x)) -> kmov(not(x)) and not(widen_subvector(x)) -> widen_subvector(not(x))
Improve AVX512 mask inversion, rG38c799bce801 exposed some missing opportunities to move scalar not() back onto the boolvector types for folding with setcc etc.
Thomas Lively [Sun, 11 Apr 2021 18:13:16 +0000 (11:13 -0700)]
[WebAssembly] Update v128.any_true
In the final SIMD spec, there is only a single v128.any_true instruction, rather
than one for each lane interpretation because the semantics do not depend on the
lane interpretation.
Differential Revision: https://reviews.llvm.org/D100241
Simon Pilgrim [Sun, 11 Apr 2021 18:01:59 +0000 (19:01 +0100)]
[X86] combineXor - Pull out repeated getOperand() calls. NFCI.
Simon Pilgrim [Sun, 11 Apr 2021 17:41:51 +0000 (18:41 +0100)]
[X86] Fold cmpeq/ne(and(X,Y),Y) --> cmpeq/ne(and(~X,Y),0)
Followup to D100177, handle an similar (demorgan inverse style) case from PR47797 as well
The AVX512 test cases could be further improved if we folded not(iX bitcast(vXi1)) -> (iX bitcast(not(vXi1)))
Alive2: https://alive2.llvm.org/ce/z/AnA_-W
Craig Topper [Sun, 11 Apr 2021 17:19:43 +0000 (10:19 -0700)]
[RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf.
The first source has the same EEW as the destination and the other
source is a scalar so the overlap constraints don't apply to
the unmasked version.
For the masked version we have a constraint that the destination
can't be V0 so that covers the only overlap issue there.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D100217
Craig Topper [Sun, 11 Apr 2021 16:51:45 +0000 (09:51 -0700)]
[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffff) when zext.h is supported.
Similar to what we do for zext.w.
Disable the (srl (and X, 0xffff), C) custom isel when zext.h is
available.
Craig Topper [Sun, 11 Apr 2021 16:40:13 +0000 (09:40 -0700)]
[RISCV] Add i8 and i16 srli and srai tests to Zbb/Zbp test files. NFC
These require the input to be zero or sign extended. If we have
sext.b, sext.h or zext.h instructions we can use them. Otherwise
we need to use a pair of shifts to accomplish the zero/sign extend
and the final shift.
We don't currently use zext.h when it is available.
Roman Lebedev [Sun, 11 Apr 2021 14:58:47 +0000 (17:58 +0300)]
[InstCombine] Improve "get low bit mask upto and including bit X" pattern
https://alive2.llvm.org/ce/z/3u-48R
Roman Lebedev [Sun, 11 Apr 2021 14:20:59 +0000 (17:20 +0300)]
[NFC][InstCombine] Add tests for "get low bit mask upto and including bit X" pattern
Roman Lebedev [Sun, 11 Apr 2021 13:33:47 +0000 (16:33 +0300)]
[InstCombine] (X | Op01C) + Op1C --> X + (Op01C + Op1C) iff the or is actually an add
https://alive2.llvm.org/ce/z/Coc5yf
Roman Lebedev [Sun, 11 Apr 2021 13:49:21 +0000 (16:49 +0300)]
[NFC][InstCombine] Add a few test of adding to add-like or
Roman Lebedev [Sun, 11 Apr 2021 13:37:21 +0000 (16:37 +0300)]
[NFC][LoopVectorize] Autogenerate interleaved-accesses.ll
Roman Lebedev [Sun, 11 Apr 2021 12:38:15 +0000 (15:38 +0300)]
[LoopIdiom] left-shift-until-bittest: set all allowed no-wrap flags on add/sub
I've checked each one of these with alive2,
and this is both correct and precise.
Roman Lebedev [Sun, 11 Apr 2021 12:55:09 +0000 (15:55 +0300)]
[NFC][LoopIdiom] left-shift-until-bittest: add small-bitwidth tests
Roman Lebedev [Sun, 11 Apr 2021 12:51:06 +0000 (15:51 +0300)]
[NFC][LoopIdiom] Regenerate left-shift-until-bittest.ll
Mark de Wever [Sun, 4 Apr 2021 18:11:48 +0000 (20:11 +0200)]
[libc++] [CI] Validate the output of the generated scripts.
This adds a CI job validating that the output of
utils/generate_feature_test_macro_components.py,
libcxx/utils/generate_header_inclusion_tests.py, and
utils/generate_header_tests.py are up to date.
The validation method has been copied from the Format job.
Differential Revision: https://reviews.llvm.org/D99862
Zhang Qing Shan [Sun, 11 Apr 2021 11:25:02 +0000 (19:25 +0800)]
Update personal info in CREDITS.TXT
Sushma Unnibhavi [Sun, 11 Apr 2021 06:53:20 +0000 (12:23 +0530)]
Typo fix
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D100254
Sushma Unnibhavi [Sun, 11 Apr 2021 06:47:49 +0000 (12:17 +0530)]
Missing syntax highlighting for LLVM IR in Langref
Added syntax highlighting
Differential Revision: https://reviews.llvm.org/D100125
Arthur Eubanks [Sun, 11 Apr 2021 06:28:16 +0000 (23:28 -0700)]
Revert "Remove "Rewrite Symbols" from codegen pipeline"
This reverts commit
6210261ecb21c84c9a440a76c0ccbc8ad211bed3.
addr-label.ll crashes on armv7.
Arthur Eubanks [Thu, 1 Apr 2021 06:12:36 +0000 (23:12 -0700)]
Remove "Rewrite Symbols" from codegen pipeline
It breaks up the function pass manager in the codegen pipeline.
With empty parameters, it looks at the -mllvm flag -rewrite-map-file.
This is likely not in use.
Add a check that we only have one function pass manager in the codegen
pipeline.
This required reverting commit
9583a3f2625818b78c0cf6d473cdedb9f23ad82c:
"[AsmPrinter] Delete dead takeDeletedSymbsForFunction()".
This was not NFC as initially thought. By coalescing two function
psas managers, this exposed the reverted code as necessary.
addr-label.ll was crashing due to an emitted blockaddress's block being
removed but the label not emitted.
Some tests relied on the fact that we had a module pass somewhere in the
codegen pipeline.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D99707
patacca [Sat, 10 Apr 2021 21:25:05 +0000 (16:25 -0500)]
[Polly] Partially refactoring of IslAstInfo and IslNodeBuilder to use isl++. NFC.
Polly use algorithms from the Integer Set Library (isl), which is a library written in C and which is incompatible with the rest of the LLVM as it is written in C++.
Changes made:
- Refactoring the following methods of class IslAstInfo
- isParallel() isExecutedInParallel() isReductionParallel() getSchedule() getMinimalDependenceDistance() getBrokenReductions()
- Refactoring the following methods of class IslNodeBuilder
- getReferencesInSubtree() getScheduleForAstNode()
- Refactoring function getBrokenReductionsStr()
- Fixed the mismatching function declaration for getScheduleForAstNode()
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D99971
Roman Lebedev [Sat, 10 Apr 2021 21:23:27 +0000 (00:23 +0300)]
[CVP] @llvm.[us]{min,max}() intrinsics handling
If we can tell that either one of the arguments is taken,
bypass the intrinsic.
Notably, we are indeed fine with non-strict predicate:
* UL: https://alive2.llvm.org/ce/z/69qVW9 https://alive2.llvm.org/ce/z/kNFTKf
https://alive2.llvm.org/ce/z/AvaPw2 https://alive2.llvm.org/ce/z/oxo53i
* UG: https://alive2.llvm.org/ce/z/wxHeGH https://alive2.llvm.org/ce/z/Lf76qx
* SL: https://alive2.llvm.org/ce/z/hkeTGS https://alive2.llvm.org/ce/z/eR_b-W
* SG: https://alive2.llvm.org/ce/z/wEqRm7 https://alive2.llvm.org/ce/z/FpAsVr
Much like with all other comparison handling in CVP,
while we could sort-of handle two Value's,
at least for plain ICmpInst it does not appear to be worthwhile.
This only fires 78 times on test-suite + dt + rs,
but we don't canonicalize to these yet. (only SCEV produces them)
Roman Lebedev [Sat, 10 Apr 2021 21:10:47 +0000 (00:10 +0300)]
[NFC][CVP] Add tests for @llvm.[us]{min,max}() intrinsics
Nikita Popov [Sat, 10 Apr 2021 20:17:35 +0000 (22:17 +0200)]
[IVUsers] Check LoopSimplify cache earlier (NFC)
Check the cache before calling isLoopSimplifyForm(). Otherwise we'd
always perform the check for the innermost loop and only skip it
for dominating loops.
Wenlei He [Thu, 8 Apr 2021 06:06:39 +0000 (23:06 -0700)]
[CSSPGO] Fix dangling context strings and improve profile order consistency and error handling
This patch fixed the following issues along side with some refactoring:
1. Fix bugs where StringRef for context string out live the underlying std::string. We now keep string table in profile generator to hold std::strings. We also do the same for bracketed context strings in profile writer.
2. Make sure profile output strictly follow (total sample, name) order. Previously, there's inconsistency between ProfileMap's key and FunctionSamples's name, leading to inconsistent ordering. This is now fixed by introducing context profile canonicalization. Assertions are also added to make sure ProfileMap's key and FunctionSamples's name are always consistent.
3. Enhanced error handling for profile writing to make sure we bubble up errors properly for both llvm-profgen and llvm-profdata when string table is not populated correctly for extended binary profile.
4. Keep all internal context representation bracket free. This avoids creating new strings for context trimming, merging and preinline. getNameWithContext API is now simplied accordingly.
5. Factor out the code for context trimming and merging into SampleContextTrimmer in SampleProf.cpp. This enables llvm-profdata to use the trimmer when merging profiles. Changes in llvm-profgen will be in separate patch.
Differential Revision: https://reviews.llvm.org/D100090
Roman Lebedev [Sat, 10 Apr 2021 18:24:29 +0000 (21:24 +0300)]
[NFC][JumpThreading] Increment 'NumFolds' statistic all places terminator becomes uncond
Roman Lebedev [Sat, 10 Apr 2021 18:23:20 +0000 (21:23 +0300)]
[NFC][CVP] Add statistic for function pointer argument non-null-ness deduction
Roman Lebedev [Sat, 10 Apr 2021 18:05:17 +0000 (21:05 +0300)]
[CVP] LVI: Use in-block values when checking value signedness domain
This has a huge positive impact on all the folds that use these helpers,
as it can be seen on vanilla test-suite + rawspeed + darktable:
correlated-value-propagation.NumSRems +75.68% (+ 28)
correlated-value-propagation.NumAShrs +63.87% (+198)
correlated-value-propagation.NumSDivs +49.42% (+127)
correlated-value-propagation.NumSExt + 8.85% (+593)
correlated-value-propagation.NumUDivURemsNarrowed + 8.65% (+34)
... while having pretty minimal compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=
e8c7f43e2c2c6f3581ec1c6489ec21ad9f98958a&to=
4cd197711e58ee1b2faeee0c35eea54540185569&stat=instructions
Roman Lebedev [Sat, 10 Apr 2021 17:45:37 +0000 (20:45 +0300)]
[NFC][LVI] getPredicateAt(): drop default value for UseBlockValue
The default is likely wrong.
Out of all the callees, only a single one needs to pass-in false (JumpThread),
everything else either already passes true, or should pass true.
Until the default is flipped, at least make it harder to unintentionally
add new callees with UseBlockValue=false.
Roman Lebedev [Sat, 10 Apr 2021 17:34:27 +0000 (20:34 +0300)]
[NFC] Rename LimitingIntrinsic into MinMaxIntrinsic
As requested in post-commit review
peter klausler [Wed, 7 Apr 2021 20:21:10 +0000 (13:21 -0700)]
[flang] Accept & fold IEEE_SELECTED_REAL_KIND
F18 supports the standard intrinsic function SELECTED_REAL_KIND
but not its synonym in the standard module IEEE_ARITHMETIC
named IEEE_SELECTED_REAL_KIND until this patch.
Differential Revision: https://reviews.llvm.org/D100066
Whisperity [Sat, 10 Apr 2021 16:48:22 +0000 (18:48 +0200)]
[libtooling][clang-tidy] Fix off-by-one rendering issue with SourceRanges
There was an off-by-one issue with calculating the *exact* end location
of token ranges (as given by SomeDecl->getSourceRange()) which resulted in:
xxx(something)
^~~~~~~~ // Note the missing ~ under the last character.
In addition, a test is added to keep the behaviour in check in the future.
This patch hotfixes commit
3b677b81cec7b3c5132aee8fccc30252d87deb69.
Roman Lebedev [Sat, 10 Apr 2021 16:37:59 +0000 (19:37 +0300)]
[NFC][ConstantRange] Add 'icmp' helper method
"Does the predicate hold between two ranges?"
Not very surprisingly, some places were already doing this check,
without explicitly naming the algorithm, cleanup them all.
Roman Lebedev [Sat, 10 Apr 2021 16:37:53 +0000 (19:37 +0300)]
Revert "[NFC][ConstantRange] Add 'icmp' helper method"
This reverts commit
17cf2c94230bc107e7294ef84fad3b47f4cd1b73.
Roman Lebedev [Sat, 10 Apr 2021 16:37:16 +0000 (19:37 +0300)]
Revert "zz"
It wasn't meant to be committed, two commits should have been squashed.
This reverts commit
0c184154969c020db416bd7066af80ffd2a27ac4.
Roman Lebedev [Sat, 10 Apr 2021 14:58:47 +0000 (17:58 +0300)]
[NFC][ConstantRange] Add 'icmp' helper method
"Does the predicate hold between two ranges?"
Not very surprisingly, some places were already doing this check,
without explicitly naming the algorithm, cleanup them all.
Roman Lebedev [Sat, 10 Apr 2021 14:10:51 +0000 (17:10 +0300)]
zz
Whisperity [Mon, 15 Mar 2021 16:06:03 +0000 (17:06 +0100)]
[libtooling][clang-tidy] Fix diagnostics not highlighting fed SourceRanges
Fixes bug http://bugs.llvm.org/show_bug.cgi?id=49000.
This patch allows Clang-Tidy checks to do
diag(X->getLocation(), "text") << Y->getSourceRange();
and get the highlight of `Y` as expected:
warning: text [blah-blah]
xxx(something)
^ ~~~~~~~~~
Reviewed-By: aaron.ballman, njames93
Differential Revision: http://reviews.llvm.org/D98635
Roman Lebedev [Sat, 10 Apr 2021 12:52:28 +0000 (15:52 +0300)]
[CVP] @llvm.abs() handling
Iff we know the sigdness domain of the argument,
we can either skip @llvm.abs, or do negation directly.
Notably, INT_MIN can belong to either domain:
* X u<= INT_MIN --> X is always fine
https://alive2.llvm.org/ce/z/QB8j-C https://alive2.llvm.org/ce/z/7sFKpS
* X s<= 0 --> -X is always fine
https://alive2.llvm.org/ce/z/QbGSyq https://alive2.llvm.org/ce/z/APsN84
If all else fails, try to inferr NSW flag:
https://alive2.llvm.org/ce/z/qCJfYm
Roman Lebedev [Sat, 10 Apr 2021 12:41:43 +0000 (15:41 +0300)]
[NFC][CVP] Add `@llvm.abs` test cases
Saurabh Jha [Sat, 10 Apr 2021 09:25:34 +0000 (10:25 +0100)]
[Matrix] Implement C-style explicit type conversions for matrix types.
This implements C-style type conversions for matrix types, as specified
in clang/docs/MatrixTypes.rst.
Fixes PR47141.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D99037
Hsiangkai Wang [Fri, 9 Apr 2021 23:02:08 +0000 (07:02 +0800)]
[RISCV][Clang] Add RVV vleff intrinsic functions.
Reviewed By: craig.topper, liaolucy, jrtc27, khchen
Differential Revision: https://reviews.llvm.org/D99151
Roman Lebedev [Sat, 10 Apr 2021 07:41:16 +0000 (10:41 +0300)]
Temporairly revert "[CGCall] Annotate `this` argument with alignment"
As per @jyknight, "It seems like there's a bug with vtable thunks getting the wrong information."
See https://reviews.llvm.org/D99790#2680857, https://godbolt.org/z/MxhYMe1q7
This reverts commit
0aa0458f1429372038ca6a4edc7e94c96cd9a753.
dfukalov [Tue, 16 Feb 2021 19:20:06 +0000 (22:20 +0300)]
[AMDGPU][CostModel] Refine cost model for control-flow instructions.
Added cost estimation for switch instruction, updated costs of branches, fixed
phi cost.
Had to increase `-amdgpu-unroll-threshold-if` default value since conditional
branch cost (size) was corrected to higher value.
Test renamed to "control-flow.ll".
Removed redundant code in `X86TTIImpl::getCFInstrCost()` and
`PPCTTIImpl::getCFInstrCost()`.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D96805
Ben Shi [Sat, 10 Apr 2021 03:23:55 +0000 (11:23 +0800)]
[clang][AVR] Support variable decorator '__flash'
Reviewed By: Anastasia
Differential Revision: https://reviews.llvm.org/D96853
Duncan P. N. Exon Smith [Fri, 9 Apr 2021 01:43:21 +0000 (18:43 -0700)]
Support: Add move semantics to mapped_file_region
Update llvm::sys::fs::mapped_file_region to have a move constructor and
a move assignment operator, allowing it to be used as an Optional. Also,
update FileOutputBuffer's OnDiskBuffer to take advantage of this,
avoiding an extra allocation from the unique_ptr.
A nice follow-up would be to make the mapped_file_region constructor
private and replace its use with a factory function, such as
mapped_file_region::create(), that returns an Expected (or ErrorOr). I
don't plan on doing that immediately, but I might swing back later.
No functionality change, besides the saved allocation in OnDiskBuffer.
Differential Revision: https://reviews.llvm.org/D100159
peter klausler [Wed, 7 Apr 2021 20:14:14 +0000 (13:14 -0700)]
[flang] RANDOM_NUMBER, RANDOM_SEED, RANDOM_INIT in runtime
Add APIs, initial non-coarray implementations, and unit
tests for the intrinsic subroutines for pseudo-random
number generation.
Differential Revision: https://reviews.llvm.org/D100064
Jez Ng [Fri, 9 Apr 2021 23:47:10 +0000 (19:47 -0400)]
[lld-macho][nfc] Remove DYSYM8 reloc attribute
It's likely redundant, per discussion with @gkm. The BYTE8
attribute covers the bit width requirement already.
Reviewed By: #lld-macho, gkm
Differential Revision: https://reviews.llvm.org/D100133
peter klausler [Wed, 7 Apr 2021 20:17:39 +0000 (13:17 -0700)]
[flang] Enforce a limit on recursive PDT instantiations
For pernicious test cases with explicit non-constant actual
type parameter expressions in components, e.g.:
type :: t(k)
integer, kind :: k
type(t(k+1)), pointer :: p
end type
we should detect the infinite recursion and complain rather
than looping until the stack overflows.
Differential Revision: https://reviews.llvm.org/D100065
Mitch Phillips [Fri, 9 Apr 2021 22:36:11 +0000 (15:36 -0700)]
Revert "[AMDGPU] Remove MachineDCE after SIFoldOperands"
This reverts commit
5a0117b2d0eaedffeeb393bd9915f11cccfe241b.
Reason: Dependent change
d19a42eba98fe853dd52f7dc89d8cd2727c7fc1c broke
the ASan buildbots.
Mitch Phillips [Fri, 9 Apr 2021 22:02:33 +0000 (15:02 -0700)]
Revert "[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs"
This reverts commit
d19a42eba98fe853dd52f7dc89d8cd2727c7fc1c.
Reason: Broke the ASan buildbots. See the original phabricator review
for more details: https://reviews.llvm.org/D100188
Jessica Paquette [Mon, 9 Nov 2020 21:35:41 +0000 (13:35 -0800)]
[AArch64][GlobalISel] Swap compare operands when it may be profitable
This adds support for swapping comparison operands when it may introduce new
folding opportunities.
This is roughly the same as the code added to AArch64ISelLowering in
162435e7b5e026b9f988c730bb6527683f6aa853.
For an example of a testcase which exercises this, see
llvm/test/CodeGen/AArch64/swap-compare-operands.ll
(Godbolt for that testcase: https://godbolt.org/z/43WEMb)
The idea behind this is that sometimes, we may be able to fold away, say, a
shift or extend in a compare by swapping its operands.
e.g. in the case of this compare:
```
lsl x8, x0, #1
cmp x8, x1
cset w0, lt
```
The following is equivalent:
```
cmp x1, x0, lsl #1
cset w0, gt
```
Most of the code here is just a reimplementation of what already exists in
AArch64ISelLowering.
(See `getCmpOperandFoldingProfit` and `getAArch64Cmp` for the equivalent code.)
Note that most of the AND code in the testcase doesn't actually fold. It seems
like we're missing selection support for that sort of fold right now, since SDAG
happily folds these away (e.g testSwapCmpWithShiftedZeroExtend8_32 in the
original .ll testcase)
Differential Revision: https://reviews.llvm.org/D89422
peter klausler [Wed, 7 Apr 2021 20:23:45 +0000 (13:23 -0700)]
[flang] Check for conflicting BIND(C) names
Check for two or more symbols that define a data object or entry point
with the same interoperable BIND(C) name.
Differential Revision: https://reviews.llvm.org/D100067
Roman Lebedev [Fri, 9 Apr 2021 21:31:56 +0000 (00:31 +0300)]
[Analysis] isDereferenceableAndAlignedPointer(): recurse into select's hands
By doing this within the method itself,
we support traversing multiple levels of selects (TODO: PHI's),
fixing the SROA `std::clamp()` testcase.
Fixes https://bugs.llvm.org/show_bug.cgi?id=47271
Mostly fixes https://bugs.llvm.org/show_bug.cgi?id=49909
Roman Lebedev [Fri, 9 Apr 2021 21:26:18 +0000 (00:26 +0300)]
[NFC][SROA] Add C++'s `std::clamp()` testcase from PR47271/PR49909
Mitch Phillips [Fri, 9 Apr 2021 20:46:24 +0000 (13:46 -0700)]
[ASan] Allow new/delete replacement by making interceptors weak
ASan declares these functions as strongly-defined, which results in
'duplicate symbol' errors when trying to replace them in user code when
linking the runtimes statically.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D100220
Kostya Kortchinsky [Wed, 7 Apr 2021 19:39:24 +0000 (12:39 -0700)]
[scudo][standalone] Use BatchClassId in drain rather than 0
D99763 fixed `SizeClassAllocatorLocalCache::drain` but with the
assumption that `BatchClassId` is 0 - which is currently true. I would
rather not make the assumption so that if we ever change the ID of
the batch class, the loop would still work. Since `BatchClassId` is
used more often in `local_cache.h`, introduce a constant so that we
don't have to specify `SizeClassMap::` every time.
Differential Revision: https://reviews.llvm.org/D100062
Mitch Phillips [Fri, 9 Apr 2021 20:32:12 +0000 (13:32 -0700)]
Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"
This reverts commit
16fe741c69429235210c03c46420f8fa6aece4a1.
Reason: Broke the UBSan buildbots. More information available in the
phabricator review: https://reviews.llvm.org/D99375
Nicolas Vasilache [Fri, 9 Apr 2021 10:37:44 +0000 (10:37 +0000)]
[mlir] NFC - Add help functions to scf.ForOp
This revision adds 2 helperr functions that help tie OpOperands and
BlockArguments in scf.ForOp without having to use the internal implementation
details.
cchen [Fri, 9 Apr 2021 20:21:13 +0000 (15:21 -0500)]
[OpenMP51][DOCS] Claimed masked construct and report current patch, NFC.
Jay Foad [Thu, 8 Apr 2021 16:10:54 +0000 (17:10 +0100)]
[AMDGPU] Remove MachineDCE after SIFoldOperands
Remove the MachineDCE pass after the first SIFoldOperands pass now
that SIFoldOperands deletes its own dead instructions.
Differential Revision: https://reviews.llvm.org/D100189
Jay Foad [Fri, 9 Apr 2021 12:52:35 +0000 (13:52 +0100)]
[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs
This is fairly cheap to implement and means less work for future
passes like MachineDCE.
Differential Revision: https://reviews.llvm.org/D100188
Alina Sbirlea [Fri, 9 Apr 2021 06:56:34 +0000 (23:56 -0700)]
[MSSA] Rename uses in IDF regardless of new def position in basic block.
When inserting a new def and renaming of uses is asked, always compute
IDF and do the renaming for the blocks with Phis in that IDF.
Resolves PR49859.
Differential Revision: https://reviews.llvm.org/D100163
Louis Dionne [Fri, 9 Apr 2021 19:19:42 +0000 (15:19 -0400)]
[libc++] NFC: Move unused include of <limits> to allocator_traits.h
The include should have been moved when I split allocator_traits.h out
of memory.
Stanislav Mekhanoshin [Fri, 9 Apr 2021 19:19:42 +0000 (12:19 -0700)]
[AMDGPU] Added udot2 op_sel test. NFC.
Stefan Pintilie [Fri, 9 Apr 2021 19:07:13 +0000 (14:07 -0500)]
Add correct types to the xxsplti32dx pattern.
Regiser types for xxsplti32dx for two td file patterns was incorrect.
Fixed the two types and added a test case that was reduced from a larger
failing test.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D100223
Shafik Yaghmour [Fri, 9 Apr 2021 19:05:36 +0000 (12:05 -0700)]
[LLDB][NFC] Add clarifying comments for AddCXXSummary and AddCXXSynthetic
Adding comments to AddCXXSynthetic and AddCXXSummary to better explain what they are doing.
cchen [Fri, 9 Apr 2021 19:00:36 +0000 (14:00 -0500)]
[OpenMP51] Initial support for masked directive and filter clause
Adds basic parsing/sema/serialization support for the #pragma omp masked
directive.
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D99995
Duncan P. N. Exon Smith [Fri, 9 Apr 2021 18:48:40 +0000 (11:48 -0700)]
Support: Remove code duplication for mapped_file_region accessors, NFC
Martin Storsjö [Tue, 23 Mar 2021 12:33:11 +0000 (14:33 +0200)]
[libcxx] [test] Add more tests for renaming directories in fs.op.rename
This was requested during the review of D98640.
Differential Revision: https://reviews.llvm.org/D99982
Martin Storsjö [Thu, 11 Mar 2021 13:01:58 +0000 (15:01 +0200)]
[libcxx] [test] Use GetWindowsInaccessibleDir() in a couple more tests
Differential Revision: https://reviews.llvm.org/D98443
Martin Storsjö [Thu, 11 Mar 2021 19:42:13 +0000 (21:42 +0200)]
[libcxx] [test] Use GetWindowsInaccessibleDir() instead of dirs with perms::none in fs.op.is_*
Differential Revision: https://reviews.llvm.org/D98442
Thomas Lively [Fri, 9 Apr 2021 18:21:49 +0000 (11:21 -0700)]
[WebAssembly] Add shuffles as an option for lowering BUILD_VECTOR
When lowering a BUILD_VECTOR SDNode, we choose among various possible vector
creation instructions in an attempt to minimize the total number of instructions
used. We previously considered using swizzles, consts, and splats, and this
patch adds shuffles as well. A common pattern that now lowers to shuffles is
when two 64-bit vectors are concatenated. Previously, concatenations generally
lowered to sequences of extract_lane and replace_lane instructions when they
could have been a single shuffle.
Differential Revision: https://reviews.llvm.org/D100018
Alex Richardson [Thu, 6 Dec 2018 12:22:08 +0000 (12:22 +0000)]
Handle alloc_size attribute on function pointers
I have been trying to statically find and analyze all calls to heap
allocation functions to determine how many of them use sizes known at
compile time vs only at runtime. While doing so I saw that quite a few
projects use replaceable function pointers for heap allocation and noticed
that clang was not able to annotate functions pointers with alloc_size.
I have changed the Sema checks to allow alloc_size on all function pointers
and typedefs for function pointers now and added checks that these
attributes are propagated to the LLVM IR correctly.
With this patch we can also compute __builtin_object_size() for calls to
allocation function pointers with the alloc_size attribute.
Reviewed By: aaron.ballman, erik.pilkington
Differential Revision: https://reviews.llvm.org/D55212
Alex Richardson [Fri, 9 Apr 2021 15:58:58 +0000 (16:58 +0100)]
[builtins] Avoid enum name conflicts with fenv.h
After a follow-up change (D98332) this header can be included the same time
as fenv.h when running the tests. To avoid enum members conflicting with
the macros/enums defined in the host fenv.h, prefix them with CRT_.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D98333
Alex Richardson [Fri, 9 Apr 2021 15:58:16 +0000 (16:58 +0100)]
[TableGen] Report an error message on a missing comma
I recently forgot a comma in a defm argument list and tablegen just
failed with exit code 1 without printing an error message. I believe
this issue was introduced in
a9fc44c5573208859c2550382755098d750fc47d.
This change prints the following instead:
.../clang/include/clang/Driver/Options.td:569:3: error: Expected comma before next argument
Reviewed By: Paul-C-Anagnostopoulos
Differential Revision: https://reviews.llvm.org/D100178
Amara Emerson [Fri, 9 Apr 2021 17:39:59 +0000 (10:39 -0700)]
[AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR.
Fixes PR49904
Stefan Pintilie [Fri, 9 Apr 2021 17:05:52 +0000 (12:05 -0500)]
[PowerPC] Add ROP Protection Instructions for PowerPC
There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.
These instructions will be used for ROP Protection.
This patch adds the four instructions.
Reviewed By: nemanjai, amyk, #powerpc
Differential Revision: https://reviews.llvm.org/D99375
Paul Robinson [Fri, 9 Apr 2021 16:40:00 +0000 (09:40 -0700)]
[RGT] Disable some tests on Windows at compile-time, not runtime
These show up as un-executed on non-Windows hosts.
Found by the Rotten Green Tests project.
Adrian Prantl [Fri, 9 Apr 2021 16:48:33 +0000 (09:48 -0700)]
Update the linkage name of coro-split functions in the debug info.
This patch updates the linkage name in the DISubprogram of coro-split
functions, which is particularly important for Swift, where the
funclets have a special name mangling. This patch does not affect C++
coroutines, since the DW_AT_specification is expected to hold the
(original) linkage name. I believe this is mostly due to limitations
in AsmPrinter, so we might be able to relax this restriction in the
future.
Differential Revision: https://reviews.llvm.org/D99693
Sanjay Patel [Fri, 9 Apr 2021 15:52:47 +0000 (11:52 -0400)]
[PhaseOrdering] add test for llvm.expect; NFC