Chia-Wei Wang [Fri, 22 Oct 2021 00:06:16 +0000 (10:36 +1030)]
soc: aspeed: Add UART routing support
Add driver support for the UART routing control. Users can perform
runtime configuration of the RX muxes among the UART controllers and
the UART IO pins.
The sysfs interface is also exported for the convenience of routing paths
check and update.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Tested-by: Lei YU <yulei.sh@bytedance.com>
Link: https://lore.kernel.org/r/20210927023053.6728-5-chiawei_wang@aspeedtech.com
Link: https://lore.kernel.org/r/20211022000616.481772-1-joel@jms.id.au'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 22 Oct 2021 15:31:39 +0000 (17:31 +0200)]
Merge tag 'soc-fsl-next-v5.16' of git://git./linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.16
DPIO Driver
- Code cleanup and fix compile warning
RCMP and Guts Driver
- Make use of the helper function devm_platform_ioremap_resource()
* tag 'soc-fsl-next-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: dpio: rename the enqueue descriptor variable
soc: fsl: dpio: use an explicit NULL instead of 0
soc: fsl: rcpm: Make use of the helper function devm_platform_ioremap_resource()
soc: fsl: guts: Make use of the helper function devm_platform_ioremap_resource()
Link: https://lore.kernel.org/r/20211022010027.11866-2-leoyang.li@nxp.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Youri Querry [Wed, 21 Apr 2021 13:56:44 +0000 (09:56 -0400)]
soc: fsl: dpio: rename the enqueue descriptor variable
The struct qbman_eq_desc 'd' variable declaration is covering one of the
function parameters. This has no functional impact since this function
parameter was not used after the new declaration.
Even so, rename the variable so that we make the code more readable.
Fixes:
3b2abda7d28c ("soc: fsl: dpio: Replace QMAN array mode with ring mode enqueue")
Signed-off-by: Youri Querry <youri.querry_1@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Ioana Ciornei [Thu, 14 Oct 2021 14:49:22 +0000 (17:49 +0300)]
soc: fsl: dpio: use an explicit NULL instead of 0
Use an explicit NULL pointer when calling qbman_swp_enqueue_multiple()
instead of a plain integer. Without this fix, we get the following
compile time error.
drivers/soc/fsl/dpio/dpio-service.c:466:60: warning: Using plain integer as NULL pointer
Fixes:
9d98809711ae ("soc: fsl: dpio: Adding QMAN multiple enqueue interface")
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Cai Huoqing [Wed, 8 Sep 2021 07:16:30 +0000 (15:16 +0800)]
soc: fsl: rcpm: Make use of the helper function devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Cai Huoqing [Wed, 8 Sep 2021 07:16:29 +0000 (15:16 +0800)]
soc: fsl: guts: Make use of the helper function devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Jens Wiklander [Thu, 21 Oct 2021 12:55:39 +0000 (14:55 +0200)]
optee: smc_abi.c: add missing #include <linux/mm.h>
Adds missing #include <linux/mm.h> drivers/tee/optee/smc_abi.c to fix
compile errors like:
drivers/tee/optee/smc_abi.c:405:15: error: implicit
declaration of function 'page_to_section'
[-Werror,-Wimplicit-function-declaration]
optee_page = page_to_phys(*pages) +
^
arch/arm/include/asm/memory.h:148:43: note: expanded from
macro 'page_to_phys'
^
include/asm-generic/memory_model.h:52:21: note: expanded
from macro 'page_to_pfn'
^
include/asm-generic/memory_model.h:35:14: note: expanded
from macro '__page_to_pfn'
int __sec = page_to_section(__pg); \
^
drivers/tee/optee/smc_abi.c:405:15: note: did you mean
'__nr_to_section'?
arch/arm/include/asm/memory.h:148:43: note: expanded from
macro 'page_to_phys'
^
include/asm-generic/memory_model.h:52:21: note: expanded
from macro 'page_to_pfn'
^
include/asm-generic/memory_model.h:35:14: note: expanded
from macro '__page_to_pfn'
int __sec = page_to_section(__pg); \
^
include/linux/mmzone.h:1365:35: note: '__nr_to_section'
declared here
static inline struct mem_section *__nr_to_section(unsigned long nr)
Fixes:
c51a564a5b48 ("optee: isolate smc abi")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Link: https://lore.kernel.org/r/20211021125539.3858495-1-jens.wiklander@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 Oct 2021 19:34:20 +0000 (21:34 +0200)]
Merge tag 'memory-controller-drv-5.16-2' of git://git./linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.16, part two
1. Convert LPDDR2 bindings to dtschema and extend them with new
properties.
2. Tegra 20 EMC: support matching timings by LPDDR2 configuration from
devicetree.
* tag 'memory-controller-drv-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: tegra20-emc: Add runtime dependency on devfreq governor module
memory: tegra20-emc: Support matching timings by LPDDR2 configuration
memory: Add LPDDR2-info helpers
dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node
dt-bindings: Add vendor prefix for Elpida Memory
dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F
dt-bindings: memory: lpddr2: Add revision-id properties
dt-bindings: memory: lpddr2: Convert to schema
dt-bindings: Relocate DDR bindings
Link: https://lore.kernel.org/r/20211021093002.118192-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Dmitry Osipenko [Tue, 19 Oct 2021 23:15:24 +0000 (02:15 +0300)]
memory: tegra20-emc: Add runtime dependency on devfreq governor module
Tegra20 EMC driver uses simple devfreq governor. Add simple devfreq
governor to the list of the Tegra20 EMC driver module softdeps to allow
userspace initramfs tools like dracut to automatically pull the devfreq
module into ramfs image together with the EMC module.
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Suggested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20211019231524.888-1-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Arnd Bergmann [Wed, 20 Oct 2021 21:26:52 +0000 (23:26 +0200)]
Merge tag 'reset-for-v5.16' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.16
Allow building the reset-brcmstb-rescal driver as module, add reset
lines for the Uniphier PXs3 audio and video input subsystems and
bindings for the Uniphier NX1 SoC, and add lan966x switch reset support
to the reset-microchip-sparx5 driver.
* tag 'reset-for-v5.16' of git://git.pengutronix.de/pza/linux:
reset: mchp: sparx5: Extend support for lan966x
dt-bindings: reset: Add lan966x support
reset: uniphier: Add NX1 reset support
dt-bindings: reset: uniphier: Add NX1 reset control binding
reset: uniphier: Add audio system and video input reset control for PXs3
reset: Allow building Broadcom STB RESCAL as module
Link: https://lore.kernel.org/r/96e686f78f0e42bad666df5ec0cbcb2dcdc270a3.camel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 20 Oct 2021 15:46:57 +0000 (17:46 +0200)]
Merge tag 'optee-ffa-for-v5.16' of git://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers
Add FF-A support in OP-TEE driver
Adds supports for the OP-TEE driver to communicate with secure world
using FF-A [1] as transport.
[1] https://developer.arm.com/documentation/den0077/latest
* tag 'optee-ffa-for-v5.16' of git://git.linaro.org/people/jens.wiklander/linux-tee:
optee: add FF-A support
optee: isolate smc abi
optee: refactor driver with internal callbacks
optee: simplify optee_release()
tee: add sec_world_id to struct tee_shm
tee: optee: Fix missing devices unregister during optee_remove
tee/optee/shm_pool: fix application of sizeof to pointer
Link: https://lore.kernel.org/r/20211018121324.GA2943530@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Nikita Shubin [Mon, 18 Oct 2021 10:31:05 +0000 (12:31 +0200)]
ep93xx: clock: convert in-place to COMMON_CLK
Converted in-place without moving file to drivers/clk.
tested on ts7250 (EP9302).
Only setting rate and change parent tested for, as they
are missing on ts7250:
- video
- I2S
- ADC/KEYPAD
- PWM
Only video and I2S clock are interesting, as they are
GATE + double DIV + MUX, all other are pretty much
common but require ep93xx_syscon_swlocked_write to set
registers.
Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Acked-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20211018103105.146380-3-alexander.sverdlin@gmail.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Alexander Sverdlin [Mon, 18 Oct 2021 10:31:04 +0000 (12:31 +0200)]
ASoC: cirrus: i2s: Prepare clock before using it
Use clk_prepare_enable()/clk_disable_unprepare() in preparation for switch
to Common Clock Framework, otherwise the following is visible:
WARNING: CPU: 0 PID: 97 at drivers/clk/clk.c:1011 clk_core_enable+0x9c/0xbc
Enabling unprepared mclk
...
Hardware name: Cirrus Logic EDB9302 Evaluation Board
...
clk_core_enable
clk_core_enable_lock
ep93xx_i2s_hw_params
snd_soc_dai_hw_params
soc_pcm_hw_params
snd_pcm_hw_params
snd_pcm_ioctl
...
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Acked-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20211018103105.146380-2-alexander.sverdlin@gmail.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 20 Oct 2021 15:45:32 +0000 (17:45 +0200)]
Merge tag 'sunxi-drivers-for-5.16-1' of git://git./linux/kernel/git/sunxi/linux into arm/drivers
Some new drivers changes for the Allwinner SoCs, converting to a helper
and improving logging.
* tag 'sunxi-drivers-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
bus: sun50i-de2: Adjust printing error message
soc: sunxi_sram: Make use of the helper function devm_platform_ioremap_resource()
Link: https://lore.kernel.org/r/ad0aa469-9e1b-4bb6-a116-92648ed774fa.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 20 Oct 2021 14:53:32 +0000 (16:53 +0200)]
Merge tag 'imx-drivers-5.16' of git://git./linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.16:
- Select REGMAP_MMIO for i.MX GPCv2 driver to avoid build issue.
- A couple of i.MX GPCv2 driver changes from Marek Vasut to turn
domain->pgc into bitfield for i.MX8MM GPU domain support.
- A series from Lucas Stach adding support of i.MX8MM nested power
domains like VPUMIX and DISPMIX which contains the ADB and BLK_CTRL.
- An off-by-one fix on Lucas' i.MX8M blk-ctrl driver code.
* tag 'imx-drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: imx8m-blk-ctrl: off by one in imx8m_blk_ctrl_xlate()
soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
soc: imx: add i.MX8M blk-ctrl driver
soc: imx: gpcv2: support system suspend/resume
soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
soc: imx: gpcv2: add domain option to keep domain clocks enabled
soc: imx: gpcv2: add lockdep annotation
Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
soc: imx: gpcv2: allow to disable individual power domains
imx: soc: Select REGMAP_MMIO
soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
soc: imx: gpcv2: Turn domain->pgc into bitfield
Link: https://lore.kernel.org/r/20211016140138.1603-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Horatiu Vultur [Mon, 18 Oct 2021 09:15:22 +0000 (11:15 +0200)]
reset: mchp: sparx5: Extend support for lan966x
This patch extends sparx5 driver to support also the lan966x. The
process to reset the switch is the same only it has different offsets.
Therefore make the driver more generic and add support for lan966x.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Steen Hegelund <steen.hegelund@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20211018091522.1113510-3-horatiu.vultur@microchip.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Horatiu Vultur [Mon, 18 Oct 2021 09:15:21 +0000 (11:15 +0200)]
dt-bindings: reset: Add lan966x support
This patch extends the existing file microchip,rst.yaml to support
also the lan966x. For this is added only a new compatible string.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20211018091522.1113510-2-horatiu.vultur@microchip.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Jens Wiklander [Wed, 21 Jul 2021 15:45:21 +0000 (17:45 +0200)]
optee: add FF-A support
Adds support for using FF-A [1] as transport to the OP-TEE driver.
Introduces struct optee_msg_param_fmem which carries all information
needed when OP-TEE is calling FFA_MEM_RETRIEVE_REQ to get the shared
memory reference mapped by the hypervisor in S-EL2. Register usage is
also updated to include the information needed.
The FF-A part of this driver is enabled if CONFIG_ARM_FFA_TRANSPORT is
enabled.
[1] https://developer.arm.com/documentation/den0077/latest
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Wed, 21 Jul 2021 14:30:28 +0000 (16:30 +0200)]
optee: isolate smc abi
Isolate the ABI based on raw SMCs. Code specific to the raw SMC ABI is
moved into smc_abi.c. This makes room for other ABIs with a clear
separation.
The driver changes to use module_init()/module_exit() instead of
module_platform_driver(). The platform_driver_register() and
platform_driver_unregister() functions called directly to keep the same
behavior. This is needed because module_platform_driver() is based on
module_driver() which can only be used once in a module.
A function optee_rpc_cmd() is factored out from the function
handle_rpc_func_cmd() to handle the ABI independent part of RPC
processing.
This patch is not supposed to change the driver behavior, it's only a
matter of reorganizing the code.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 25 Mar 2021 14:08:50 +0000 (15:08 +0100)]
optee: refactor driver with internal callbacks
The OP-TEE driver is refactored with three internal callbacks replacing
direct calls to optee_from_msg_param(), optee_to_msg_param() and
optee_do_call_with_arg().
These functions a central to communicating with OP-TEE in secure world
by using the SMC Calling Convention directly.
This refactoring makes room for using other primitives to communicate
with OP-TEE in secure world while being able to reuse as much as
possible from the present driver.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 25 Mar 2021 14:08:46 +0000 (15:08 +0100)]
optee: simplify optee_release()
Simplifies optee_release() with a new helper function,
optee_close_session_helper() which has been factored out from
optee_close_session().
A separate optee_release_supp() is added for the supplicant device.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Jens Wiklander [Thu, 25 Mar 2021 14:08:44 +0000 (15:08 +0100)]
tee: add sec_world_id to struct tee_shm
Adds sec_world_id to struct tee_shm which describes a shared memory
object. sec_world_id can be used by a driver to store an id assigned by
secure world.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:59 +0000 (01:46 +0300)]
memory: tegra20-emc: Support matching timings by LPDDR2 configuration
ASUS Transformer TF101 doesn't provide RAM code and in this case memory
timings should be selected based on identity information read out from
SDRAM chip. Support matching timings by LPDDR2 configuration.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20211006224659.21434-10-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:58 +0000 (01:46 +0300)]
memory: Add LPDDR2-info helpers
Add common helpers for reading and parsing standard LPDDR2 configuration
properties.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20211006224659.21434-9-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:57 +0000 (01:46 +0300)]
dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node
Some Tegra20 boards don't have RAM code stored in NVMEM, which is used for
the memory chip identification and the identity information should be read
out from LPDDR2 chip in this case. Document new sub-node containing generic
LPDDR2 properties that will be used for the memory chip identification if
RAM code isn't available. The identification is done by reading out memory
configuration values from generic LPDDR2 mode registers of SDRAM chip and
comparing them with the values of device-tree 'lpddr2' sub-node.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211006224659.21434-8-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:55 +0000 (01:46 +0300)]
dt-bindings: Add vendor prefix for Elpida Memory
Elpida Memory designed, manufactured and sold dynamic random-access
memory (DRAM) products. It was acquired by Micron Technology in 2013,
still there are many devices with components from Elpida. Document the
vendor prefix.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211006224659.21434-6-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:54 +0000 (01:46 +0300)]
dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F
Elpida B8132B2PB-6D-F memory chip is used by ASUS Transformer TF101
tablet, add compatible for it. We need to specify this compatible it
for a device-tree node containing corresponding memory timings in order
to allow software to match the timings with the detected hardware.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211006224659.21434-5-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:53 +0000 (01:46 +0300)]
dt-bindings: memory: lpddr2: Add revision-id properties
Add optional revision-id standard LPDDR2 properties which will help to
identify memory chip.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211006224659.21434-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:52 +0000 (01:46 +0300)]
dt-bindings: memory: lpddr2: Convert to schema
Convert LPDDR2 binding to schema. I removed obsolete ti,jedec-lpddr2-*
compatibles since they were never used by device-trees and by the code.
I also changed "Elpida" compatible prefix to lowercase "elpida".
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211006224659.21434-3-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dmitry Osipenko [Wed, 6 Oct 2021 22:46:51 +0000 (01:46 +0300)]
dt-bindings: Relocate DDR bindings
Move DDR bindings to memory-controllers directory to make them more
discoverable.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211006224659.21434-2-digetx@gmail.com
[krzysztof: Correct path in lpddr3.txt and samsung,exynos5422-dmc.yaml]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Dan Carpenter [Mon, 11 Oct 2021 12:36:38 +0000 (15:36 +0300)]
soc: imx: imx8m-blk-ctrl: off by one in imx8m_blk_ctrl_xlate()
The > comparison should be >= to prevent reading one element beyond the
end of the array. The onecell_data->domains[] array is allocated in
imx8m_blk_ctrl_probe() and it has "onecell_data->num_domains" elements.
Fixes:
5b340e7813d4 ("soc: imx: add i.MX8M blk-ctrl driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Arnd Bergmann [Wed, 13 Oct 2021 21:01:39 +0000 (23:01 +0200)]
Merge tag 'arm-soc/for-5.16/drivers' of https://github.com/Broadcom/stblinux into arm/drivers
This pull request contains Broadcom ARM/ARM64 SoC drivers changes for
5.16, please pull the following:
- Cai updates the bcm-pmb and bcm63xx-power drivers to use the
devm_platform_ioremap_resource() helper
- Florian updates the Bus Interface Unit code to tune the 72116 and
72113 chips according to their existing counterparts. The GISB driver is
updated to be built as a non-removable module
* tag 'arm-soc/for-5.16/drivers' of https://github.com/Broadcom/stblinux:
bus: brcmstb_gisb: Allow building as module
soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72116
soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72113
soc: bcm63xx-power: Make use of the helper function devm_platform_ioremap_resource()
soc: bcm: bcm-pmb: Make use of the helper function devm_platform_ioremap_resource()
Link: https://lore.kernel.org/r/20211013174016.831348-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 13 Oct 2021 20:34:41 +0000 (22:34 +0200)]
Merge tag 'qcom-drivers-for-5.16' of git://git./linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.16
This drops the use of power-domains for exposing the load_state from the
QMP driver to clients, to avoid issues related to system suspend.
SMP2P becomes wakeup capable, to allow dying remoteprocs to wake up
Linux from suspend to perform recovery.
It adds RPM power-domain support for SM6350 and MSM8953 and base RPM
support for MSM8953 and QCM2290.
It adds support for MSM8996, SDM630 and SDM660 in the SPM driver, which
will enable the introduction of proper voltage scaling of the CPU
subsystem.
Support for releasing secondary CPUs on MSM8226 is introduced.
The Asynchronous Packet Router (APR) driver is extended to support the
new Generic Packet Router (GPR) variant, which is used to communicate
with the firmware in the new AudioReach audio driver.
Lastly it transitions a number of drivers to safer string functions, as
well as switching things to use devm_platform_ioremap_resource().
* tag 'qcom-drivers-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (40 commits)
soc: qcom: apr: Add GPR support
soc: dt-bindings: qcom: add gpr bindings
soc: qcom: apr: make code more reuseable
soc: dt-bindings: qcom: apr: deprecate qcom,apr-domain property
soc: dt-bindings: qcom: apr: convert to yaml
dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
dt-bindings: msm/dp: Remove aoss-qmp header
soc: qcom: aoss: Drop power domain support
dt-bindings: soc: qcom: aoss: Drop the load state power-domain
soc: qcom: smp2p: Add wakeup capability to SMP2P IRQ
dt-bindings: power: rpmpd: Add SM6350 to rpmpd binding
dt-bindings: soc: qcom: aoss: Add SM6350 compatible
soc: qcom: llcc: Disable MMUHWT retention
soc: qcom: smd-rpm: Add QCM2290 compatible
dt-bindings: soc: qcom: smd-rpm: Add QCM2290 compatible
firmware: qcom_scm: Add compatible for MSM8953 SoC
dt-bindings: firmware: qcom-scm: Document msm8953 bindings
soc: qcom: pdr: Prefer strscpy over strcpy
soc: qcom: rpmh-rsc: Make use of the helper function devm_platform_ioremap_resource_byname()
soc: qcom: gsbi: Make use of the helper function devm_platform_ioremap_resource()
...
Link: https://lore.kernel.org/r/20211012173442.1017010-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Jernej Skrabec [Sun, 10 Oct 2021 07:18:12 +0000 (09:18 +0200)]
bus: sun50i-de2: Adjust printing error message
SRAM driver often returns -EPROBE_DEFER and thus this bus driver often
prints error message, even if it probes successfully later. This is
confusing for users and they often think that something is wrong.
Use dev_err_probe() helper for printing error message. It handles
-EPROBE_DEFER automatically.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211010071812.145178-1-jernej.skrabec@gmail.com
Sumit Garg [Tue, 12 Oct 2021 07:31:16 +0000 (13:01 +0530)]
tee: optee: Fix missing devices unregister during optee_remove
When OP-TEE driver is built as a module, OP-TEE client devices
registered on TEE bus during probe should be unregistered during
optee_remove. So implement optee_unregister_devices() accordingly.
Fixes:
c3fa24af9244 ("tee: optee: add TEE bus device enumeration support")
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Arnd Bergmann [Mon, 11 Oct 2021 14:55:32 +0000 (16:55 +0200)]
Merge tag 'omap-for-v5.16/ti-sysc-signed' of git://git./linux/kernel/git/tmlind/linux-omap into arm/drivers
Driver changes for ti-sysc for v5.16
Changes for ti-sysc driver for improved system suspend and resume
support as some drivers need to be reinitialized on resume. Also
a non-urgent resume warning fix, and dropping of legacy flags for
gpio and sham:
- Fix timekeeping suspended warning on resume. Probably no need to merge
this into fixes as it's gone unnoticed for a while.
- Check for context loss for reinit of a module
- Add add quirk handling to reinit on context loss, and also fix a
build warning it caused
- Add quirk handling to reset on reinit
- Use context loss quirk for gpmc and otg
- Handle otg force-idle quirk even if no driver is loaded
- Drop legacy flags for gpio and sham
* tag 'omap-for-v5.16/ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
bus: ti-sysc: Fix variable set but not used warning for reinit_modules
bus: ti-sysc: Drop legacy quirk flag for sham
bus: ti-sysc: Drop legacy quirk flag for gpio
bus: ti-sysc: Handle otg force idle quirk
bus: ti-sysc: Use context lost quirk for otg
bus: ti-sysc: Use context lost quirks for gpmc
bus: ti-sysc: Add quirk handling for reset on re-init
bus: ti-sysc: Add quirk handling for reinit on context lost
bus: ti-sysc: Check for lost context in sysc_reinit_module()
bus: ti-sysc: Fix timekeeping_suspended warning on resume
Link: https://lore.kernel.org/r/pull-1633950030-501948@atomide.com-2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 10:09:07 +0000 (12:09 +0200)]
Merge tag 'v5.15-next-soc' of git://git./linux/kernel/git/matthias.bgg/linux into arm/drivers
- mt8192: add mutex support
- mmsys:
add more components
add routing table for mt8192
add reset controller support
* tag 'v5.15-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
drm/mediatek: mtk_dsi: Reset the dsi0 hardware
soc: mediatek: mmsys: Add reset controller support
soc: mediatek: add mtk mutex support for MT8192
soc: mediatek: mmsys: Add mt8192 mmsys routing table
soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
Link: https://lore.kernel.org/r/b1d364d0-f2ae-488b-b3f7-c694049c20d3@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 10:07:56 +0000 (12:07 +0200)]
Merge tag 'memory-controller-drv-5.16' of git://git./linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.16
1. Renesas RPC: fix unaligned bus access and QSPI data transfers in
manual modes.
2. Renesas RPC: select RESET_CONTROLLER as it is necessary for
operation.
3. FSL IFC: fix error paths.
4. Broadcom: allow building as module.
* tag 'memory-controller-drv-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: fsl_ifc: fix leak of irq and nand_irq in fsl_ifc_ctrl_probe
memory: renesas-rpc-if: RENESAS_RPCIF should select RESET_CONTROLLER
memory: brcmstb_dpfe: Allow building Broadcom STB DPFE as module
memory: samsung: describe drivers in KConfig
memory: renesas-rpc-if: Avoid unaligned bus access for HyperFlash
memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
dt-bindings: rpc: renesas-rpc-if: Add support for the R8A779A0 RPC-IF
Link: https://lore.kernel.org/r/20211010175836.13302-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 10:06:45 +0000 (12:06 +0200)]
Merge tag 'memory-controller-drv-mtk-5.16' of git://git./linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.14 - Mediatek
Add MT8195 support to the Mediatek SMI memory controller driver. This
brings also several cleanups and minor enhancements before adding actual
new device support.
* tag 'memory-controller-drv-mtk-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
MAINTAINERS: Add entry for MediaTek SMI
memory: mtk-smi: mt8195: Add initial setting for smi-larb
memory: mtk-smi: mt8195: Add initial setting for smi-common
memory: mtk-smi: mt8195: Add smi support
memory: mtk-smi: Use devm_platform_ioremap_resource
memory: mtk-smi: Add clocks for smi-sub-common
memory: mtk-smi: Add device link for smi-sub-common
memory: mtk-smi: Add error handle for smi_probe
memory: mtk-smi: Adjust some code position
memory: mtk-smi: Rename smi_gen to smi_type
memory: mtk-smi: Use clk_bulk clock ops
dt-bindings: memory: mediatek: Add mt8195 smi sub common
dt-bindings: memory: mediatek: Add mt8195 smi binding
Link: https://lore.kernel.org/r/20211010175836.13302-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 10:05:29 +0000 (12:05 +0200)]
Merge tag 'memory-controller-drv-tegra-5.16' of git://git./linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.16 - Tegra SoC
1. Several minor improvements.
2. Handle errors in BPMP response of Tegra186 EMC.
* tag 'memory-controller-drv-tegra-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with
memory: tegra186-emc: Fix error return code in tegra186_emc_probe()
memory: tegra: Make use of the helper function devm_add_action_or_reset()
memory: tegra186-emc: Handle errors in BPMP response
memory: tegra: Remove interconnect state syncing hack
memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
memory: tegra30-emc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
memory: tegra: make the array list static const, makes object smaller
Link: https://lore.kernel.org/r/20211010175836.13302-3-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 09:24:04 +0000 (11:24 +0200)]
Merge tag 'tegra-for-5.16-cpuidle' of git://git./linux/kernel/git/tegra/linux into arm/drivers
cpuidle: tegra: Changes for v5.16-rc1
This pulls in the for-5.16/clk and for-5.16/soc branches and uses the
stubs added in them to enable compile testing of the cpuidle driver.
While at it, this also fixes a potential driver probe order race
condition between the PMC and the cpuidle driver.
* tag 'tegra-for-5.16-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
cpuidle: tegra: Check whether PMC is ready
cpuidle: tegra: Enable compile testing
clk: tegra: Add stubs needed for compile testing
Link: https://lore.kernel.org/r/20211008201132.1678814-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 09:11:00 +0000 (11:11 +0200)]
Merge tag 'tegra-for-5.16-soc' of git://git./linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.16-rc1
This set consists of stub additions to enable compile testing for more
drivers, exposes the PMC's USB regmap on all SoC generations, removes a
state synchronization workaround that is no longer needed and adds an
error reporting driver that can help troubleshoot crashes.
To top it all off, an error handling path in the powergating code is
fixed and the devm_platform_ioremap_resource() function is used to
remove some boilerplate code.
* tag 'tegra-for-5.16-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: Use devm_platform_ioremap_resource()
soc/tegra: Add Tegra186 ARI driver
soc/tegra: Fix an error handling path in tegra_powergate_power_up()
soc/tegra: pmc: Expose USB regmap to all SoCs
soc/tegra: pmc: Disable PMC state syncing
soc/tegra: pm: Make stubs usable for compile testing
soc/tegra: irq: Add stubs needed for compile testing
soc/tegra: fuse: Add stubs needed for compile testing
Link: https://lore.kernel.org/r/20211008201132.1678814-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 09:00:30 +0000 (11:00 +0200)]
Merge tag 'tegra-for-5.16-firmware' of git://git./linux/kernel/git/tegra/linux into arm/drivers
firmware: tegra: Changes for v5.16-rc1
This contains a fix for a stack usage problem that was causing build
failures on 32-bit ARM and a minor janitorial cleanup.
* tag 'tegra-for-5.16-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
firmware: tegra: bpmp: Use devm_platform_ioremap_resource()
firmware: tegra: Reduce stack usage
Link: https://lore.kernel.org/r/20211008201132.1678814-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 11 Oct 2021 08:31:10 +0000 (10:31 +0200)]
Merge tag 'amlogic-drivers-for-v5.16' of git://git./linux/kernel/git/amlogic/linux into arm/drivers
Amlogic Drivers updates for v5.16:
Minor cleanups, and the addition of the S905Y2 SoC ID
* tag 'amlogic-drivers-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
soc: amlogic: meson-clk-measure: Make use of the helper function devm_platform_ioremap_resource()
soc: amlogic: canvas: Make use of the helper function devm_platform_ioremap_resource()
soc: amlogic: meson-gx-socinfo: Add S905Y2 ID for Radxa Zero
Link: https://lore.kernel.org/r/f8e020d3-29f7-0745-3864-01975edd20f7@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Krzysztof Kozlowski [Sun, 10 Oct 2021 17:45:00 +0000 (19:45 +0200)]
Merge branch 'for-v5.16/renesas-rpc' into mem-ctrl-next
Cai Huoqing [Wed, 8 Sep 2021 07:17:24 +0000 (15:17 +0800)]
soc/tegra: pmc: Use devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of calling
platform_get_resource() and devm_ioremap_resource() separately.
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Thu, 17 Jun 2021 12:13:07 +0000 (15:13 +0300)]
soc/tegra: Add Tegra186 ARI driver
Add a driver to hook into panic notifiers and print machine check
status for debugging. Status information is retrieved via SMC. This
is supported by upstream ARM Trusted Firmware.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enric Balletbo i Serra [Thu, 30 Sep 2021 08:31:50 +0000 (10:31 +0200)]
drm/mediatek: mtk_dsi: Reset the dsi0 hardware
Reset dsi0 HW to default when power on. This prevents to have different
settingis between the bootloader and the kernel.
As not all Mediatek boards have the reset consumer configured in their
board description, also is not needed on all of them, the reset is optional,
so the change is compatible with all boards.
Cc: Jitao Shi <jitao.shi@mediatek.com>
Suggested-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20210930103105.v4.7.Idbb4727ddf00ba2fe796b630906baff10d994d89@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Enric Balletbo i Serra [Thu, 30 Sep 2021 08:31:49 +0000 (10:31 +0200)]
soc: mediatek: mmsys: Add reset controller support
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
Cc: Jitao Shi <jitao.shi@mediatek.com>
Suggested-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210930103105.v4.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Yongqiang Niu [Thu, 30 Sep 2021 15:52:21 +0000 (23:52 +0800)]
soc: mediatek: add mtk mutex support for MT8192
Add mtk mutex support for MT8192 SoC.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://lore.kernel.org/r/20210930155222.5861-5-yongqiang.niu@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Cai Huoqing [Wed, 8 Sep 2021 10:56:23 +0000 (18:56 +0800)]
firmware: tegra: bpmp: Use devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of calling
platform_get_resource() and devm_ioremap_resource() separately.
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Arnd Bergmann [Mon, 27 Sep 2021 12:41:40 +0000 (14:41 +0200)]
firmware: tegra: Reduce stack usage
Building the bpmp-debugfs driver for Arm results in a warning for stack usage:
drivers/firmware/tegra/bpmp-debugfs.c:321:16: error: stack frame size of 1224 bytes in function 'bpmp_debug_store' [-Werror,-Wframe-larger-than=]
static ssize_t bpmp_debug_store(struct file *file, const char __user *buf,
It should be possible to rearrange the code to not require two separate
buffers for the file name, but the easiest workaround is to use dynamic
allocation.
Fixes:
5e37b9c137ee ("firmware: tegra: Add support for in-band debug")
Link: https://lore.kernel.org/all/20201204193714.3134651-1-arnd@kernel.org/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[treding@nvidia.com: consistently return NULL on failure]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dongliang Mu [Sat, 25 Sep 2021 15:14:32 +0000 (23:14 +0800)]
memory: fsl_ifc: fix leak of irq and nand_irq in fsl_ifc_ctrl_probe
The error handling code of fsl_ifc_ctrl_probe is problematic. When
fsl_ifc_ctrl_init fails or request_irq of fsl_ifc_ctrl_dev->irq fails,
it forgets to free the irq and nand_irq. Meanwhile, if request_irq of
fsl_ifc_ctrl_dev->nand_irq fails, it will still free nand_irq even if
the request_irq is not successful.
Fix this by refactoring the error handling code.
Fixes:
d2ae2e20fbdd ("driver/memory:Move Freescale IFC driver to a common driver")
Signed-off-by: Dongliang Mu <mudongliangabcd@gmail.com>
Link: https://lore.kernel.org/r/20210925151434.8170-1-mudongliangabcd@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Kai Song [Tue, 5 Oct 2021 04:35:14 +0000 (12:35 +0800)]
memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with
fix debugfs_simple_attr.cocci warning:
drivers/memory/tegra/tegra210-emc-core.c:1665:0-23: WARNING:tegra210_emc_debug_min_rate_fops
should be defined with DEFINE_DEBUGFS_ATTRIBUTE
Commit
6fc5f1adf5a1 ("memory: tegra210-emc: replace
DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE") fixed the same
warning, but didn't fix all matches in this file at once.
Signed-off-by: Kai Song <songkai01@inspur.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20211005043514.9650-1-songkai01@inspur.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Geert Uytterhoeven [Tue, 5 Oct 2021 15:29:22 +0000 (17:29 +0200)]
memory: renesas-rpc-if: RENESAS_RPCIF should select RESET_CONTROLLER
The Renesas RPC-IF driver calls devm_reset_control_get_exclusive(),
which returns -ENOTSUPP if CONFIG_RESET_CONTROLLER is not enabled.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/e443aa66d146da5646b7ebece8876545b8621063.1633447756.git.geert+renesas@glider.be
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Yang Yingliang [Tue, 28 Sep 2021 02:15:45 +0000 (10:15 +0800)]
memory: tegra186-emc: Fix error return code in tegra186_emc_probe()
Return the error code when command fails.
Fixes:
13324edbe926 ("memory: tegra186-emc: Handle errors in BPMP response")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://lore.kernel.org/r/20210928021545.3774677-1-yangyingliang@huawei.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Christophe JAILLET [Sun, 27 Jun 2021 15:54:31 +0000 (17:54 +0200)]
soc/tegra: Fix an error handling path in tegra_powergate_power_up()
If an error occurs after a successful tegra_powergate_enable_clocks()
call, it must be undone by a tegra_powergate_disable_clocks() call, as
already done in the below and above error handling paths of this function.
Update the 'goto' to branch at the correct place of the error handling
path.
Fixes:
a38045121bf4 ("soc/tegra: pmc: Add generic PM domain support")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lucas Stach [Sat, 2 Oct 2021 00:59:49 +0000 (02:59 +0200)]
soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
This adds the description for the i.MX8MM disp blk-ctrl.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 2 Oct 2021 00:59:46 +0000 (02:59 +0200)]
soc: imx: add i.MX8M blk-ctrl driver
This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.
Software needs to do different things to make the bus handshake happen
after the GPC *MIX domain is powered up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.
The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 2 Oct 2021 00:59:43 +0000 (02:59 +0200)]
soc: imx: gpcv2: support system suspend/resume
Our usage of runtime PM to control the hierarchy of power domains is
slightly unusual and means that powering up a domain may fail in early
system resume, as runtime PM is still disallowed at this stage.
However the system suspend/resume path takes care of powering down/up
the power domains in the order defined by the device parent/child and
power-domain provider/consumer hierarachy. So we can just runtime
resume all our power-domain devices to allow the power-up to work
properly in the resume path. System suspend will still disable all
domains as intended.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 2 Oct 2021 00:59:42 +0000 (02:59 +0200)]
soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 2 Oct 2021 00:59:41 +0000 (02:59 +0200)]
soc: imx: gpcv2: add domain option to keep domain clocks enabled
Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 2 Oct 2021 00:59:40 +0000 (02:59 +0200)]
soc: imx: gpcv2: add lockdep annotation
Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.
Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tony Lindgren [Wed, 6 Oct 2021 05:38:09 +0000 (08:38 +0300)]
bus: ti-sysc: Fix variable set but not used warning for reinit_modules
Fix drivers/bus/ti-sysc.c:2494:13: error: variable 'error' set but not
used introduced by commit
9d881361206e ("bus: ti-sysc: Add quirk handling
for reinit on context lost").
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Dmitry Osipenko [Sun, 12 Sep 2021 20:29:07 +0000 (23:29 +0300)]
cpuidle: tegra: Check whether PMC is ready
Check whether PMC is ready before proceeding with the cpuidle registration.
This fixes racing with the PMC driver probe order, which results in a
disabled deepest CC6 idling state if cpuidle driver is probed before the
PMC.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 12 Sep 2021 20:29:06 +0000 (23:29 +0300)]
cpuidle: tegra: Enable compile testing
Enable compile testing of tegra-cpuidle driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 5 Oct 2021 17:11:21 +0000 (19:11 +0200)]
Merge branch 'for-5.16/soc' into for-5.16/cpuidle
Thierry Reding [Tue, 5 Oct 2021 17:10:57 +0000 (19:10 +0200)]
Merge branch 'for-5.16/clk' into for-5.16/cpuidle
Thierry Reding [Mon, 4 Oct 2021 20:06:41 +0000 (22:06 +0200)]
clk: tegra: Add stubs needed for compile testing
These stubs are needed to allow the tegra-cpuidle driver to be
compile-tested.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Arnd Bergmann [Tue, 5 Oct 2021 14:33:27 +0000 (16:33 +0200)]
Merge tag 'renesas-drivers-for-v5.16-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.16
- Initial support for the new R-Car H3e, M3e, M3Ne(-2G), D3e, E3e, and
H3Ne SoCs.
* tag 'renesas-drivers-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Identify more R-Car Gen3e SoCs
Link: https://lore.kernel.org/r/cover.1633081156.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Tue, 5 Oct 2021 02:10:42 +0000 (11:10 +0900)]
reset: uniphier: Add NX1 reset support
Add basic reset data for UniPhier NX1 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1633399842-1402-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Kunihiko Hayashi [Tue, 5 Oct 2021 02:10:41 +0000 (11:10 +0900)]
dt-bindings: reset: uniphier: Add NX1 reset control binding
Update reset controller binding document for UniPhier NX1 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1633399842-1402-3-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Kunihiko Hayashi [Tue, 5 Oct 2021 02:10:40 +0000 (11:10 +0900)]
reset: uniphier: Add audio system and video input reset control for PXs3
Add reset lines for audio subsystem (AIO) and video input subsystem (EXIV)
on UniPhier PXs3 SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1633399842-1402-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Florian Fainelli [Fri, 24 Sep 2021 03:08:40 +0000 (20:08 -0700)]
reset: Allow building Broadcom STB RESCAL as module
The driver can be built as a module and uses device managed resources.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210924030840.9650-1-f.fainelli@gmail.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Lucas Stach [Sat, 2 Oct 2021 00:59:37 +0000 (02:59 +0200)]
Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
This reverts commit
a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.
Cc: <stable@vger.kernel.org> # 5.14
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lucas Stach [Sat, 2 Oct 2021 12:48:52 +0000 (14:48 +0200)]
soc: imx: gpcv2: allow to disable individual power domains
Some board designs don't supply power to all of the power domains,
as they are not used anyways. In that case we must make sure to
not touch those power domains at all, as trying to power up a
domain that has no power supplied to it will obviously end in a
system crash. Allow to disable those domains via the standard DT
status property.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-By: Tim Harvey <tharvey@gateworks.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Ezequiel Garcia [Fri, 24 Sep 2021 14:01:46 +0000 (11:01 -0300)]
imx: soc: Select REGMAP_MMIO
The imx-gpcv2 driver needs Regmap MMIO. Select it, and fix:
drivers/soc/imx/gpcv2.c:420:34: error: array type has incomplete element type ‘struct regmap_range’
420 | static const struct regmap_range imx7_yes_ranges[] = {
| ^~~~~~~~~~~~~~~
drivers/soc/imx/gpcv2.c:421:17: error: implicit declaration of function ‘regmap_reg_range’; did you mean ‘remap_pfn_range’? [-Werror=implicit-function-declaration]
421 | regmap_reg_range(GPC_LPCR_A_CORE_BSC,
| ^~~~~~~~~~~~~~~~
| remap_pfn_range
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Dmitry Osipenko [Sun, 12 Sep 2021 18:17:14 +0000 (21:17 +0300)]
soc/tegra: pmc: Expose USB regmap to all SoCs
All Tegra SoCs prior to Tegra186 have USB power controls within the Power
Management controller. These controls need to be configured by USB driver.
Expose the regmap to these SoCs.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 26 Sep 2021 22:40:26 +0000 (01:40 +0300)]
soc/tegra: pmc: Disable PMC state syncing
Disable PMC state syncing in order to ensure that we won't break older
kernels once device-trees will be updated with the addition of the power
domains. This also allows to apply device-tree PM patches independently
from the driver patches.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 12 Sep 2021 20:29:04 +0000 (23:29 +0300)]
soc/tegra: pm: Make stubs usable for compile testing
The PM stubs need to depend on ARCH_TEGRA in order to be usable for
compile-testing of tegra-cpuidle driver. Add the dependency.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 12 Sep 2021 20:29:03 +0000 (23:29 +0300)]
soc/tegra: irq: Add stubs needed for compile testing
Add stubs needed for compile-testing of tegra-cpuidle driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 12 Sep 2021 20:29:02 +0000 (23:29 +0300)]
soc/tegra: fuse: Add stubs needed for compile testing
Add stubs needed for compile-testing of tegra-cpuidle driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Marek Vasut [Tue, 7 Sep 2021 02:38:30 +0000 (04:38 +0200)]
soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.
Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Tue, 7 Sep 2021 02:38:29 +0000 (04:38 +0200)]
soc: imx: gpcv2: Turn domain->pgc into bitfield
There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.
Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.
This is a preparatory patch, no functional change.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Florian Fainelli [Fri, 24 Sep 2021 03:14:59 +0000 (20:14 -0700)]
memory: brcmstb_dpfe: Allow building Broadcom STB DPFE as module
Allow building the Broadcom STB DPFE driver as a module, it is already a
platform driver proper with all of the resource releasing device
managed.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Markus Mayer <mmayer@broadcom.com>
Link: https://lore.kernel.org/r/20210924031459.8911-1-f.fainelli@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Krzysztof Kozlowski [Fri, 24 Sep 2021 13:34:06 +0000 (15:34 +0200)]
memory: samsung: describe drivers in KConfig
Rephrase the Kconfig option and make it clear it applies only to Samsung
SoC.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210924133406.112174-1-krzysztof.kozlowski@canonical.com
Andrew Gabbasov [Wed, 22 Sep 2021 18:48:30 +0000 (13:48 -0500)]
memory: renesas-rpc-if: Avoid unaligned bus access for HyperFlash
HyperFlash devices in Renesas SoCs use 2-bytes addressing, according
to HW manual paragraph 62.3.3 (which officially describes Serial Flash
access, but seems to be applicable to HyperFlash too). And 1-byte bus
read operations to 2-bytes unaligned addresses in external address space
read mode work incorrectly (returns the other byte from the same word).
Function memcpy_fromio(), used by the driver to read data from the bus,
in ARM64 architecture (to which Renesas cores belong) uses 8-bytes
bus accesses for appropriate aligned addresses, and 1-bytes accesses
for other addresses. This results in incorrect data read from HyperFlash
in unaligned cases.
This issue can be reproduced using something like the following commands
(where mtd1 is a parition on Hyperflash storage, defined properly
in a device tree):
[Correct fragment, read from Hyperflash]
root@rcar-gen3:~# dd if=/dev/mtd1 of=/tmp/zz bs=32 count=1
root@rcar-gen3:~# hexdump -C /tmp/zz
00000000 f4 03 00 aa f5 03 01 aa f6 03 02 aa f7 03 03 aa |................|
00000010 00 00 80 d2 40 20 18 d5 00 06 81 d2 a0 18 a6 f2 |....@ ..........|
00000020
[Incorrect read of the same fragment: see the difference at offsets 8-11]
root@rcar-gen3:~# dd if=/dev/mtd1 of=/tmp/zz bs=12 count=1
root@rcar-gen3:~# hexdump -C /tmp/zz
00000000 f4 03 00 aa f5 03 01 aa 03 03 aa aa |............|
0000000c
Fix this issue by creating a local replacement of the copying function,
that performs only properly aligned bus accesses, and is used for reading
from HyperFlash.
Fixes:
ca7d8b980b67f ("memory: add Renesas RPC-IF driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Link: https://lore.kernel.org/r/20210922184830.29147-1-andrew_gabbasov@mentor.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Wolfram Sang [Wed, 22 Sep 2021 09:10:06 +0000 (11:10 +0200)]
memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
This patch fixes 2 problems:
[1] The output warning logs and data loss when performing
mount/umount then remount the device with jffs2 format.
[2] The access width of SMWDR[0:1]/SMRDR[0:1] register is wrong.
This is the sample warning logs when performing mount/umount then
remount the device with jffs2 format:
jffs2: jffs2_scan_inode_node(): CRC failed on node at 0x031c51d4:
Read 0x00034e00, calculated 0xadb272a7
The reason for issue [1] is that the writing data seems to
get messed up.
Data is only completed when the number of bytes is divisible by 4.
If you only have 3 bytes of data left to write, 1 garbage byte
is inserted after the end of the write stream.
If you only have 2 bytes of data left to write, 2 bytes of '00'
are added into the write stream.
If you only have 1 byte of data left to write, 2 bytes of '00'
are added into the write stream. 1 garbage byte is inserted after
the end of the write stream.
To solve problem [1], data must be written continuously in serial
and the write stream ends when data is out.
Following HW manual 62.2.15, access to SMWDR0 register should be
in the same size as the transfer size specified in the SPIDE[3:0]
bits in the manual mode enable setting register (SMENR).
Be sure to access from address 0.
So, in 16-bit transfer (SPIDE[3:0]=b'1100), SMWDR0 should be
accessed by 16-bit width.
Similar to SMWDR1, SMDDR0/1 registers.
In current code, SMWDR0 register is accessed by regmap_write()
that only set up to do 32-bit width.
To solve problem [2], data must be written 16-bit or 8-bit when
transferring 1-byte or 2-byte.
Fixes:
ca7d8b980b67 ("memory: add Renesas RPC-IF driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Duc Nguyen <duc.nguyen.ub@renesas.com>
[wsa: refactored to use regmap only via reg_read/reg_write]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922091007.5516-1-wsa+renesas@sang-engineering.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Bjorn Andersson [Tue, 28 Sep 2021 03:13:45 +0000 (22:13 -0500)]
Merge tag '
20210927135559.738-6-srinivas.kandagatla@linaro.org' into drivers-for-5.16
v5.15-rc1 +
20210927135559.738-[23456]-srinivas.kandagatla@linaro.org
This immutable branch is based on v5.15-rc1 and contains the following
patches extending the existig APR driver to also implement GPR:
20210927135559.738-2-srinivas.kandagatla@linaro.org
20210927135559.738-3-srinivas.kandagatla@linaro.org
20210927135559.738-4-srinivas.kandagatla@linaro.org
20210927135559.738-5-srinivas.kandagatla@linaro.org
20210927135559.738-6-srinivas.kandagatla@linaro.org
Srinivas Kandagatla [Mon, 27 Sep 2021 13:55:42 +0000 (14:55 +0100)]
soc: qcom: apr: Add GPR support
Qualcomm Generic Packet router aka GPR is the IPC mechanism found
in AudioReach next generation signal processing framework to perform
command and response messages between various processors.
GPR has concepts of static and dynamic port, all static services like
APM (Audio Processing Manager), PRM (Proxy resource manager) have
fixed port numbers where as dynamic services like graphs have dynamic
port numbers which are allocated at runtime. All GPR packet messages
will have source and destination domain and port along with opcode
and payload.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-6-srinivas.kandagatla@linaro.org
Srinivas Kandagatla [Mon, 27 Sep 2021 13:55:41 +0000 (14:55 +0100)]
soc: dt-bindings: qcom: add gpr bindings
Qualcomm Generic Packet router aka GPR is the IPC mechanism found
in AudioReach next generation signal processing framework to perform
command and response messages between various processors.
GPR has concepts of static and dynamic port, all static services like
APM (Audio Processing Manager), PRM (Proxy resource manager) have
fixed port numbers where as dynamic services like graphs have dynamic
port numbers which are allocated at runtime. All GPR packet messages
will have source and destination domain and port along with opcode
and payload.
This support is added using existing APR driver to reuse most of
the code.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-5-srinivas.kandagatla@linaro.org
Srinivas Kandagatla [Mon, 27 Sep 2021 13:55:40 +0000 (14:55 +0100)]
soc: qcom: apr: make code more reuseable
APR and other packet routers like GPR are pretty much same and
interact with other drivers in similar way.
Ex: GPR ports can be considered as APR services, only difference
is they are allocated dynamically.
Other difference is packet layout, which should not matter
with the apis abstracted. Apart from this the rest of the
functionality is pretty much identical across APR and GPR.
Make the apr code more reusable by abstracting it service level,
rather than device level so that we do not need to write
new drivers for other new packet routers like GPR.
This patch is in preparation to add GPR support to this driver.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-4-srinivas.kandagatla@linaro.org
Srinivas Kandagatla [Mon, 27 Sep 2021 13:55:39 +0000 (14:55 +0100)]
soc: dt-bindings: qcom: apr: deprecate qcom,apr-domain property
replace usage of qcom,apr-domain property with qcom,domain property so
that bindings and driver can be reused.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-3-srinivas.kandagatla@linaro.org
Srinivas Kandagatla [Mon, 27 Sep 2021 13:55:38 +0000 (14:55 +0100)]
soc: dt-bindings: qcom: apr: convert to yaml
Convert APR bindings to yaml format so that we could add new bindings support.
All the dsp services bindings are now part of apr bindings instead
of adding them to audio bindings.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-2-srinivas.kandagatla@linaro.org
Florian Fainelli [Fri, 24 Sep 2021 19:10:34 +0000 (12:10 -0700)]
bus: brcmstb_gisb: Allow building as module
Allow building the Broadcom STB GISB arbiter driver as a module, however
similar to interrupt controller drivers, don't allow its unbind/removal
since it is not quite prepared for that and we want it to catch bus
errors all the time.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Sibi Sankar [Thu, 16 Sep 2021 13:59:30 +0000 (19:29 +0530)]
dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
Delete unused power-domain definitions exposed by AOSS QMP.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-14-git-send-email-sibis@codeaurora.org
Sibi Sankar [Thu, 16 Sep 2021 13:59:29 +0000 (19:29 +0530)]
dt-bindings: msm/dp: Remove aoss-qmp header
Remove the unused aoss-qmp header from the list of includes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-13-git-send-email-sibis@codeaurora.org
Sibi Sankar [Thu, 16 Sep 2021 13:59:28 +0000 (19:29 +0530)]
soc: qcom: aoss: Drop power domain support
Strip out the load state power-domain support from the driver since the
low power mode signalling for the co-processors is now accessible through
the direct qmp message send interface.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-12-git-send-email-sibis@codeaurora.org
Sibi Sankar [Thu, 16 Sep 2021 13:59:18 +0000 (19:29 +0530)]
dt-bindings: soc: qcom: aoss: Drop the load state power-domain
The power-domains exposed by AOSS QMP node are used to notify the Always
on Subsystem (AOSS) that a particular co-processor is up/down. These
co-processors enter low-power modes independent to that of the application
processor and their states are expected to remain unaltered across system
suspend/resume cycles. To achieve this behavior let's drop the load
power-domain and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-2-git-send-email-sibis@codeaurora.org
Linus Torvalds [Sun, 26 Sep 2021 21:08:19 +0000 (14:08 -0700)]
Linux 5.15-rc3