freedreno/pps: improve interaction with turnip

turnip uses priority 0.  pps should too (actually, it makes sense to do
so regardless of what turnip does).

turnip is not expected to starve pps, but it does with drm-next for
5.20.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18093>

pan/bi: Test int8/16 -> float32 opts

These are easy, since round modes don't matter.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17857>

pan/bi: Fuse [US][8|16]_TO_F32 ops

This combines nicely with the previous isel change. Now GLSL like

   float(int_x >> 24)

will generate a single machine instruction

   S8_TO_F32 int_x.b3

Noticed when debugging

   KHR-GLES31.core.shader_bitfield_operation.unpackSnorm4x8.0

...but naturally no real workloads care. Helped shaders are from Android games
that appear to have run through a translator, naturally.

total instructions in shared programs: 2674831 -> 2674783 (<.01%)
instructions in affected programs: 11493 -> 11445 (-0.42%)
helped: 31
HURT: 0
helped stats (abs) min: 1.0 max: 3.0 x̄: 1.55 x̃: 1
helped stats (rel) min: 0.16% max: 2.90% x̄: 0.51% x̃: 0.41%
95% mean confidence interval for instructions value: -1.87 -1.22
95% mean confidence interval for instructions %-change: -0.69% -0.33%
Instructions are helped.

total cvt in shared programs: 14128.84 -> 14128.09 (<.01%)
cvt in affected programs: 78.17 -> 77.42 (-0.96%)
helped: 31
HURT: 0
helped stats (abs) min: 0.015625 max: 0.046875 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.36% max: 4.26% x̄: 1.28% x̃: 1.20%
95% mean confidence interval for cvt value: -0.03 -0.02
95% mean confidence interval for cvt %-change: -1.62% -0.94%
Cvt are helped.

total quadwords in shared programs: 1449920 -> 1449840 (<.01%)
quadwords in affected programs: 2184 -> 2104 (-3.66%)
helped: 10
HURT: 0
helped stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
helped stats (rel) min: 2.44% max: 5.88% x̄: 4.11% x̃: 4.76%
95% mean confidence interval for quadwords value: -8.00 -8.00
95% mean confidence interval for quadwords %-change: -5.11% -3.12%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17857>

pan/bi: Implement some extracts and inserts

Rather than lowering in NIR. Importantly for Valhall, this allows
nir_opt_algebraic to optimize various bitwise ops into extracts and inserts,
taking pressure off the low-throughout SFU pipe and moving it onto the
high-throughput CVT pipe. This will mitigate a cycle count regression from
switching to the precise idiv lowering.

This also generates more integer widening conversions which we can fold into
32-bit instructions later, to allow optimizing GLSL like "(a & 0xFFFF) + b"

Valhall:

total instructions in shared programs: 2674836 -> 2674840 (<.01%)
instructions in affected programs: 6473 -> 6477 (0.06%)
helped: 14
HURT: 6
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.16% max: 1.37% x̄: 0.41% x̃: 0.49%
HURT stats (abs)   min: 3.0 max: 3.0 x̄: 3.00 x̃: 3
HURT stats (rel)   min: 1.19% max: 1.62% x̄: 1.35% x̃: 1.24%
95% mean confidence interval for instructions value: -0.68 1.08
95% mean confidence interval for instructions %-change: -0.30% 0.53%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 140627.42 -> 140627.36 (<.01%)
cycles in affected programs: 2.31 -> 2.25 (-2.70%)
helped: 1
HURT: 0

total cvt in shared programs: 14127.25 -> 14128.91 (0.01%)
cvt in affected programs: 153.50 -> 155.16 (1.08%)
helped: 0
HURT: 41
HURT stats (abs)   min: 0.015625 max: 0.09375 x̄: 0.04 x̃: 0
HURT stats (rel)   min: 0.27% max: 4.44% x̄: 1.61% x̃: 1.22%
95% mean confidence interval for cvt value: 0.03 0.05
95% mean confidence interval for cvt %-change: 1.29% 1.93%
Cvt are HURT.

total sfu in shared programs: 7555.69 -> 7549.31 (-0.08%)
sfu in affected programs: 107.31 -> 100.94 (-5.94%)
helped: 48
HURT: 0
helped stats (abs) min: 0.0625 max: 0.375 x̄: 0.13 x̃: 0
helped stats (rel) min: 1.34% max: 50.00% x̄: 13.57% x̃: 7.14%
95% mean confidence interval for sfu value: -0.15 -0.11
95% mean confidence interval for sfu %-change: -17.07% -10.06%
Sfu are helped.

total quadwords in shared programs: 1449912 -> 1449928 (<.01%)
quadwords in affected programs: 256 -> 272 (6.25%)
helped: 0
HURT: 2

Bifrost:

total instructions in shared programs: 2415370 -> 2415380 (<.01%)
instructions in affected programs: 1642 -> 1652 (0.61%)
helped: 2
HURT: 6
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.40% max: 0.40% x̄: 0.40% x̃: 0.40%
HURT stats (abs)   min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.95% max: 1.27% x̄: 1.07% x̃: 1.00%
95% mean confidence interval for instructions value: 0.09 2.41
95% mean confidence interval for instructions %-change: 0.13% 1.29%
Instructions are HURT.

total tuples in shared programs: 1928495 -> 1928476 (<.01%)
tuples in affected programs: 3329 -> 3310 (-0.57%)
helped: 9
HURT: 2
helped stats (abs) min: 1.0 max: 6.0 x̄: 2.56 x̃: 2
helped stats (rel) min: 0.25% max: 2.33% x̄: 1.00% x̃: 0.75%
HURT stats (abs)   min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.48% max: 0.48% x̄: 0.48% x̃: 0.48%
95% mean confidence interval for tuples value: -3.46 0.00
95% mean confidence interval for tuples %-change: -1.35% -0.10%
Inconclusive result (value mean confidence interval includes 0).

total clauses in shared programs: 354978 -> 354983 (<.01%)
clauses in affected programs: 398 -> 403 (1.26%)
helped: 3
HURT: 8
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 2.33% max: 3.85% x̄: 2.83% x̃: 2.33%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 2.27% max: 3.70% x̄: 2.88% x̃: 2.78%
95% mean confidence interval for clauses value: -0.17 1.08
95% mean confidence interval for clauses %-change: -0.51% 3.16%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 166575.69 -> 166575.65 (<.01%)
cycles in affected programs: 6.88 -> 6.83 (-0.61%)
helped: 1
HURT: 0

total arith in shared programs: 73688.79 -> 73688 (<.01%)
arith in affected programs: 127.29 -> 126.50 (-0.62%)
helped: 9
HURT: 2
helped stats (abs) min: 0.04166700000000034 max: 0.25 x̄: 0.11 x̃: 0
helped stats (rel) min: 0.26% max: 2.45% x̄: 1.07% x̃: 0.80%
HURT stats (abs)   min: 0.08333299999999966 max: 0.08333299999999966 x̄: 0.08 x̃: 0
HURT stats (rel)   min: 0.55% max: 0.55% x̄: 0.55% x̃: 0.55%
95% mean confidence interval for arith value: -0.14 0.00
95% mean confidence interval for arith %-change: -1.44% -0.11%
Inconclusive result (value mean confidence interval includes 0).

total quadwords in shared programs: 1674514 -> 1674480 (<.01%)
quadwords in affected programs: 9086 -> 9052 (-0.37%)
helped: 23
HURT: 2
helped stats (abs) min: 1.0 max: 6.0 x̄: 1.65 x̃: 1
helped stats (rel) min: 0.15% max: 2.79% x̄: 0.63% x̃: 0.33%
HURT stats (abs)   min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.53% max: 0.53% x̄: 0.53% x̃: 0.53%
95% mean confidence interval for quadwords value: -2.08 -0.64
95% mean confidence interval for quadwords %-change: -0.86% -0.21%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17857>

gallivm: always do per-pixel LOD for cube maps

In the past we were doing per-quad lod for cube maps (when no_quad_lod
wasn't set), however commit d413fd02190d ("gallivm: Always take the
per-pixel LOD path for cubemaps.") unconditionally enabled calculating
per-pixel derivatives.
However, the actual lod calculation was still only done per quad, which
probably doesn't make much sense, so unconditionally enable taking the
per-pixel lod path for cubemaps (for op_is_lodq we always force
no_quad_lod to false in any case so there's no difference there neither).

v2: adjust ci results accordingly

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18126>

lavapipe: initialize index_bias to zero for non-indexed draws

This is mostly just cosmetic, since the index bias will be ignored.
(The multi draw function already initializes this to 0 too.)

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18126>

anv: Do not duplicate intel_device_info memory in each logical device

Each logical device can point to its physical device intel_device_info
saving at least one intel_device_info.

This also allow us to set 'const' to avoid values in intel_device_info
being changed by mistake.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17897>

vk/render_pass: don't deref null resolve attachments

Fixes: d2990b65997 ("vulkan: hook up VK_EXT_multisampled_render_to_single_sampled")

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18134>

panfrost: Don't segfault on unknown models

If we don't recognize the model, dev->model will be NULL. In that case, we can't
dereference dev->model to get the tilebuffer size. If we do, we'll segfault,
instead of gracefully refusing to probe and loading the swrast instead.

Fixes: 96d65b47c71 ("panfrost: Use implementation-specific tile size")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18115>

nv30: Fix non-scissored clears after a scissor has been set

Additionally add support for PIPE_CAP_CLEAR_SCISSORED since we are already
touching the scissor state.

Fixes various gnome-shell rendering artifacts.

v2: Remove NEW_SCISSOR as clear now updates scissor registers explicitly
v3: Reset scissor_off state since its not off now after clear

Cc: mesa-stable
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18137>

zink: remove needless check

textureCompressionBC is just a short-hand to know is *all* BPTC formats
are supported. We're already checking per format, so we don't need this
coarser check.

Besides, it's also kinda wrong; textureCompressionBC also requires all
BC formats, not just BPTC. In other words, all DXT formats and RGTC
formats were missing from the check.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17986>

freedreno: Disable LRZ write when alpha-to-coverage is enabled

Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.

Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18102>

radv: Inline bvh build headers

Thos are only included once, so just move the code into the
corresponding .comp files.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17963>

zink: Fix incorrect emission of SPIR-V shift ops

SPIR-V shift ops unlike NIR have undefined behavior if shift count
larger than or equalt to bitwidth.
This means that true translation of NIR ishl/ishr/ushr to SPIR-V requires
masking like that done in gallivm.
This was seen in the case of soft fp64 in cts case
KHR-GL46.gpu_shader_fp64.builtin.ceil_double.

Cc: mesa-stable
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18074>

r600: Fix SCRATCH OP de-assembly

1d871aa6268159cdc63ef846599456d9ba567206
   r600g: Implement spilling of temp arrays (v2)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600: Don't use SB with R600 style scratch reads

SB fails when handling indirect READ_SCRATCH commands.

Fixes: 1d871aa6268159cdc63ef846599456d9ba567206
   r600g: Implement spilling of temp arrays (v2)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600/sfn: Handle R600 scratch read

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
     r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600: Force NOPs when loading AR on R600 class hardware

Loading indirectly from a register that was just written to
doesn't work on R600 class hardware, so add a NOP group with
the address register load being emitted in the t-slot. to make
sure that the register write was finished.

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
     r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600/sfn: Initialize out buffer when printing op

79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

Closes: #7021

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600/sfn: Fix color outputs when color0 writes all

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
       r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600/sfn: Sort FS inputs to make interpolated values come first

On R600 and R700 class hardware the input declaration order maps
directly to the register the hardware writes the inputs to, so
make all interpolated inputs come first, and only then emit the
system values like POS or FACE.

Related: #7035

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
     r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600/sfn: Add GS thread fix just like the TGSI code path

The old code does the same for R600.

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
     r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

r600/sfn: Schedule shift instruction on R600 in t-slot

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
    r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>

crocus: sync performance monitor code with iris.

This provides the same info as iris does now, and exposes
INTEL_performance_query

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18099>

glsl: dont lower precision for textureGatherOffsets

textureGatherOffsets always takes a highp array of constants. As
per the discussion in [1] trying to lower the precision results in segfault
later on in the compiler as textureGatherOffsets will end up being passed
a temp when its expecting a constant as required by the spec.

[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547#note_1393704

Fixes: b83f4b9fa23d ("glsl: Add an IR lowering pass to convert mediump operations to 16-bit")

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18101>

v3dv: Avoid swapchain_info handling on Android

Allows following tests to pass.
dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info
dEQP-VK.wsi.android.swapchain.simulate_oom#image_swapchain_create_info

Venus code was used as example.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>

v3dv: Limit API version to v1.0 for Android

Android CDD has additional requirements that must be met in order to
enable 1.1+:

 - samplerYcbcrConversion
 - VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
 - VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
 - VK_ANDROID_external_memory_android_hardware_buffer >= v2

Requirements are checked by:
android.graphics.cts.VulkanFeaturesTest#testVulkan1_1Requirements CTS

Fixes: 2686c5419d67 ("v3dv: add Android support")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>

v3dv: Enable sync_fd importing/exporting on Android

vk_common_AcquireImageANDROID and vk_common_QueueSignalReleaseImageANDROID
expect sync_fd import/export to be enabled, otherwise they crashes
while trying to ImportSemaphoreFdKHR() / GetSemaphoreFdKHR().

Features was disabled on Linux to skip sync_fd CTS tests, which is using
late vkEvent signalling which causes deadlock / dEQP timeout on v3dv.

One of the options was implementing blocking v3dv-specific
AcquireImageANDROID / QueueSignalReleaseImageANDROID to avoid importing
/ exporting sync_fd, but since these features are also required by CDD
for Vulkan 1.1 and above, it was decided to enable the extensions for
Android in exchange of a few failed dEQP tests (which should not cause
any issues in non-dEQP scenarious).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6977
Fixes: 316728a55bc8 ("v3dv: Switch to the common submit framework")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>

ci: bumping all tags to make sure we don't have hidden fails

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18108>

ci: update fails list

one might want to investigate this, but for now let's move on and unblock
MRs.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18108>

ci: remove broken device-select-layer from build

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18108>

intel/compiler: fix mesh urb write regression

Right now even the simplest mesh test (func.mesh.basic.mesh from crucible) fails like this:
ASSERT: Scalar MESH validation failed!
load_payload(16) vgrf11+0.0:F, vgrf8:D
../../src/intel/compiler/brw_fs_validate.cpp:61: inst->dst.offset / REG_SIZE + regs_written(inst) <= alloc.sizes[inst->dst.nr]
Because we try to load 8 regs with LOAD_PAYLOAD in SIMD16 mode.

Fixes: 349a040f684 ("intel/fs: Make logical URB write instructions more like other logical instructions")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18075>

Revert "radeon: add EFC support to only VCN2.0 devices"

This reverts commit 23e5b910c57158030ba246530c57ab13a51245f3.

Reason for revert:
It's causing the regression for H264 transcoding. We will Enable EFC
once we verify all corner cases and as of now disabling

Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17869>

iris: Fix PIPE_CAP_UMA

If we have VRAM we're not exactly a unified memory architecture, are we?

Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18123>

intel/compiler: Drop variable group size lowering

This backend lowering code has been dead since the removal of i965 -
nothing in the current source tree ever sets the flag.

This is handled by iris_setup_uniforms() and crocus_setup_uniforms().
Variable group size does not appear to be a feature in anv.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18055>

llvmpipe: Align persistent mappings to page size

KVM requires memory mapping to be aligned to page size, otherwise it
refuses to do the mapping. In particular this causes KVM mapping errors
when llvmpipe is used by virtio-gpu on host and guest tries to map buffer
that has a persistent mapping, i.e. it tries to map the llvmpipe's host
blob/buffer. Mesa virgl driver uses host blobs only for the buffers with
persistent mapping, hence let's align buffer allocations to the page size
when the persistence flag is set to fix the KVM fault.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18053>

zink: try to reuse swapchain modifier for dmabuf export

the non-negotiated path assumes that drivers know what implicit modifiers they're
using, but zink doesn't know what it's doing, so instead try to copy the
swapchain's modifier and reuse that since in theory it should work

Fixes: 247b8f2924b ("zink: add all format modifiers when adding for dmabuf export")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>

zink: iterate over all modifiers and nuke the ones that aren't supported

the spec mandates that all modifiers passed to the driver be valid, so
iterate through all of them and delete the invalid ones

Fixes: 247b8f2924b ("zink: add all format modifiers when adding for dmabuf export")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>

zink: bail out of dmabuf resource creation when srgb explosion is expected

if srgb-ness isn't supported by the driver for dmabuf, bail out early with an
error message with the assumption that this would later (maybe) explode when
trying to create a view for srgb framebuffer

ref !17900

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>

microsoft/compiler: Fix PSV struct when numthreads is 0

Fixes: d9e575d4 ("microsoft/compiler: DXIL validator 1.6 uses a new PSV struct version")
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18023>

dxil_nir_lower_int_cubemaps: When not lowering samplers, don't touch sampler types

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18025>

microsoft/compiler: Discard shouldn't be marked readnone

Cc: mesa-stable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18034>

aco: Force tex operand to have the correct sub dword size before packing.

get_ssa_temp's and NIR's bit size can differ for scalar sources.
This causes broken packing of the MIMG operands with A16/G16.

Fixes: f5f73db846e ("aco: Support 16bit sources for texture ops.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18008>

radv: refactor descriptor set layout tracking

Separately track descriptor set layouts for pools with
FREE_DESCRIPTOR_SET disabled, instead of reusing
`radv_descriptor_pool::entries`. This saves 8 bytes for each entry and
also avoids some indirection.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16541>

c11: #include <threads.h> when the os/platform provide it

Closes #6964

CC: mesa-stable
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18043>

llvmpipe: Add some missing locking

The lp_rasterizer is shared across contexts, and lp_rast_fence called
without holding rast_mutex could race with rast_mutex being replaced and
unref'd on a different thread.

Fixes: a680fd078c0 ("llvmpipe: make last_fence a screen/rast object not a context one.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18116>

nir: add uses_bindless flag for shader_info

this is cumbersome to detect, so detect it here

the flag denotes the use of either bindless texture operations
or shader variables such that drivers can infer the use of bindless
descriptor management functionality

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18088>

egl/dri2: Error path cleanups

Simplify things for the next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl/dri2: Indenting fix

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl: Add some locking asserts

Make it obvious if we screw up while reworking locking.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl: Convert to simple_mtx_t

Mostly because simple_mtx_assert_locked() will come in handy during
locking re-work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl: Remove redundant fxn param

*Technically* we should be unlocking with the 'disp' and not the 'dpy'
(even though they are the same thing).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl: Drop unused _EGL_FUNC_START() arg

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl: Drop _eglSetFuncName() return

It always returned EGL_TRUE

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

util: Fix vs2019 build error

Needed for dependency on MAX_INT.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

freedreno/drm/virtio: Add some atrace

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

egl: atrace support

Perfetto is showing mutex contention on disp->Mutex when multiple
threads are making egl calls on their own current context.  This
makes it easier to see what is contending with what.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

freedreno/drm: Avoid lock in fd_pipe_del()

If we aren't dropping the last refcnt we don't need the lock.  This
avoids contention between retire-queue against others.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>

radv: do not compress DCC in presence of render loops on GFX10+

DCC shouldn't be compressed for Vulkan feedback loops (ie. render pass
with input attachments). It looks like it has always been broken...
Note that GFX9 and earlier chips aren't affected because they don't
compress DCC on GENERAL.

This fixes
dEQP-VK.rasterization.rasterization_order_attachment_access.format*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18104>

svga: support TGSI_SEMANTIC_TEXCOORD in swtnl draw context

Since PIPE_CAP_TGSI_TEXCOORD is now enabled, texcoord is now declared
as TGSI_SEMANTIC_TEXCOORD instead of TGSI_SEMANTIC_GENERIC.

Fixes assert running REDTurbineDEMO with MTL Renderer when the guest needs to
fallback to swtnl for line stipple.

Fixes: e73443b7a50 ("svga: enable PIPE_CAP_TGSI_TEXCOORD for vgpu10 and up")

Reviewed-by: Martin Krastev <krastevm@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18113>

pan/mdg: Remove disassembler stats

They're now unused and they were never especially useful.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Clean up _bifrost_ decode routines

It's noisy since Bifrost was introduced, unnecessary since we converted to
per-arch GenXML, and wrong since Valhall was added.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Centrally declare pandecode entrypoints

Deduplicate in preparation for CSF.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Defeature disassembler stats

Architecturally, these only work for Midgard, and even on Midgard didn't turn
out to be too useful. While we're removing pandecode cruft, let's remove the
stats that just add noise to Bifrost and Valhall (and largely just noise to
Midgard too).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Unify SFBD/MFBD decoding

It's the same core logic. Unify and let GenXML do its thing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Reorder MFBD decoding

Eliminate some #ifdef by grouping v5 and v6 state separately.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Simplify pandecode_fbd

Remove unsued width/height properties, and use cleaner C syntax to build the
return value.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Stop passing suffixes around

Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Stop passing job index around

There are a lot of problems with passing job_index around:

* Almost entirely unused
* Not particularly helpful even when used
* Mostly ignored for Valhall already
* Doesn't extend to CSF

It only really exists due to the early days of pandecode generating valid C code
as the trace format. With GenXML instead, that's not applicable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Remove pandecode_msg

It hasn't had a consistent semantic meaning since we've switched decoding over
to GenXML.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

pan/decode: Don't pass around memory handles

The hardware doesn't care what BO a given buffer resides in, only what GPU
address it's at. It's simpler to fetch from a GPU address, rather than the pair
of a GPU address and a backing allocation. This cleans up a lot of cruft in
pandecode.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>

tu: Implement VK_EXT_non_seamless_cube_map

Passes CTS tests: dEQP-VK.texture.*non_seamless_*

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18079>

radv/winsys: Return VK_ERROR_INVALID_EXTERNAL_HANDLE if buffer imports fail

Section 11.2.6 of the Vulkan spec states:
"Importing memory from a particular host pointer may not be possible due to
 additional platform-specific restrictions beyond the scope of this
 specification in which case the implementation must fail the memory
 import operation with the error code VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR."

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17995>

radeonsi: prevent u_blitter recursion in si_update_ps_colorbuf0_slot

When u_blitter calls util_blitter_restore_fragment_states we may
end up in si_update_ps_colorbuf0_slot.
This commit makes sure we don't call u_blitter from there.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6921
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17981>

radv: add a very initial implementation of VK_EXT_graphics_pipeline_library

This experimental and very suboptimal implementation of graphics
pipeline library shouldn't be used by anyone, except for development
purposes. It's still under active development from my side. This
extension is only exposed via RADV_PERFTEST=gpl anyways.

It's very suboptimal because RADV doesn't yet support PS epilogs and
VS prologs need to be improved/reworked because GPL changed the logic
(eg. can't know the next stage when compiling a prolog). So, currently
the driver ALWAYS retains NIR shaders during libs creation and it links
and compiles in the final pipeline.

I have WIP branches for approximately everything but it looks simpler
to start merging an initial implementation in order to improve steps
by steps from main. This commit might look simple and short but I
already merged TON of preliminary work. RADV was definitely not ready
for GPL and it's still not completely fine. Expect refactoring again.

This implementation currently pass
dEQP-VK.pipeline.pipeline_library.* on NAVI21, except few feedback
creation tests due to CTS bugs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>

radv: prevent accessing rasterization state when it's NULL

It might be NULL for gfx pipeline libs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>

radv: store vk_graphics_pipeline_state to radv_graphics_pipeline

For gfx pipeline libraries we would have to keep track of the gfx
state, so change how it's allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>

radv: introduce a new pipeline type for graphics libs

It currently inherits from radv_graphics_pipeline because it's simpler
but I think it could be improved because most of fields won't be useful
for libs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>

radv: add radv_graphics_pipeline_import_info() helper

It also initializes dynamic states and active stages. It will also be
used when creating a graphics pipeline library.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>

radv: remove unused pCreateInfo from radv_pipeline_init_blend_state()

I missed this one last time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>

tu: Disable LRZ write when alpha-to-coverage is enabled

Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6876

Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18083>

intel/tools: Also look for 'batch' tag

This changed in the kernel at some point, but I'm not sure when.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18087>

tu: remove tu_syncobj_to_fd

It isnt used anymore, last used in tu_wsi_display.c which doesnt
exist anymore.

Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17927>

iris: Clean up iris_sample_with_depth_aux()

The majority of the logic here was for the Gfx8-9 sample-from-hiz
hardware feature, which only applies to AUX_USAGE_HIZ, and neither
of the combined HiZ+CCS modes.  So, reorganize the function to put
the logic for each case in the case itself.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4674>

iris: Always retain ISL_AUX_USAGE_HIZ_CCS_WT in texture aux usage

When using HIZ_CCS_WT, we always want to use that for texturing so that
we're able to sample from the CCS buffer, which will have the latest
data due to the write-through mode.

With the previous commit in place, HiZ now exists for all miplevels
on platforms which support HIZ_CCS_WT, so we no longer need the
per-miplevel checks.

The other restrictions in this function only apply to the Gfx8-9 feature
where the sampler directly supported reading from HiZ itself, which was
removed.  Hardware where HiZ and CCS can be used together doesn't have
that feature nor its restrictions.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4952
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4674>

iris: Enable HiZ for non-8x4 aligned miplevels on Icelake and later

8x4 alignment was absolutely required prior to Gfx8, and while some
things were relaxed on Gfx8-9, Nanley's experiments in issue #3788
indicated that there were still issues on those platforms.

It appears that the restrictions were relaxed on Icelake and
non-8x4 aligned HiZ "should" work on Gfx11+.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4674>

iris: Pass devinfo to iris_resource_level_has_hiz()

This will let us enforce 8x4 alignment rules differently based on the
specific hardware generation in question.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4674>

ir3: Suppress disasm of internal shaders unless IR3_SHADER_DEBUG=internal.

When you're debugging some deqp test or app, it's irritating to page
through 8 MRT clear shaders in turnip to get to what you're looking for.
Use the info.internal flag to suppress those shaders.  (but if you want to
IR3_SHADER_DEBUG=internal, then yeah, print them all).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18002>

nir_to_tgsi_info: drop const_buffers_declared

Drivers don't use this, so avoid the assert it could have.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18042>

amd/common: Remove redundant code for determining memory ops per clock

Fixes: 82fd379d9ef ("amd/common: move ac_memory_ops_per_clock into ac_gpu_info.h")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18038>

radeonsi/vcn: add decode support for gfx1101 and gfx1103

Add decode support for gfx1101 and gfx1103

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18063>

anv: Free vmas in case device creation fails in pthread_mutex_init(&device->mutex

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>

anv: Remove anv_app_info

Dead-code not used anywhere.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>

anv: Remove duplicated memset() in physical device creation

device is allocated with vk_zalloc() that zeroes the allocated memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>

intel: Simply intel_gem_create_context_engines()

We can use I915_DEFINE_CONTEXT_PARAM_ENGINES() to simply the filling
of engines_param.

As some compilers might not support VLA, defining struct with 64
engines, the maximum that i915 API supports.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>

zink: rework descriptor pool overflow

previously this would just destroy and recreate pools, but it's much
smarter to instead store the pools and just reuse them when needed

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18065>

zink: use a single allocation for zink_descriptor_layout_key

this is slightly more smart

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18065>

zink: use a dynarray instead of hash table for tracking pools

this may use a little more memory, but having direct access to the pool
without needing a lookup in a (potentially big) hash table is definitely
worth it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18065>

zink: add an id member for zink_descriptor_pool_key

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18065>

zink: require VK_KHR_descriptor_update_template

it's been long enough, and there's no technical reason why drivers
shouldn't have this implemented

ZINK_DESCRIPTORS environment variable is preserved for future use

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18065>