Ian Romanick [Thu, 12 Nov 2020 22:50:23 +0000 (14:50 -0800)]
intel/fs: Combine constants for integer instructions too
v2: Remove type change for SHR with negation. This was a leftover from
a previous attempt to deal with SHR and negation. Now all right-shifts
with unsigned parameters are marked as not being able to have source
modifiers.
v3: Disallow negations on right shifts of unsigned sources by setting
the no_negations flag in add_candidate_immediate. This eliminates the
need to exclude SHR in can_do_source_mods.
Tiger Lake
total instructions in shared programs:
21102817 ->
21099443 (-0.02%)
instructions in affected programs: 296796 -> 293422 (-1.14%)
helped: 92 / HURT: 356
total cycles in shared programs:
790564691 ->
790393358 (-0.02%)
cycles in affected programs:
36456886 ->
36285553 (-0.47%)
helped: 171 / HURT: 286
total spills in shared programs: 3951 -> 3959 (0.20%)
spills in affected programs: 176 -> 184 (4.55%)
helped: 0 / HURT: 2
total fills in shared programs: 2631 -> 2639 (0.30%)
fills in affected programs: 176 -> 184 (4.55%)
helped: 0 / HURT: 2
LOST: 0
GAINED: 4
Ice Lake
total instructions in shared programs:
19954204 ->
19949122 (-0.03%)
instructions in affected programs: 40301 -> 35219 (-12.61%)
helped: 23 / HURT: 2
total cycles in shared programs:
858377735 ->
858462082 (<.01%)
cycles in affected programs:
75537286 ->
75621633 (0.11%)
helped: 124 / HURT: 319
total spills in shared programs: 6255 -> 6190 (-1.04%)
spills in affected programs: 392 -> 327 (-16.58%)
helped: 1 / HURT: 2
total fills in shared programs: 7813 -> 7382 (-5.52%)
fills in affected programs: 942 -> 511 (-45.75%)
helped: 1 / HURT: 2
LOST: 0
GAINED: 3
Skylake
total instructions in shared programs:
18049362 ->
18044440 (-0.03%)
instructions in affected programs: 48317 -> 43395 (-10.19%)
helped: 26 / HURT: 2
total cycles in shared programs:
844884806 ->
844915655 (<.01%)
cycles in affected programs:
76137133 ->
76167982 (0.04%)
helped: 171 / HURT: 293
total spills in shared programs: 6148 -> 6149 (0.02%)
spills in affected programs: 595 -> 596 (0.17%)
helped: 4 / HURT: 2
total fills in shared programs: 7484 -> 7067 (-5.57%)
fills in affected programs: 1226 -> 809 (-34.01%)
helped: 4 / HURT: 2
LOST: 0
GAINED: 8
Broadwell
total instructions in shared programs:
17826844 ->
17821805 (-0.03%)
instructions in affected programs: 60687 -> 55648 (-8.30%)
helped: 28 / HURT: 8
total cycles in shared programs:
905332682 ->
904369499 (-0.11%)
cycles in affected programs:
76743509 ->
75780326 (-1.26%)
helped: 179 / HURT: 225
total spills in shared programs: 17922 -> 17908 (-0.08%)
spills in affected programs: 2495 -> 2481 (-0.56%)
helped: 6 / HURT: 8
total fills in shared programs: 26290 -> 25397 (-3.40%)
fills in affected programs: 2606 -> 1713 (-34.27%)
helped: 8 / HURT: 6
LOST: 1
GAINED: 1
Haswell
total instructions in shared programs:
16678878 ->
16674444 (-0.03%)
instructions in affected programs: 78458 -> 74024 (-5.65%)
helped: 87 / HURT: 6
total cycles in shared programs:
880189381 ->
880301043 (0.01%)
cycles in affected programs:
29956463 ->
30068125 (0.37%)
helped: 169 / HURT: 163
total spills in shared programs: 14428 -> 14378 (-0.35%)
spills in affected programs: 2384 -> 2334 (-2.10%)
helped: 8 / HURT: 6
total fills in shared programs: 16975 -> 16881 (-0.55%)
fills in affected programs: 1334 -> 1240 (-7.05%)
helped: 10 / HURT: 4
Ivy Bridge
total instructions in shared programs:
15706048 ->
15706035 (<.01%)
instructions in affected programs: 9941 -> 9928 (-0.13%)
helped: 13 / HURT: 0
total cycles in shared programs:
433618834 ->
433624637 (<.01%)
cycles in affected programs:
12926714 ->
12932517 (0.04%)
helped: 52 / HURT: 41
Sandy Bridge
total cycles in shared programs:
741223552 ->
741223443 (<.01%)
cycles in affected programs: 19814 -> 19705 (-0.55%)
helped: 14 / HURT: 0
No changes on Iron Lake or GM45
fossil-db changes:
Tiger Lake
Instructions in all programs:
156858030 ->
156905532 (+0.0%)
Instructions helped: 3915
Instructions hurt: 15411
Cycles in all programs:
7529667771 ->
7532117340 (+0.0%)
Cycles helped: 10260
Cycles hurt: 9990
Spills in all programs: 5610 -> 5457 (-2.7%)
Spills helped: 18
Fills in all programs: 6274 -> 6091 (-2.9%)
Fills helped: 18
Gained: 2
Lost: 16
Ice Lake
Instructions in all programs:
141308082 ->
141303083 (-0.0%)
Instructions helped: 574
Instructions hurt: 172
Cycles in all programs:
9091361325 ->
9094622766 (+0.0%)
Cycles helped: 8764
Cycles hurt: 11702
Spills in all programs: 7531 -> 7385 (-1.9%)
Spills helped: 19
Fills in all programs: 8462 -> 8294 (-2.0%)
Fills helped: 19
Gained: 22
Lost: 15
Skylake
Instructions in all programs:
131872162 ->
131867263 (-0.0%)
Instructions helped: 566
Instructions hurt: 172
Cycles in all programs:
8795095440 ->
8799676943 (+0.1%)
Cycles helped: 8333
Cycles hurt: 12182
Spills in all programs: 7006 -> 6884 (-1.7%)
Spills helped: 13
Fills in all programs: 7696 -> 7552 (-1.9%)
Fills helped: 13
Gained: 24
Lost: 1
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>
Ian Romanick [Tue, 4 Aug 2020 23:39:06 +0000 (16:39 -0700)]
intel/fs: Combine constants for SEL instructions too
It is very common to have bcsel where the second and third sources are
both constants. This results in a situation where we would want to emit
a SEL with two constant sources, but that's not allowed.
Previously, we would load both constants into registers, then let
constant propagation copy the last constant into the SEL instruction.
This results in the constant using an entire SIMD register instead of a
single channel.
Instead, copy propagate both sources, then let the combine-constants
pass do its thing. In the worst case, this stores the constant in a
single channel of the SIMD register. In the best case, it reuses a
value that was loaded into a register to satisfy another instruction.
shader-db results:
Tiger Lake, Ice Lake, and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs:
19951549 ->
19948709 (-0.01%)
instructions in affected programs: 482795 -> 479955 (-0.59%)
helped: 1184 / HURT: 3
total cycles in shared programs:
858584724 ->
858205341 (-0.04%)
cycles in affected programs:
356168375 ->
355788992 (-0.11%)
helped: 1448 / HURT: 1195
total spills in shared programs: 6569 -> 6255 (-4.78%)
spills in affected programs: 912 -> 598 (-34.43%)
helped: 58 / HURT: 0
total fills in shared programs: 8218 -> 7813 (-4.93%)
fills in affected programs: 1570 -> 1165 (-25.80%)
helped: 58 / HURT: 0
LOST: 6
GAINED: 16
Broadwell
total instructions in shared programs:
17819660 ->
17819389 (<.01%)
instructions in affected programs: 1078129 -> 1077858 (-0.03%)
helped: 1067 / HURT: 304
total cycles in shared programs:
904722624 ->
905035016 (0.03%)
cycles in affected programs:
362583117 ->
362895509 (0.09%)
helped: 1381 / HURT: 1123
total spills in shared programs: 17884 -> 17922 (0.21%)
spills in affected programs: 5088 -> 5126 (0.75%)
helped: 55 / HURT: 152
total fills in shared programs: 25533 -> 26290 (2.96%)
fills in affected programs: 12992 -> 13749 (5.83%)
helped: 61 /HURT: 295
LOST: 7
GAINED: 24
Haswell
total instructions in shared programs:
16678080 ->
16673976 (-0.02%)
instructions in affected programs: 1162893 -> 1158789 (-0.35%)
helped: 1584 / HURT: 7
total cycles in shared programs:
880180082 ->
879932525 (-0.03%)
cycles in affected programs:
364067522 ->
363819965 (-0.07%)
helped: 1226 / HURT: 976
total spills in shared programs: 14937 -> 14428 (-3.41%)
spills in affected programs: 7866 -> 7357 (-6.47%)
helped: 351 / HURT: 5
total fills in shared programs: 17572 -> 16975 (-3.40%)
fills in affected programs: 11028 -> 10431 (-5.41%)
helped: 350 / HURT: 3
LOST: 8
GAINED: 16
Ivy Bridge
total instructions in shared programs:
15704044 ->
15703158 (<.01%)
instructions in affected programs: 304513 -> 303627 (-0.29%)
helped: 707 / HURT: 0
total cycles in shared programs:
433560149 ->
433471118 (-0.02%)
cycles in affected programs:
19299650 ->
19210619 (-0.46%)
helped: 687 / HURT: 395
LOST: 2
GAINED: 9
Sandy Bridge
total instructions in shared programs:
13913386 ->
13912884 (<.01%)
instructions in affected programs: 195687 -> 195185 (-0.26%)
helped: 455 / HURT: 0
total cycles in shared programs:
741156272 ->
741136266 (<.01%)
cycles in affected programs:
10934349 ->
10914343 (-0.18%)
helped: 578 / HURT: 289
LOST: 9
GAINED: 4
Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8364056 -> 8364042 (<.01%)
instructions in affected programs: 5178 -> 5164 (-0.27%)
helped: 10 / HURT: 0
total cycles in shared programs:
248759794 ->
248757940 (<.01%)
cycles in affected programs: 4305246 -> 4303392 (-0.04%)
helped: 183 / HURT: 24
fossil-db results:
Tiger Lake
Instructions in all programs:
156943594 ->
156802601 (-0.1%)
Instructions helped: 20595
Instructions hurt: 23248
Cycles in all programs:
7512086950 ->
7528386387 (+0.2%)
Cycles helped: 29531
Cycles hurt: 27837
Spills in all programs: 13500 -> 5643 (-58.2%)
Spills helped: 394
Spills hurt: 22
Fills in all programs: 18943 -> 6306 (-66.7%)
Fills helped: 394
Fills hurt: 11
Gained: 93
Lost: 76
Ice Lake
Instructions in all programs:
141395899 ->
141249621 (-0.1%)
Instructions helped: 30067
Instructions hurt: 3
Cycles in all programs:
9097127057 ->
9089668235 (-0.1%)
Cycles helped: 32268
Cycles hurt: 24315
Spills in all programs: 13695 -> 7564 (-44.8%)
Spills helped: 403
Fills in all programs: 18400 -> 8494 (-53.8%)
Fills helped: 403
Gained: 114
Lost: 137
Skylake
Instructions in all programs:
131948328 ->
131826063 (-0.1%)
Instructions helped: 29968
Instructions hurt: 3
Cycles in all programs:
8794778440 ->
8793934844 (-0.0%)
Cycles helped: 32705
Cycles hurt: 23575
Spills in all programs: 10526 -> 7039 (-33.1%)
Spills helped: 403
Fills in all programs: 11025 -> 7728 (-29.9%)
Fills helped: 403
Gained: 102
Lost: 250
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>
Ian Romanick [Mon, 8 Jun 2020 22:18:19 +0000 (15:18 -0700)]
intel/fs: Completely re-write the combine constants pass
The is a squash of what in the original MR was "util: Add generic pass
that tries to combine constants" and "intel/fs: Switch to using
util_combine_constants".
The new algorithm uses a multi-pass greedy algorithm that attempts to
collect constants for loading in order of increasing degrees of freedom.
The first pass collects constants that must be emitted as-is (e.g.,
without source modifiers).
The second pass emits all constants that must be emitted (because they
are used in a source field that cannot be a literal constant) but that
can have a source modifier.
The final pass possibly emits constants that may not have to be emitted.
This is used for instructions where one of the fields is allowed to be a
constant. This is not used in the current commit, but future commits
that enable SEL will use this. The SEL instruction can have a single
constant, but when both sources are constant, one of the sources has to
be loaded into a register.
By loading constants in this order, required "choices" made in earlier
passes may be re-used in later passes. This provides a more optimal
result.
At this point in the series, most platforms have the same results with
the new implementation. Gen7 platforms see a significant number of
"small" changes. Due to the coissue optimization on Gen7, each shader
is likely to have most constants affected by constant combining.
If a shader has only a single basic block, constants are packed into
registers in the order produced by the constant combining process.
Since each constant has a different live range in the shader, even
slightly different packing orders can have dramatic effects on the live
range of a register. Even in cases where this does not affect register
pressure in a meaningful way, it can cause the scheduler to make very
different choices about the ordering of instructions.
From my analysis (using the `if (debug) { ... }` block at the end of
fs_visitor::opt_combine_constants), the old implementation and the new
implementation pick the same set of constants, but the order produced
may be slightly different. For the smaller number of values in non-Gfx7
shaders, the orders are similar enough to not matter.
No shader-db or fossil-db changes on any non-Gfx7 platforms.
Haswell and Ivy Bridge had similar results. (Haswell shown)
total cycles in shared programs:
879930036 ->
880001666 (<.01%)
cycles in affected programs:
22485040 ->
22556670 (0.32%)
helped: 1879
HURT: 2309
helped stats (abs) min: 1 max: 6296 x̄: 258.54 x̃: 34
helped stats (rel) min: <.01% max: 54.63% x̄: 3.88% x̃: 0.87%
HURT stats (abs) min: 1 max: 9739 x̄: 241.41 x̃: 40
HURT stats (rel) min: <.01% max: 160.50% x̄: 6.01% x̃: 0.99%
95% mean confidence interval for cycles value: -1.04 35.25
95% mean confidence interval for cycles %-change: 1.23% 1.92%
Inconclusive result (value mean confidence interval includes 0).
LOST: 82
GAINED: 39
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>
Helen Koike [Mon, 28 Aug 2023 20:40:46 +0000 (17:40 -0300)]
ci/android: remove strace output from cuttlefish-runner.sh
strace output is only used for debug and its output takes too much
space. Remove it to save resources.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Fixes:
7b51a583edb7 ("ci/android: add android to the ci")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24913>
Helen Koike [Mon, 28 Aug 2023 19:23:09 +0000 (16:23 -0300)]
ci: add --project option to ci_run_n_monitor.py
Now that we have drm-ci, add --project, so the script can also be used
to linux (and any other projects).
Let the default to "mesa" so it can keep behaving as before when the
option is not given.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24912>
Eric Engestrom [Fri, 25 Aug 2023 19:09:29 +0000 (20:09 +0100)]
ci/farm-rules: fix missing valve-infra jobs in scheduled pipelines
Fixes:
79f7882fc60451530235 ("ci: add quirk for GitLab assuming changes is always true for scheduled runs")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24897>
Alyssa Rosenzweig [Thu, 24 Aug 2023 20:01:32 +0000 (16:01 -0400)]
nir/lower_shader_calls: Fix warning with clang
Implicit conversion warning.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24864>
Konstantin Seurer [Thu, 24 Aug 2023 12:14:24 +0000 (14:14 +0200)]
nir/lower_shader_calls: Limit the remat chain length
There is no way we will rematerialize a 40k instruction long chain and
it also won't be beneficial. This improves the replay time if our CP2077
fossil by 350% when compiling only ray tracing pipelines.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24864>
David Heidelberg [Tue, 29 Aug 2023 12:02:03 +0000 (14:02 +0200)]
panvk: catch unsupported arch in the panvk_physical_device_init
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24201>
David Heidelberg [Mon, 17 Jul 2023 23:01:33 +0000 (01:01 +0200)]
panvk: architecture isn't invalid, just unsupported
When we fail, tell users clearly why.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24201>
David Rosca [Tue, 29 Aug 2023 11:34:56 +0000 (13:34 +0200)]
gallium/auxiliary/vl: Set vertex element src_stride in vl_deint_filter
Fixes:
76725452239 ("gallium: move vertex stride to CSO")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24926>
Rhys Perry [Fri, 25 Aug 2023 18:21:54 +0000 (19:21 +0100)]
aco/spill: skip p_branch in process_block
Fixes compilation of a Dead by Daylight shader.
fossil-db (gfx1100):
Totals from 58 (0.04% of 133461) affected shaders:
Instrs: 319824 -> 319421 (-0.13%); split: -0.13%, +0.00%
CodeSize: 1711260 -> 1708744 (-0.15%); split: -0.15%, +0.00%
SpillSGPRs: 2567 -> 2459 (-4.21%)
Latency: 3274930 -> 3274921 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 924106 -> 924105 (-0.00%); split: -0.00%, +0.00%
Copies: 41883 -> 41757 (-0.30%); split: -0.31%, +0.00%
Branches: 9144 -> 9146 (+0.02%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9599
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24896>
David Heidelberg [Tue, 29 Aug 2023 10:23:35 +0000 (12:23 +0200)]
ci/panfrost: add G52 simple_tests.partial_image_pot_same_format_noclear flake
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>
David Heidelberg [Tue, 29 Aug 2023 10:23:22 +0000 (12:23 +0200)]
ci/freedreno: add another a530 flake
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>
David Heidelberg [Tue, 29 Aug 2023 09:57:23 +0000 (11:57 +0200)]
ci/virgl: flakes in functional.draw_buffers_indexed group
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>
Timothy Arceri [Tue, 29 Aug 2023 02:53:15 +0000 (12:53 +1000)]
util: add radeonsi workaround for Nowhere Patrol
Cc: mesa-stable
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24919>
Samuel Pitoiset [Tue, 22 Aug 2023 18:36:57 +0000 (20:36 +0200)]
aco: fix emitting TCS epilogs end on GFX9+
With merged shaders, the long-jump should be emitted inside the
divergent if (ie. only for TCS invocations) and other non TCS
invocations should just end the program.
This fixes a bunch of failures with CTS by forcing TCS epilogs on
RDNA2.
Not sure how RadeonSI will handle that but maybe doing the merged
wave info thing in epilogs would help.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24832>
Samuel Pitoiset [Thu, 24 Aug 2023 09:32:58 +0000 (11:32 +0200)]
radv: remove the pipeline dependency for emitting VGT_GS_MODE
For shader object.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24865>
Alejandro Piñeiro [Tue, 15 Aug 2023 07:19:12 +0000 (09:19 +0200)]
v3dv: re-enable sync_fd import/export on the simulator
On commit
29588fe11667 we re-enable sync_fd import/export. But only
with the real hw, because at that time there were wrong CTS tests
(that were calling vkSetEvent after submission) that needed to be
fixed.
Since this commit:
https://github.com/KhronosGroup/VK-GL-CTS/commit/
717c051d4bcc9b71f13bc6b223e9926dcf9b7bd5
Those tests are fixed. That fix has been on CTS releases for some
time. So we can enable it on the simulator too.
With this change the pattern dEQP-VK.api.external.semaphore.sync_fd*
goes from 2 Passed/10 Not Supported to 12 Passed on the simulator.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24688>
Samuel Pitoiset [Fri, 25 Aug 2023 14:47:06 +0000 (16:47 +0200)]
radv: fix emitting TCS epilogs if TES and GS are linked on GFX9+
TES would be NULL because everything is merged to GS.
Found by inspection.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>
Samuel Pitoiset [Fri, 25 Aug 2023 14:45:50 +0000 (16:45 +0200)]
radv: small cleanups in radv_emit_patch_control_points()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>
Samuel Pitoiset [Fri, 25 Aug 2023 14:40:38 +0000 (16:40 +0200)]
radv: rename tcs_shader to tcs in radv_emit_tcs_epilog_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>
Mike Blumenkrantz [Fri, 25 Aug 2023 14:16:55 +0000 (10:16 -0400)]
zink: remove sync TODO
after investigating, this is pointless and won't ever generate any value
fixes #9016
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
Mike Blumenkrantz [Thu, 24 Aug 2023 14:53:05 +0000 (10:53 -0400)]
zink: simplify some image barrier conditionals
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
Mike Blumenkrantz [Thu, 24 Aug 2023 14:50:53 +0000 (10:50 -0400)]
zink: make image barrier init functions void return
the return value was never used
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
Mike Blumenkrantz [Thu, 24 Aug 2023 13:40:42 +0000 (09:40 -0400)]
zink: reset unordered flags for image barriers on non-matching batch access
this allows more reordering when the first barrier in a new cmdbuf can
be reordered after previous ordered access exists
KHR-GLES3.copy_tex_image_conversions.required.texture2d_cubemap_negz:
before - ordered 68
after - ordered 16
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
Mike Blumenkrantz [Thu, 24 Aug 2023 13:27:11 +0000 (09:27 -0400)]
zink: force-reset unordered flags for buffer barriers on non-matching batch access
this should allow slightly better reordering
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
Simon Ser [Fri, 25 Aug 2023 13:43:58 +0000 (15:43 +0200)]
vulkan/wsi/wayland: fix unset present_mode
chain->base.present_mode is unset at this point, ie. it's
zero-initialized. VK_PRESENT_MODE_IMMEDIATE_KHR happens to be 0,
so the WSI will attempt to use tearing-control on compositors that
don't support it.
Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes:
5ceba97c2e18 ("vulkan/wsi/wayland: add support for IMMEDIATE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24885>
Mike Blumenkrantz [Fri, 25 Aug 2023 17:39:19 +0000 (13:39 -0400)]
zink: fix optimal_keys warning message
needs more newlines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>
Mike Blumenkrantz [Fri, 25 Aug 2023 17:20:22 +0000 (13:20 -0400)]
zink: be consistent with ds3 state resetting for blits
handle no-stipple case
Fixes:
122ffb0c888 ("zink: unset line stipple ds3 state flags when stipple not available")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>
Mike Blumenkrantz [Fri, 25 Aug 2023 17:19:34 +0000 (13:19 -0400)]
zink: break out ds3 state resetting
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>
Bas Nieuwenhuizen [Sat, 19 Aug 2023 22:47:07 +0000 (00:47 +0200)]
vulkan: Add trace points for more Vulkan waiting functions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24799>
Ruijing Dong [Fri, 25 Aug 2023 21:44:29 +0000 (17:44 -0400)]
frontends/va: checking va version for av1enc support
need to ensure va version >= 1.16 to support av1enc.
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24901>
Yiwei Zhang [Thu, 24 Aug 2023 19:26:32 +0000 (12:26 -0700)]
venus: expose at least one cached memory type
Kernel makes every mapping coherent. If a memory type is truly
incoherent, it's better to remove the host-visible flag than silently
making it coherent. However, for app compatibility purpose, when
coherent-cached memory type is unavailable, we emulate the first cached
memory type with the first coherent memory type.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24875>
Sil Vilerino [Sat, 26 Aug 2023 20:04:40 +0000 (16:04 -0400)]
d3d12: Fix H264 interlaced decode
Have to set the interlaced field of the surface before
end_frame is called in the pipe codec object so the info
is available to the frontend/va, instead of setting it
directly in end_frame like before.
Fixes:
578e10e1571 ("frontends/va: Alloc interlaced surface for interlaced pics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24909>
Sil Vilerino [Fri, 25 Aug 2023 21:02:00 +0000 (17:02 -0400)]
d3d12: Fix Map/Unmap of YUV resources
Restore transfer box original size after temporal per plane
dimension calculation.
Currently the returned transfer object on Map will have the
size (usually downsampled) of the latest plane instead of
the overall resource size. Then on unmap, when flushing the
changes the received transfer box has the wrong dimensions
and only partial data is flushed.
Fixes:
12a4f2c1328 ("frontends/va: Also map VAImageBufferType for reading")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24909>
Vinson Lee [Mon, 21 Aug 2023 00:53:09 +0000 (17:53 -0700)]
vk/wsi/x11: Remove dead code
Fix defect reported by Coverity Scan.
Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement: return VK_ERROR_SURFACE_LOS....
Fixes:
fb9f697fbb8 ("vk/wsi/x11: move surface alpha check from get_caps to creation")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24802>
Vinson Lee [Mon, 21 Aug 2023 00:31:06 +0000 (17:31 -0700)]
nv50: Remove unused value
Fix defect reported by Coverity Scan.
Unused value (UNUSED_VALUE)
assigned_pointer: Assigning value from &nv50->vtxbuf[b] to vb here, but
that stored value is overwritten before it can be used.
Fixes:
76725452239 ("gallium: move vertex stride to CSO")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24801>
Paul Gofman [Fri, 18 Aug 2023 21:58:12 +0000 (15:58 -0600)]
driconf: add a workaround for Rainbow Six Extraction
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24784>
M Henning [Sat, 19 Aug 2023 19:48:02 +0000 (15:48 -0400)]
nv/codegen: Delete copy and assign
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24904>
M Henning [Sat, 19 Aug 2023 19:46:14 +0000 (15:46 -0400)]
nv/codegen: Change copy-constructor call to assign
This almost certainly intends to call the user-definied assignment
operator here instead of the automatically generated copy constructor.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24904>
Ian Romanick [Fri, 21 Jul 2023 23:50:01 +0000 (16:50 -0700)]
nir/algebraic: Remove redundant pack / unpack lowering patterns
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24900>
Ian Romanick [Sat, 22 Jul 2023 00:01:35 +0000 (17:01 -0700)]
nir/builder: Add nir_extract_i8_imm and nir_extract_u8_imm helpers
v2: Fix problems with 16-bit src0.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24899>
Caio Oliveira [Thu, 27 Jul 2023 21:54:02 +0000 (14:54 -0700)]
hasvk/tests: Propagate failures to gtest
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24355>
Caio Oliveira [Thu, 27 Jul 2023 21:18:43 +0000 (14:18 -0700)]
hasvk/tests: Link a single hasvk_tests binary using gtest
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24355>
Caio Oliveira [Thu, 27 Jul 2023 21:06:45 +0000 (14:06 -0700)]
hasvk/tests: Refactor state_pool_test_helper to not use macros for parametrization
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24355>
Caio Oliveira [Thu, 27 Jul 2023 21:54:02 +0000 (14:54 -0700)]
anv/tests: Propagate failures to gtest
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24355>
Caio Oliveira [Thu, 27 Jul 2023 21:18:43 +0000 (14:18 -0700)]
anv/tests: Link a single anv_tests binary using gtest
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24355>
Caio Oliveira [Thu, 27 Jul 2023 21:06:45 +0000 (14:06 -0700)]
anv/tests: Refactor state_pool_test_helper to not use macros for parametrization
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24355>
David Heidelberg [Thu, 24 Aug 2023 17:28:01 +0000 (19:28 +0200)]
ci/panfrost: we have enough device, parallelize Vulkan tests
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24873>
David Heidelberg [Thu, 24 Aug 2023 17:26:47 +0000 (19:26 +0200)]
ci/panfrost: add G52 flakes
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24873>
Roland Scheidegger [Fri, 25 Aug 2023 13:46:35 +0000 (15:46 +0200)]
lavapipe: further limit accurate_a0 hack
With lavapipe the previous change to only enable the hack when there's
no textures bound doesn't work anymore, since we don't have that
information when using the texture handles.
So add another random state restriction which is sufficient to pass
tests. (This really needs a better long term solution.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24887>
Mike Blumenkrantz [Fri, 25 Aug 2023 16:46:36 +0000 (12:46 -0400)]
zink: add a618 flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24892>
Pavel Ondračka [Tue, 22 Aug 2023 14:25:10 +0000 (16:25 +0200)]
r300: there is no limitation on presubtract source file
RV530 shader-db:
total instructions in shared programs: 128840 -> 128803 (-0.03%)
instructions in affected programs: 1085 -> 1048 (-3.41%)
helped: 37
HURT: 1
total presub in shared programs: 7670 -> 7751 (1.06%)
presub in affected programs: 328 -> 409 (24.70%)
helped: 0
HURT: 81
total temps in shared programs: 16926 -> 16939 (0.08%)
temps in affected programs: 182 -> 195 (7.14%)
helped: 6
HURT: 19
total cycles in shared programs: 193751 -> 193729 (-0.01%)
cycles in affected programs: 3088 -> 3066 (-0.71%)
helped: 33
HURT: 5
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24830>
Pavel Ondračka [Mon, 17 Jul 2023 12:49:21 +0000 (14:49 +0200)]
r300: move power of two multipliers down
RV530 shader-db:
total instructions in shared programs: 128864 -> 128840 (-0.02%)
instructions in affected programs: 1260 -> 1236 (-1.90%)
helped: 21
HURT: 2
total presub in shared programs: 7682 -> 7670 (-0.16%)
presub in affected programs: 77 -> 65 (-15.58%)
helped: 12
HURT: 0
total omod in shared programs: 386 -> 403 (4.40%)
omod in affected programs: 3 -> 20 (566.67%)
helped: 0
HURT: 14
total temps in shared programs: 16948 -> 16926 (-0.13%)
temps in affected programs: 280 -> 258 (-7.86%)
helped: 20
HURT: 2
total cycles in shared programs: 194101 -> 193751 (-0.18%)
cycles in affected programs: 3422 -> 3072 (-10.23%)
helped: 25
HURT: 5
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6855
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24830>
Pavel Ondračka [Tue, 22 Aug 2023 14:08:01 +0000 (16:08 +0200)]
r300: convert x * 2 into x + x for presubtract
total instructions in shared programs: 128859 -> 128864 (<.01%)
instructions in affected programs: 931 -> 936 (0.54%)
helped: 0
HURT: 5
total presub in shared programs: 7635 -> 7682 (0.62%)
presub in affected programs: 208 -> 255 (22.60%)
helped: 0
HURT: 17
total cycles in shared programs: 194124 -> 194101 (-0.01%)
cycles in affected programs: 1671 -> 1648 (-1.38%)
helped: 9
HURT: 1
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24830>
Pavel Ondračka [Wed, 9 Aug 2023 08:17:48 +0000 (10:17 +0200)]
r300: implement bias presubtract
RV530 shader-db:
total instructions in shared programs: 129468 -> 128859 (-0.47%)
instructions in affected programs: 34432 -> 33823 (-1.77%)
helped: 362
HURT: 56
total presub in shared programs: 5411 -> 7635 (41.10%)
presub in affected programs: 2069 -> 4293 (107.49%)
helped: 8
HURT: 468
total temps in shared programs: 16918 -> 16944 (0.15%)
temps in affected programs: 2022 -> 2048 (1.29%)
helped: 73
HURT: 79
total lits in shared programs: 3555 -> 2913 (-18.06%)
lits in affected programs: 2346 -> 1704 (-27.37%)
helped: 479
HURT: 0
total cycles in shared programs: 194675 -> 194124 (-0.28%)
cycles in affected programs: 62939 -> 62388 (-0.88%)
helped: 343
HURT: 84
Also dEQP-GLES2.functional.shaders.random.trigonometric.fragment.15
now fits into the instruction limit on RV370.
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24830>
Pavel Ondračka [Wed, 9 Aug 2023 06:32:01 +0000 (08:32 +0200)]
r300: exit early in presubtract is not supported
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24830>
Pavel Ondračka [Mon, 17 Jul 2023 11:17:04 +0000 (13:17 +0200)]
r300: reorder for easier presubtract 1-x pattern recognition
It is much easier to just add a simple late algebraic pass than actually
trying to teach the backend to recognize all the different patterns.
RV530 shader-db:
total instructions in shared programs: 129643 -> 129468 (-0.13%)
instructions in affected programs: 17665 -> 17490 (-0.99%)
helped: 176
HURT: 39
total presub in shared programs: 4912 -> 5411 (10.16%)
presub in affected programs: 1651 -> 2150 (30.22%)
helped: 0
HURT: 287
total temps in shared programs: 16904 -> 16918 (0.08%)
temps in affected programs: 812 -> 826 (1.72%)
helped: 25
HURT: 37
total cycles in shared programs: 194771 -> 194675 (-0.05%)
cycles in affected programs: 28096 -> 28000 (-0.34%)
helped: 146
HURT: 41
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9364
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24830>
Mike Blumenkrantz [Mon, 17 Oct 2022 14:11:08 +0000 (10:11 -0400)]
zink: pass KERNEL shaders through successfully
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24868>
Mike Blumenkrantz [Mon, 17 Oct 2022 13:34:01 +0000 (09:34 -0400)]
rusticl: fixes for zink shader images
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24868>
Karol Herbst [Tue, 22 Aug 2023 17:37:52 +0000 (19:37 +0200)]
rusticl/device: _MAX_CONST_BUFFER0_SIZE is unsigned
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24868>
Karol Herbst [Tue, 22 Aug 2023 19:17:33 +0000 (21:17 +0200)]
rusticl: add debug option to sync every event
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24868>
Samuel Pitoiset [Wed, 23 Aug 2023 12:14:40 +0000 (14:14 +0200)]
radv,aco: remove unused clip/cull distances variables
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24883>
Samuel Pitoiset [Thu, 24 Aug 2023 07:41:46 +0000 (09:41 +0200)]
aco: add support for compiling {VS,TES}+GS separately on GFX9+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24862>
Samuel Pitoiset [Thu, 24 Aug 2023 07:41:55 +0000 (09:41 +0200)]
aco: ensure to initialize exec manually for non-monolithic {VS,TES}/GS on GFX9+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24862>
Samuel Pitoiset [Thu, 24 Aug 2023 06:13:02 +0000 (08:13 +0200)]
radv: preserve shader arguments for non-monolithic {VS,TES}/GS on GFX9+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24862>
Samuel Pitoiset [Thu, 24 Aug 2023 06:13:26 +0000 (08:13 +0200)]
radv: always declare some arguments for non-monolithic {VS,TES}/GS shaders
When compiling VS/TES and GS separately, we can't know if the GS will
need shader queries, so we have to always declare this argument.
Similar story for the view index.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24862>
Kenneth Graunke [Fri, 25 Aug 2023 07:12:43 +0000 (00:12 -0700)]
iris: Check prog[] instead of uncompiled[] for BLORP state skipping
Huge thanks to Tapani Pälli for debugging this issue, figuring out
what was going wrong, proposing fixes, and walking me through where
things were going off the rails.
BLORP always disables tessellation and geometry shaders. Our handling
tried to look at ice->shaders.uncompiled[] to determine whether the next
draw needed those shaders. If not, we can leave BLORP's residual state
that disabled those stages in place, and skip looking at it.
Unfortunately, predicting the future is a bit fraught, in part due to
the uncompiled[] and prog[] arrays being slightly out of sync at times.
Consider the following case:
1. Draw with tessellation shaders in place
=> uncompiled[TES] and prog[TES] will both point at valid shaders.
2. Gallium calls pipe->bind_tes_state(NULL).
=> This makes uncompiled[TES] point at NULL, and flags
IRIS_STAGE_DIRTY_UNCOMPILED_TES.
Because iris_update_compiled_shaders() hasn't happened yet,
uncompiled[TES] is NULL but prog[TES] has the stale TES from
the previous draw still.
3. BLORP operations happen
=> BLORP sees uncompiled[TES] == NULL and decides that tessellation
is off for the upcoming draws. So it skips flagging tess state.
4. Gallium calls pipe->bind_tes_state(shader from step #1).
=> uncompiled[TES] points at the original shader.
IRIS_STAGE_DIRTY_UNCOMPILED_TES gets flagged again.
5. Draw again
=> This calls iris_update_compiled_shaders(), which sees that
a TES is bound, and calls iris_update_compiled_tes(). But
because the same shader was bound as before, the program it
comes up with is identical to the one already bound at
ice->shaders.prog[TES]. So, it thinks it doesn't have to
flag any tessellation state dirty because it was already
set up for the last draw.
This random unbind and rebind between draws leads to a situation
where, at step #3, BLORP thinks it can skip flagging tessellation
state (nothing is bound), and at step #5, normal state handling
thinks it can skip flagging tessellation state (nothing changed
since last time). So nobody does, and things break.
This unbind appears to be happening when st_release_variants()
decides it wants to free some shaders. Then a rebind happens to
put back the actual shader for the draw. So, it's not theoretical.
To fix this, we change BLORP to look at ice->shaders.prog[] rather
than uncompiled[]. This is equivalent to thinking about the previous
draw, rather than the next. If the last draw had tessellation off,
then BLORP's disabling was a no-op, and the GPU is still in the same
state as the previous draw. This is more reliable than predicting
the future.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8308
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9678
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24880>
Yiwei Zhang [Mon, 21 Aug 2023 22:15:26 +0000 (15:15 -0700)]
venus: set deviceMemoryReport feature
VK_EXT_device_memory_report is implemented in venus driver side, which
has a feature struct. So we must enable it after setting features for
renderer extensions. This change also includes tiny format fixes.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24881>
Konstantin Seurer [Fri, 18 Aug 2023 10:30:05 +0000 (12:30 +0200)]
venus: Use the common GetPhysicalDeviceFeatures2 implementation
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24881>
Konstantin Seurer [Wed, 16 Aug 2023 15:16:07 +0000 (17:16 +0200)]
vulkan/wsi/x11: Implement capture hotkey using the keymap
This way, we can avoid opening another connection. The capture key is
changes to F1 because F12 has issues on Wayland. (After pressing F12,
all keys become unresponsive, refocussing the window fixes it)
Fixes: 291fa05 ("vulkan/wsi/x11: Capture traces using a hotkey")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9578
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24710>
Samuel Pitoiset [Tue, 15 Aug 2023 13:20:16 +0000 (15:20 +0200)]
aco: add support for compiling VS+TCS separately on GFX9+
The VS will just jump to the TCS.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Mon, 21 Aug 2023 13:50:23 +0000 (15:50 +0200)]
aco: ensure to initialize exec manually for VS as LS on GFX9+
When VS and TCS are compiled separately with shader object on GFX9+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Tue, 15 Aug 2023 08:52:53 +0000 (10:52 +0200)]
aco: disable shared VGPRs for non-monolithic shaders on GFX9+
For unmerged shaders on GFX9+, we would need to jump to the second
shader part which means shared VGPRs can't be enabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Wed, 23 Aug 2023 16:11:14 +0000 (18:11 +0200)]
radv: preserve shader arguments for non-monolithic VS/TCS on GFX9+
This is more robust than re-creating the function signature in ACO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Wed, 23 Aug 2023 16:10:25 +0000 (18:10 +0200)]
ac: allow to mark shader arguments as preserved
These arguments would be used by ACO to generate a function signature
for merged shaders automatically.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Tue, 15 Aug 2023 09:56:56 +0000 (11:56 +0200)]
radv: add a new shader argument for non-monolithic shaders PC
This will be used to jump from VS to TCS/GS or TES to GS on GFX9+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Wed, 23 Aug 2023 14:56:58 +0000 (16:56 +0200)]
radv: always declare some arguments for non-monolithic VS/TCS shaders
For separate VS/TCS compilation on GFX9+, the TCS might be using push
constants but not the VS and we can't know this information when
compiling the VS. Similar logic for the other arguments.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Tue, 15 Aug 2023 09:41:17 +0000 (11:41 +0200)]
radv: force indirect descriptor sets for non-monolithic shaders
When VS and TCS are compiled separately on GFX9+, we can't know how
many descriptor sets are used for both stages and the function
arguments must match.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Tue, 15 Aug 2023 09:37:46 +0000 (11:37 +0200)]
radv: do not inline push constants for non-monolithic shaders
It's hard to implement this because the function arguments must match
when eg. VS or TCS are compiled separately on GFX9+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Wed, 23 Aug 2023 14:48:49 +0000 (16:48 +0200)]
radv: use info->uses_view_index directly when declaring shader arguments
No need for a separate variable.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Samuel Pitoiset [Mon, 14 Aug 2023 10:01:49 +0000 (12:01 +0200)]
radv: add radv_shader_info::is_monolithic
This will be used to implement shader object on GFX9+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
Benjamin Cheng [Mon, 21 Aug 2023 13:58:15 +0000 (09:58 -0400)]
anv/video: send h264 scaling list in raster order
ITU spec defines the H264 ScalingList{4x4,8x8} in zig-zag order, but
Intel HW wants raster order.
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
Benjamin Cheng [Tue, 8 Aug 2023 23:52:37 +0000 (19:52 -0400)]
radv/video: send h264 scaling list in raster order
ITU spec defines the H264 ScalingList{4x4,8x8} in zig-zag order, but
AMD HW wants raster order.
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
Benjamin Cheng [Tue, 8 Aug 2023 23:20:52 +0000 (19:20 -0400)]
util/vl: extract gallium vl scanning data to shared code
Vulkan video on both ANV and RADV need these data to make converting
from zig-zag to raster order easier.
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
Benjamin Cheng [Wed, 9 Aug 2023 05:32:16 +0000 (01:32 -0400)]
anv/video: use vk_video_derive_h264_scaling_list
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
Benjamin Cheng [Wed, 9 Aug 2023 04:23:12 +0000 (00:23 -0400)]
radv/video: use vk_video_derive_h264_scaling_list
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
Benjamin Cheng [Wed, 9 Aug 2023 04:19:27 +0000 (00:19 -0400)]
vulkan/video: add helper to derive H264 scaling lists
The H264 spec defines a complicated way of layering PPS scaling lists
on top of SPS scaling lists. The details can be found in 7.4.2.1
(seq_scaling_matrix_present_flag semantics) and 7.4.2.2
(pic_scaling_matrix_present_flag semantics).
Both ANV and RADV need to derive the final scaling lists sent to HW
using this logic in order to handle H264 scaling lists correctly.
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
Yiwei Zhang [Thu, 24 Aug 2023 21:56:02 +0000 (14:56 -0700)]
venus: add no_sparse debug option to disable sparse resource support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24877>
twisted89 [Tue, 8 Aug 2023 21:19:55 +0000 (22:19 +0100)]
util/driconf: add workarounds for the Chronicles of Riddick
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24567>
Mike Blumenkrantz [Thu, 24 Aug 2023 19:38:32 +0000 (15:38 -0400)]
zink: fix rewrite_read_as_0 filtering
Fixes:
9e42553ca8d ("zink: use lowered io (kinda) for i/o vars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24874>
Faith Ekstrand [Thu, 24 Aug 2023 16:56:35 +0000 (11:56 -0500)]
nouveau/mme: Fix a compile warning
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
Faith Ekstrand [Tue, 22 Aug 2023 23:12:10 +0000 (18:12 -0500)]
nvk: Plumb no_prefetch through to the DRM back-end
Instead of using bit 23 of nvk_cmd_push::range for this, pass it as a
separate bool. This lets us use the actual kernel flag with the new
UAPI.
Reviewed-by: Danilo Krummrich <dakr@redhat.com>
Tested-by: Danilo Krummrich <dakr@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
Faith Ekstrand [Tue, 22 Aug 2023 23:04:24 +0000 (18:04 -0500)]
drm-uapi: Sync nouveau_drm.h
From https://cgit.freedesktop.org/drm-misc/
commit
443f9e0b1ab5e3b95abf8606097d13e30e2f2413
Author: Danilo Krummrich <dakr@redhat.com>
Date: Wed Aug 23 20:15:34 2023 +0200
drm/nouveau: uapi: don't pass NO_PREFETCH flag implicitl
Reviewed-by: Danilo Krummrich <dakr@redhat.com>
Tested-by: Danilo Krummrich <dakr@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
Ian Romanick [Wed, 23 Aug 2023 19:53:56 +0000 (12:53 -0700)]
util/rb-tree: Fix typo in comment
Trivial.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24856>
Ian Romanick [Wed, 23 Aug 2023 19:08:21 +0000 (12:08 -0700)]
util/rb-tree: Return the actual first node from rb_tree_search
Previously rb_tree_search would return the first node encountered, but
that may not be the first node that would be encoutnered by, say,
rb_tree_foreach.
Two test cases are added.
v2: Add more curly braces. Suggested by Faith.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24856>
David Heidelberg [Thu, 24 Aug 2023 15:38:51 +0000 (17:38 +0200)]
ci/iris: add GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive timeout
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24870>
Dmitry Baryshkov [Thu, 24 Aug 2023 04:48:54 +0000 (07:48 +0300)]
tu: Pass real size of prime buffers to allocator
The msm driver reserves the actual DMABUF size in the memory map, while
TU can request smaller memory chunk to be allocated. This potentially
can lead to a situation when next allocation IOVA will be in the middle
of the address space which is reserved for the DMABUF. Pass the
`real_size' to TU allocator instead, so that kernel and userspace have
the same picture of memory allocations.
Cc: mesa-stable
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24861>
Alyssa Rosenzweig [Wed, 23 Aug 2023 16:53:26 +0000 (12:53 -0400)]
treewide: Also handle struct nir_builder form
Via Coccinelle patch:
@def@
typedef bool;
typedef nir_builder;
typedef nir_instr;
typedef nir_def;
identifier fn, instr, intr, x, builder, data;
@@
static fn(struct nir_builder* builder,
-nir_instr *instr,
+nir_intrinsic_instr *intr,
...)
{
(
- if (instr->type != nir_instr_type_intrinsic)
- return false;
- nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
|
- nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
- if (instr->type != nir_instr_type_intrinsic)
- return false;
)
<...
(
-instr->x
+intr->instr.x
|
-instr
+&intr->instr
)
...>
}
@pass depends on def@
identifier def.fn;
expression shader, progress;
@@
(
-nir_shader_instructions_pass(shader, fn,
+nir_shader_intrinsics_pass(shader, fn,
...)
|
-NIR_PASS_V(shader, nir_shader_instructions_pass, fn,
+NIR_PASS_V(shader, nir_shader_intrinsics_pass, fn,
...)
|
-NIR_PASS(progress, shader, nir_shader_instructions_pass, fn,
+NIR_PASS(progress, shader, nir_shader_intrinsics_pass, fn,
...)
)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24852>
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