spirv: add support for SpvCapabilityFragmentBarycentricKHR

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23254>

zink: update profiles schema

The 0.8.1-251 release has shipped, which contains the latest bits we
need in order to be clean here. Let's bump the bumpbump-bump.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23342>

draw: add (disabled) vertex dumping for non-linear emit

matches linear path

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23368>

lavapipe: don't pass indirect info in streamout draws

this is otherwise broken for a sequence like draw_indirect -> draw_indirect_bc

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23368>

lavapipe: stop setting patch vertices constantly

this pollutes gallium traces and makes debugging more annoying

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23368>

lavapipe: bump max push constant size

this matches vkd3d-proton requirements

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23368>

lavapipe: fix DS3 min sample setting

if a DS3 pipeline enabling dynamic samples is not bound when samples
are set dynamically, then such a pipeline is later bound, min samples
would have been incorrectly set to 1

instead, flag the update for later and do it just before draw

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23368>

radv: Guard against misplaced RGP barrier markers.

RGP will crash if we emit a layout transition marker outside a barrier.
If this happens, trigger an assertion if its enabled or silently discard
the marker otherwise to avoid traces that cannot be opened.

Also, guard against attempts to start barrier markers recursively, since
this will corrupt the internal start/end matching.

Closes: <https://gitlab.freedesktop.org/mesa/mesa/-/issues/7971>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21033>

radv: Add RGP barrier markers for render pass transition and copy.

This allows them to be attributed to the correct event instead of being
blend to the previous barrier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21033>

radeonsi: enable aco for mono standalone vs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm: remove unused barrier implementation

memory buffer barrier is still used when nir lowering, will
be removed later.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

radeonsi: always use scoped barrier

aco has removed non-scoped barrier support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

radeonsi: use nir_umul_high for fast udiv

nir has dedicated alu op for it. Also for removing int64
multiply which aco does not support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

radeonsi: calculate needed lds size when upload raw binary for vs

ELF do the same when upload binary. We can't do this when
compile, because it's know when draw time in radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

radeonsi: fill aco shader info for mono standalone vs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

nir,ac/llvm,radeonsi: replace nir_buffer_atomic_add_amd with ssbo atomic

Now that radeonsi support pass desc to ssbo atomic ops,
we can use ssbo atomic instead. aco does not implement
nir_buffer_atomic_add either.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower nir_load_ring_esgs_amd in abi

It's not implemented by aco. So move the code from llvm
to nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower nir_load_ordered_id_amd in abi

aco does not implement it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower nir_load_packed_passthrough_primitive_amd in abi

aco does not implement it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower nir_load_initial_edgeflags_amd in abi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower load_workgroup_num_input_(vertices|primitives) in abi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower nir_load_merged_wave_info_amd in abi

aco does not implement it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

ac/llvm,radeonsi: lower nir_load_gs_vertex_offset_amd in abi

aco does not implement this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

radeonsi: add scratch offset vs args explicitly for aco

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

radeonsi: resolve lds ngg aco symbols

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23096>

aco: use ac_get_image_dim for array check when image intrinsic

This is to avoid missing array flag when <=GFX8 and 3D image
in which case is treated as 2D array image.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco: implement nir_bindless_image_fragment_mask_load_amd

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco: implement nir_xfb_counter_sub_amd

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco: use gds reg when ordered xfb counter add

This is currently only used by radeonsi.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco/assembler: handle ds_(add|sub)_gs_reg_rtn encoding

They are different than normal DS instructions, only
use DATA[0], not use ADDR.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco: implement load buffer with ACCESS_USES_FORMAT_AMD

This is used by radeonsi for vs input load and cdna
image load emulation.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

ac/nir/ngg: don't use 8bit alu ops

aco doesn't support 8bit alu ops and radeonsi won't
call nir_lower_bit_size for most alu ops, so just
don't use 8bit alu ops (they will be lowered to 32bit
anyway if we do).

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco,radv: remove unused aco_shader_info fields

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

aco: implement two load lds ngg intrininsic for radeonsi

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>

ci/turnip: Update full-run xfails.

The big pile of crashes were all either not covered by the fractional run
and a full run hadn't been run to update them, or unsupported where
Crash->Skip is not being reported as UnexpectedPass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23385>

ci: Respect $HTTP_PROXY for ci_run_n_monitor

We need to explicitly tell AIOHTTP that it's OK to take the HTTP proxy
from the environment.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23341>

ci/crocus: Add a missing xfail.

Probably more fallout from debian 12 uprev.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23379>

crocus: Fix regression from !20153

The MR fixed iris in 14dec0c1479aa149edead1e95b7feb1669ccc4c1, but didn't
do the same fix for crocus.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23379>

Revert "ci: disable anholt's farm"

Things are back up.  This reverts commit
520c5091d7de4290f87bb984a59e7ac2993471a4.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23381>

ci/freedreno: Update minetest hash.

1 different pixel, undetectable change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Use shared NIR code for ARB_vp and FF VS position transformation.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa/ffvs: Fix mvp_with_dp4 position transformation.

Copy and paste mistake, but didn't affect anybody since this knob is
disconnected at the moment.

Fixes: c5b3d488f9be ("mesa/main: make ffvertex output nir")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Use the NIR pass for fixed function fog.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa/ati_fs: Move prog->SamplersUsed/TexturesUsed setup to EndFragmentShader.

No need to have st_program.c come back into ATI_fs for this when it's a
property of program generation.  ARB programs set these up in their
translation, as well.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa/ati_fs: Move NIR translation to ATI_fs compile time.

Now ati_fs takes the same basic path as prog_to_nir, and we don't have to
think about it so much.  Also, the ATI_fs frontend can skip shader info
setup since nir_shader_gather_info does it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa/ati_fs: Move sampler dim adjustment to a separate NIR pass.

This means that the main NIR translation for ATI_fs is now independent of
the fp key, and we could do it earlier in the compile pipeline.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Move st_prog_to_nir_postprocess out of prog_to_nir.

We called it in the else branch, anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Drop remaining unused ARB program instructions.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Drop unused control flow instructions for ARB programs.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Drop ARB program helper functions that are no longer used.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Move ARB_vp position invariant option handling to NIR.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa/ARB_fp: Use the NIR pass for adding fog code instead of ARB instrs.

Tested with
https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/813

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa/ARB_fp: Drop an extra enum for fog mode.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Move ATI_fragment_shader fog code emit to a NIR lowering pass.

Now it's implemented as a RMW of the FRAG_RESULT_COLOR output var (or
adjusting the store_output intrinsic's value for lowered i/o), which
should be reusable other places we might want to emit shader code for fog
(ARB_fp, fixed function fragment shaders).

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

nir,mesa: Add helpers for creating uniform state variables.

It's one of the weirder parts of our shader interface's interactions with
the GL API, so let's try to make it a little cleaner.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

nir: Use find_state_var in lower_atomics_to_ssbo.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

mesa: Use find_state_var in lower_builtin.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23111>

d3d12: Support PIPE_CAP_VS_LAYER_VIEWPORT

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23377>

microsoft/compiler: Viewport/layer as input to GS/HS needs to set feature bit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23377>

microsoft/compiler: Fix usage of type var in semantic asserts

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23377>

microsoft/compiler: Fix the int->uint pass for arrayed I/O

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23377>

dzn: Don't lower away mediump

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23344>

spirv2dxil: Enable mediump

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23344>

microsoft/compiler: Handle mediump

Instead of treating all 16-bit values as "native 16-bit types,"
differentiate between concrete casts and mediump casts, where the
former requires native 16-bit types, and the latter only requires
DXIL min-precision. Additionally, UBO/SSBO loads/stores require
native 16-bit types.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23344>

microsoft/compiler: Always set support_16bit_alu

This just affects some nir opts. If we're lowering 16bit ops anyway,
the optimization doesn't matter.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23344>

nir: Add preserve_mediump as a shader compiler option

The DXIL backend would like to distinguish between casts to 16-bit
that must cast, vs those that may. If a shader only ever produces
16-bit types from mediump casts and ALU ops on those values, then
the resulting shader can be annotated with DXIL's min-precision
qualifier, basically telling the driver to use 16-bit precision if
it's faster for them. If it uses concrete 16-bit casts, or loads/
stores to externally-visible memory, then it must use the "native"
16-bit flag, which is not supported on all hardware.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23344>

zink: Use PIPE_CAP_FS_POINT_IS_SYSVAL.

This better matches up to how spirv treats the value.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22950>

nir/lower_texcoord_replace: Flag SYSTEM_VALUE_POINT_COORD read when we load it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22950>

glsl: Allow invariant flags on sysvals, such as gl_PointCoord.

When you set PIPE_CAP_FS_POINT_IS_SYSVAL, we'd fall out of
is_allowed_invariant(), despite it being allowed on special builtins.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22950>

gallium/nir/tgsi: add various support for task/mesh bits

these translators are used by llvmpipe so need to be updated

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

gallium/cso: add task/mesh shaders to the cso cache

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

d3d12: don't report mesh/task limits

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

svga: don't report mesh/task shader limits

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

radeonsi: don't report shader params for task/mesh

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

crocus: don't report mesh/task limits

Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

iris: don't return shader params for task/mesh.

These should be reported as 0 for cso

Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

gallium: add task/mesh shader entrypoints in context

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

freedreno: don't report task/mesh.

Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

gallium: add a new PIPE_SHADER_MESH_TYPES

This adds a new limit, changing PIPE_SHADER_TYPES seems frought
with danger and very tricky. Currently only lava/llvmpipe plan to
offer task/mesh in GL land, so let's limit the fallout for now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

gallium: expand pipe_grid_info to handle task/mesh.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

gallium: add task/mesh shader query types to stats interface.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23291>

rusticl/device: limit MAX_PARAMETER_SIZE to 32k

There is no good reason of having it too big and radeonsi returns an
absurd high value through PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE.

This speeds up the CTS testing this device limit.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23378>

intel/compiler: Fix a fallthrough in components_read() for atomics

In commit 284f0c9a57e17b14c044c04c7cf9ae77d6694492 I refactored the
handling of the data source to just call a helper rather than special
casing opcodes with 0 or 2 sources.  Unfortunately, I also dropped the
"else return 1", creating a fallthrough for all sources other than
SURFACE_LOGICAL_SRC_ADDRESS and SURFACE_LOGICAL_SRC_DATA.

The case below happened to return the correct value for all cases except
SURFACE_LOGICAL_SRC_SURFACE, which has been returning 2 instead of 1
since that commit.

Restore the else case.  Thanks to Marcin Ślusarz for catching this.

Fixes: 284f0c9a57e1 ("intel/compiler: Add an lsc_op_num_data_values() helper")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23347>

freedreno/a6xx: Enable gl46

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: GL_ARB_pipeline_statistics_query

Handle the other pipeline stats counters in order to implement
GL_ARB_pipeline_statistics_query.  Note that this does away with
collecting *all* the counters if DEBUG_COUNTERS is enabled, other-
wise it was getting over-complicated.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno: Handle compute queries

Compute stage can have queries too.  We need to handle that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Handle nested pipeline stats queries

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Split primitives and pipeline-stats queries

They are really two completely different things.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: GL_ARB_transform_feedback_overflow_query

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Remove primitives_relocw()

These days we don't track read vs write relocs, so it is the same thing
as primitives_reloc()

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Fix xfb stream configuration

Also, only emit PC_SO_STREAM_CNTL for tess shaders, to align with how
turnip does it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Add missing cap

Fixes wrong value reported for GL_MAX_VERTEX_STREAMS.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Stop using fd_wfi()

This was originally intended for earlier gens where certain draw-time
state needed a WFI (because it wasn't banked, etc).  This isn't the case
on a6xx.  So just directly emit WFIs where they are needed.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

freedreno/a6xx: Clean up open coded flushes

Migrate more code to fd6_emit_flushes().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23301>

aco: p_start_linear_vgpr doesn't always need exec mask

Foz-DB Navi21:
Totals from 1605 (1.21% of 132657) affected shaders:
CodeSize: 14023700 -> 14020320 (-0.02%)
Instrs: 2589881 -> 2589052 (-0.03%)
Latency: 22478420 -> 22473359 (-0.02%)
InvThroughput: 3851237 -> 3851092 (-0.00%)
Copies: 215316 -> 215438 (+0.06%); split: -0.39%, +0.44%

Allows more vcmpx usage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23302>

intel/fs: fix a couple of descriptor mistakes

I found those issues while testing DOOM eternal and Ian also ran into
it with other shaders.

We write the desc register in SIMD1 exec_all, so all the data is in
the first component. We need to make sure to pass that component in
the lower SEND instructions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23354>

radv: allow wave32 for geometry shaders

Because is_ngg wasn't set early enough, radv_get_wave_size() would always
return 64.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23336>

ac/surface: relax custom pitch requirements to any multiple of 256B on gfx10.3+

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23015>

radv: implement setting a custom pitch to any multiple of 256B on gfx10.3+

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23015>

radeonsi: implement setting a custom pitch to any multiple of 256B on gfx10.3+

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23015>