Homer Hsing [Fri, 14 Sep 2012 00:20:13 +0000 (08:20 +0800)]
Supporting addc instruction
The addc instruction performs component-wise addition of
src0 and src1 and stores the results in dst;
it also stores the carry into acc.
Homer Hsing [Thu, 13 Sep 2012 03:05:50 +0000 (11:05 +0800)]
Supporting bit field extract and bit field insert 2
Supporting two new operators, bfe and bfi2
bfe: Component-wise extracts a bit field from src2 using the bit field width from src0 and the bit field offset from src1.
bfi2: component-wise performs the bitfield insert operation on src1 and src2 based on the mask in src0.
Homer Hsing [Wed, 12 Sep 2012 05:04:49 +0000 (13:04 +0800)]
Supporting LRP: dest = src0 * src1 + (1-src0) * src2
Homer Hsing [Fri, 7 Sep 2012 06:38:13 +0000 (14:38 +0800)]
Support trinary source instruction "multiply add".
MAD (Multiply ADd) computes dst <- src1*src2 + src0.
Tried best to follow previous variable naming habit.
Also renamed "triinstruction" -> "trinaryinstruction" in grammar parser
for better readability.
Homer Hsing [Fri, 7 Sep 2012 01:53:17 +0000 (09:53 +0800)]
add data structure in src/brw_structs.h for supporting three-source-operator instruncions
Homer Hsing [Fri, 7 Sep 2012 01:20:50 +0000 (09:20 +0800)]
Comment magic words "da1", "da16", "ia1", and "ia16"
Homer Hsing [Thu, 6 Sep 2012 08:12:08 +0000 (16:12 +0800)]
close File yyin before calling yylex_destroy
This patch makes sure file handler yyin is closed.
yylex_destroy() calls yy_init_globals(), which reset yyin to 0.
Therefore if we do not close yyin before yylex_destroy(), yyin
will not be closed anymore.
Homer Hsing [Thu, 6 Sep 2012 07:55:54 +0000 (15:55 +0800)]
Call yylex_destroy() to free memory after yyparse()
Homer Hsing [Thu, 6 Sep 2012 07:33:41 +0000 (15:33 +0800)]
Close input file handler yyin after yyparse
Homer Hsing [Thu, 6 Sep 2012 02:31:22 +0000 (10:31 +0800)]
Fix a typo ... lable -> label
Lu Guanqun [Wed, 22 Aug 2012 01:09:36 +0000 (09:09 +0800)]
fix the label checking logics
Signed-off-by: Lu Guanqun <guanqun.lu@intel.com>
Xiang, Haihao [Tue, 17 Jul 2012 08:16:11 +0000 (16:16 +0800)]
Waring if both predication and conditional modifier are enabled but use different flag registers
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 17 Jul 2012 07:05:31 +0000 (15:05 +0800)]
Add support for flag register f1 on Ivy bridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 17 Jul 2012 06:18:54 +0000 (14:18 +0800)]
s/flag_reg_nr/flag_subreg_nr for an instruction
s/flagreg/flag_subreg_nr for a condition
They are flag subregister number indeed
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 17 Jul 2012 06:01:54 +0000 (14:01 +0800)]
Remove flag_reg_nr from the DW3 of an instruction
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 17 Jul 2012 05:46:59 +0000 (13:46 +0800)]
Change the rule for flag register
The shift/reduce conflict mentioned in the comment has been fixed, so
flagreg can return the reg number in the lvalue now. In addition, it will
be easy to add support for flag register f1 on Ivy bridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 29 Jun 2012 08:47:10 +0000 (16:47 +0800)]
Accept symbol register as the leading register of the request
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Ben Widawsky [Sun, 24 Jun 2012 22:03:28 +0000 (15:03 -0700)]
disasm: decode SENDC like SEND
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Sun, 24 Jun 2012 22:01:57 +0000 (15:01 -0700)]
disasm: add gen6 style send decoding
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Sun, 24 Jun 2012 21:43:45 +0000 (14:43 -0700)]
disasm: add sendc
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Sun, 24 Jun 2012 02:36:48 +0000 (19:36 -0700)]
disasm: add pln instruction
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Xiang, Haihao [Thu, 11 Aug 2011 07:35:14 +0000 (15:35 +0800)]
A new syntax of SEND intruction on Ivybridge
[(<pred>)] send (<exec_size>) reg greg imm6 reg32a
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 21 Jun 2011 03:12:13 +0000 (11:12 +0800)]
bump version to 1.2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 31 May 2011 05:36:03 +0000 (13:36 +0800)]
Support VME on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 10 Jun 2011 08:04:30 +0000 (16:04 +0800)]
Support DP for sampler/render/constant/data cache
Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.
data_port(
cache_type, /* sampler, render, constant or data(on Ivybridge+) cache */
message_type, /* read or write type */
message_control,
binding_table_index,
write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
header_present)
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 May 2011 08:30:48 +0000 (16:30 +0800)]
sampler/render/constant cache unit since Sandybridge
since Sandybrdige, there isn't a single function unit for data port read/write.
Instead sampler/render/constant cache unit is introduced, data port read/write
can be specified in a SEND instruction with different cache unit. To keep compatibility,
currently data port read always uses sampler cache unit however data port write
uses render cache unit
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 May 2011 08:00:12 +0000 (16:00 +0800)]
fix an error in commit cf76278
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 25 May 2011 06:29:14 +0000 (14:29 +0800)]
SEND uses GRFs instead of MRFs on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 23 May 2011 05:45:04 +0000 (13:45 +0800)]
Add support for sample (00000) on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 23 May 2011 05:32:32 +0000 (13:32 +0800)]
Add support for data port read/write on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 23 May 2011 04:43:25 +0000 (12:43 +0800)]
Add -g 7 for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Feng, Boqun [Tue, 19 Apr 2011 00:43:22 +0000 (08:43 +0800)]
Send instruction on PRE-ILK
[(<pred>)] send (<exec_size>) <pdst> <cdst> <src0> <desc>
Zhou Chang [Thu, 14 Apr 2011 03:51:29 +0000 (11:51 +0800)]
Add VME support in SEND
Ben Widawsky [Thu, 24 Mar 2011 05:08:39 +0000 (22:08 -0700)]
intel-gen4asm: add byte array style disasm
I previously added a byte array style output for intel-gen4asm, but
there was no way to disassemble here. Well here that is.
Ben Widawsky [Fri, 18 Mar 2011 01:57:59 +0000 (18:57 -0700)]
intel-gen4asm: have a C-like binary output
Have the assembler support a byte array output. This is useful for
writing blobs which can directly be linked code that wishes to upload to
the EU.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Xiang, Haihao [Tue, 1 Mar 2011 08:43:02 +0000 (16:43 +0800)]
fix the parameters of register region
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 17 Feb 2011 05:24:11 +0000 (13:24 +0800)]
send instruction on GEN6
[(<pred>)] send (<exec_size>) reg mreg imm6 imm32
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 16 Feb 2011 07:26:24 +0000 (15:26 +0800)]
fix notification count register
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 13 Dec 2010 08:07:16 +0000 (16:07 +0800)]
Support instructions which strictly follow the documents.
Previously some instructions parsed by this assembler don't follow the
documents.
Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu <haofu.han@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Chen, Yangyang [Mon, 13 Dec 2010 07:36:02 +0000 (15:36 +0800)]
1. fix DOT
2. rule for instrseq
Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu <haofu.han@intel.com>
Chen, Yangyang [Mon, 13 Dec 2010 07:30:48 +0000 (15:30 +0800)]
fix CHANNEL select
Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu <haofu.han@intel.com>
Xiang, Haihao [Mon, 1 Nov 2010 08:16:25 +0000 (16:16 +0800)]
Support for headerless write
Add a new parameter to write
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 21 Oct 2010 06:37:18 +0000 (14:37 +0800)]
bump version to 1.1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 27 Oct 2010 01:42:56 +0000 (09:42 +0800)]
add support for math instruction on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 19 Oct 2010 05:26:24 +0000 (13:26 +0800)]
add support for plane instruction (pln)
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 21 Oct 2010 06:33:35 +0000 (14:33 +0800)]
Send on Sandybridge uses a message register as operand src0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Sat, 9 Oct 2010 05:57:48 +0000 (13:57 +0800)]
no compression flag on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Sat, 9 Oct 2010 04:52:08 +0000 (12:52 +0800)]
print error message when using math function on Sandybridge.
Sandybridge doesn't have math funtion, instead it supports a set of math
instructions. The support for math instructions will be added later.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Sat, 9 Oct 2010 04:46:15 +0000 (12:46 +0800)]
sampler, urb write, null and gateway on Sandybridge are same as Ironlake.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Sat, 9 Oct 2010 03:09:47 +0000 (11:09 +0800)]
add support for data port read on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Oct 2010 08:48:15 +0000 (16:48 +0800)]
add support for data port write on Sandybridge.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Oct 2010 07:07:51 +0000 (15:07 +0800)]
fix send instruction on Sandybridge
Send doesn't have implied move on Sandybridge, the SFID moves to bits[24,27] which
is used as the destination of the implied move on Prev GEN6.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Oct 2010 05:53:22 +0000 (13:53 +0800)]
add AccWrCtrl flag on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Oct 2010 05:10:15 +0000 (13:10 +0800)]
always set destination horiz stride for Align16 to 1 on Sandybridge.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Oct 2010 04:53:38 +0000 (12:53 +0800)]
fix jump count for Sandybridge.
It is same as Ironlake.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Oct 2010 04:52:34 +0000 (12:52 +0800)]
add -g 6 for Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zou Nan hai [Wed, 21 Apr 2010 03:02:21 +0000 (11:02 +0800)]
use left recursion instead of right recursion to avoid memory exhausted issue when compiling large source files
Eric Anholt [Wed, 23 Dec 2009 01:06:47 +0000 (17:06 -0800)]
Fix setup of immediate types for gen4 disasm.
Caught by clang.
Eric Anholt [Tue, 4 Aug 2009 23:27:28 +0000 (16:27 -0700)]
disasm: Print out ELSE and ENDIF src1 arguments like IF does.
Eric Anholt [Tue, 4 Aug 2009 22:02:12 +0000 (15:02 -0700)]
whitespace cleanup from Mesa import.
Zou Nan hai [Wed, 28 Oct 2009 02:14:19 +0000 (10:14 +0800)]
1. type syntax :ud :uw etc
2. empty instruction option
3. remove a conflict
Zou Nan hai [Tue, 20 Oct 2009 06:51:04 +0000 (14:51 +0800)]
support simple expression
Xiang, Haihao [Thu, 23 Jul 2009 02:43:27 +0000 (10:43 +0800)]
add intel-gen4asm.pc.in
bump version to 1.0
Xiang, Haihao [Thu, 23 Jul 2009 02:33:55 +0000 (10:33 +0800)]
the offset of JMPI is in unit of 64bits on GEN5.
This fix is only applied for JMPI label. It is up to you
to use a right offset for JMPI imm32|reg in your program.
Xiang, Haihao [Thu, 23 Jul 2009 02:32:51 +0000 (10:32 +0800)]
change read message format on GEN5
to re-use a lot of shaders for GEN5.
Xiang Haihao [Tue, 30 Jun 2009 02:02:33 +0000 (10:02 +0800)]
Add support for GEN5
Add a new option [-g n], n=4(GEN4),5(GEN5). If don't use -g,
the default value is 4(GEN4)
Zou Nanhai [Wed, 10 Dec 2008 02:38:54 +0000 (18:38 -0800)]
Add support for labeled and conditional branches
Signed-off-by: Keith Packard <keithp@keithp.com>
Keith Packard [Sun, 19 Oct 2008 03:07:45 +0000 (20:07 -0700)]
Support more addressing modes in disasm
Eric Anholt [Wed, 18 Jun 2008 22:09:30 +0000 (15:09 -0700)]
Fix compiler warning from missing include.
Zou Nan hai [Wed, 18 Jun 2008 22:05:19 +0000 (15:05 -0700)]
Add support for dp_read message.
Zou Nan hai [Wed, 18 Jun 2008 22:04:11 +0000 (15:04 -0700)]
Add thread_spawner message target support.
Keith Packard [Thu, 24 Apr 2008 06:10:40 +0000 (23:10 -0700)]
Add conditional support to assembler. Add align16 dest support to disasm.
This is working towards round-tripping mesa programs. Still need indirect
register addressing and align16 source support.
Keith Packard [Thu, 24 Apr 2008 02:28:23 +0000 (19:28 -0700)]
Add math and urb units, deal with nop
Keith Packard [Wed, 23 Apr 2008 19:52:58 +0000 (12:52 -0700)]
Add disassembler (intel-gen4disasm).
Decodes most simple instructions. Still needs work on branching and send.
Keith Packard [Fri, 11 Apr 2008 18:04:42 +0000 (11:04 -0700)]
Support #line directives
Keith Packard [Sun, 30 Mar 2008 07:58:40 +0000 (00:58 -0700)]
Ensure that parse errors cause non-zero exit.
Also, avoid creating output file when a parse error occurs
Keith Packard [Sun, 30 Mar 2008 07:58:28 +0000 (00:58 -0700)]
Add packed vector immediate values
Keith Packard [Sun, 30 Mar 2008 07:57:40 +0000 (00:57 -0700)]
Add GCC warnings
Eric Anholt [Fri, 1 Sep 2006 23:19:04 +0000 (16:19 -0700)]
Add accidentally forgotten rnde test.
Eric Anholt [Fri, 1 Sep 2006 23:18:06 +0000 (16:18 -0700)]
More renaming of gen4asm -> intel-gen4asm, plus README update.
Eric Anholt [Fri, 1 Sep 2006 22:54:54 +0000 (15:54 -0700)]
Update .gitignore for gen4asm -> intel-gen4asm
Eric Anholt [Fri, 1 Sep 2006 22:40:57 +0000 (15:40 -0700)]
Rename package and binary to intel-gen4asm.
Eric Anholt [Fri, 1 Sep 2006 22:38:37 +0000 (15:38 -0700)]
Use 0 instead of INITIAL, as the chosen lex on my debian doesn't supply it.
Eric Anholt [Fri, 1 Sep 2006 22:37:00 +0000 (15:37 -0700)]
Use inttypes.h to get at uint32_t instead of sys/types.h.
Eric Anholt [Fri, 1 Sep 2006 20:57:02 +0000 (13:57 -0700)]
Update the TODO with more tasks and a bit more description.
Eric Anholt [Fri, 1 Sep 2006 20:37:51 +0000 (13:37 -0700)]
Add break, cont, and halt instructions.
Eric Anholt [Fri, 1 Sep 2006 20:37:07 +0000 (13:37 -0700)]
Add tests for break, cont, and halt instructions.
Eric Anholt [Fri, 1 Sep 2006 19:29:23 +0000 (12:29 -0700)]
Fix the exitcode type for ENDIF to be D instead of UD.
Fixes the endif test.
Eric Anholt [Fri, 1 Sep 2006 19:25:22 +0000 (12:25 -0700)]
Add a test for ENDIF, revealing issues.
Eric Anholt [Fri, 1 Sep 2006 19:11:55 +0000 (12:11 -0700)]
Fix initialization of null reg for ELSE, and set the pop count right.
This fixes the ELSE test.
Eric Anholt [Fri, 1 Sep 2006 19:11:24 +0000 (12:11 -0700)]
Add a test for the ELSE instruction, revealing issues.
Eric Anholt [Fri, 1 Sep 2006 18:56:12 +0000 (11:56 -0700)]
Add support for the WAIT instruction.
Eric Anholt [Fri, 1 Sep 2006 18:55:22 +0000 (11:55 -0700)]
Add a test for wait instruction (not yet implemented).
Eric Anholt [Thu, 31 Aug 2006 23:19:08 +0000 (16:19 -0700)]
Lex integers as unsigned long instead of signed int, fixing the immediate test.
Eric Anholt [Thu, 31 Aug 2006 23:16:06 +0000 (16:16 -0700)]
Add a failing test for maximum ranges of UD/D immediates.
Eric Anholt [Thu, 31 Aug 2006 22:59:14 +0000 (15:59 -0700)]
Parse negative integers for imm32s, and don't exceed the IP count width field.
This fixes the while test.
Eric Anholt [Thu, 31 Aug 2006 22:57:35 +0000 (15:57 -0700)]
Fix the width of the IP count field expected by the while test.
Eric Anholt [Thu, 31 Aug 2006 22:53:53 +0000 (15:53 -0700)]
Fix copy'n'paste-o in lexing of the WHILE instruction.
Eric Anholt [Thu, 31 Aug 2006 22:28:10 +0000 (15:28 -0700)]
Initialize the structure used for setting up the ip src/dst in branches/jumps.
This fixes jmpi, if, and iff. The while test still fails to compile.
Eric Anholt [Thu, 31 Aug 2006 22:27:30 +0000 (15:27 -0700)]
Add tests for jmpi, if, iff, and while, revealing issues.