aco: allow Builder::Result to be dereferenced

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>

aco/gfx11: fix discard early exit removal optimization

This optimization never happened because the NULL target was removed in
GFX11.

fossil-db (gfx1100):
Totals from 5439 (4.04% of 134574) affected shaders:
Instrs: 407865 -> 387123 (-5.09%)
CodeSize: 2163340 -> 2060644 (-4.75%)
Latency: 3432378 -> 3327802 (-3.05%)
InvThroughput: 270133 -> 262980 (-2.65%)
Branches: 8524 -> 3085 (-63.81%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20513>

microsoft/spirv_to_dxil: Let linking report the need of runtime data

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20608>

etnaviv: properly check for new clear value in sampler TS setup

Comparing the 64bit clear value to the lower half 32bit clear state is
obviously wrong and results in a lot of false positives.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20586>

etnaviv: blt: properly use upper half of clear value

Instead of replicating the lower half of the clear value, properly
use the upper half to program the second clear value BLT state.

CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20586>

ir3/print: Consider the size of input when matching it to a reg

First component of the input may never be read, so we have to find
the first component of the input which is being read.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20533>

ir3: Force flat.b sources to be equal

From cc29b940 according to Jonathan Marek using 2 immediates in a cat2
instruction is only "correct" if they are both equal.

They were not equal after reassigning of packed inlocks.

flat.b seemed to work fine even with imm values being different,
but better not to risk.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20533>

tu: Fix varyings interpolation reading stale values

tu6_vpc_varying_mode returned how many bits are consumed IF they are
non-zero, for SMOOTH mode nothing is written and it was treated like
no bits were consumed.

When input with smooth interpolation was the last one and straddled
the VPC_VARYING_INTERP_MODE regs, the last interp mode were not written.

Fixes misrendering in "Psychonauts 2".

Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20533>

loader/dri3: Overhaul draw->cur_num_back handling

draw->cur_num_back is no longer used for immediately reducing the number
of allocated back buffers. It just reflects how many of them are
currently allocated, and is used to prevent allocating more if the
current maximum is already reached.

This fixes an issue where the current in-progress back buffer could get
freed, which would result in visible artifacts.

Unused buffers are freed once they exceed buffer age 200. This ensures
we do not keep around more buffers than necessary in the long run.

v2:
* Drop buffer age threshold to 200. This will free unused buffers more
  quickly, and seems enough to avoid doing so prematurely even with
  "glxgears -fullscreen" running at thousands of frames per second.
* Use "buf_id != LOADER_DRI3_FRONT_ID". (Pierre-Eric Pelloux-Prayer)
* Simplify loader_dri3_get_buffers changes slightly.
* We can now use any unallocated back buffer slot in dri3_find_back.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20385>

loader/dri3: Add dri3_set_render_buffer helper

Preparation for next commit, no functional change intended.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20385>

loader/dri3: Move NULL handling into dri3_free_render_buffer

Both checking for draw->buffers[buf_id] being non-NULL, and setting
draw->buffers[buf_id] = NULL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20385>

radv: enable PS epilogs on-demand for some dynamic states

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

radv: add support for compiling PS epilogs on-demand

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

radv: copy the non-compacted color format at pipeline bind time

For PS epilogs on-demand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

radv: rework PS epilog emission

With PS epilogs compiled on-demand (for some dynamic states), they need
to be emitted outside of the graphics pipeline path. Also keep track
of the last emitted PS epilog to avoid redundant emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

radv: keep track of SPI_SHADER_COL_FORMAT for PS epilogs

To emit the related register.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

radv: enable the PS epilogs cache when some ds3 states are enabled

These dynamic states need to compile PS epilogs on-demand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

radv: add support for a PS epilogs cache in the device

Similar to VS prologs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>

ci/rpi4: add a couple of tests as flaky

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20591>

ci/rpi3: add another test variant (draw-copypixels-sync) as flaky

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20591>

gallium/draw: assert shader-stage

Nobody calls this for the wrong shader-stage. Let's turn that check into
an assert instead.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20096>

gallium/draw: use nir_shader_instructions_pass for nir_lower_aaline_fs

This just cuts away some needless boilerplate code.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20096>

radv: add a new dirty flag for the RB+ state

With PS epilogs on-demand, the non-compacted color format field won't
come from the pipeline and it seems easier to introduce a new dirty
flag for re-emitting this state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18552>

lvp: avoid redundant sampler views and image views

Align the sampler view creation condition with the image and buffer
creation usage which maps to PIPE_BIND_SAMPLER_VIEW, which fixes the spam
of "Illegal sampler view creation without bind flag". Also fix the
PIPE_BIND_SHADER_IMAGE assignment for image usage bits and avoid setting
the image view struct if without PIPE_BIND_SHADER_IMAGE.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20580>

zink: stop using VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT

this used to be fine back when there was only one thread doing cache management,
but now the cache is used by precompile threads too, so let the driver do sync

fixes #7660

Fixes: 41ffb15de56 ("zink: implement async gfx precompile")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20519>

agx: Remove obsolete comment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>

agx: Remove dead arg

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>

agx: Use i0/i1 variables

Now that we've defined them.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>

agx: Get rid of emit_alu_bool

Deduplicate lots of cases. Splitting this out was silly, bools aren't that
special.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>

agx: Use agx_subdivide_to for umul_high

Helpers!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>

agx: Remove dead code

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>

docs/envvars: Document MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ

Add documentation for the MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ environment
variable.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Juston Li <justonli@google.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20595>

util/disk_cache: Fix rw cache lookup when using combined ro+rw caches

When combining of ro+rw caches is enabled, at first the ro cache should be
looked up and if data isn't found there then rw cache should be checked.
The rw cache checking got lost by accident after the code rebase and there
was no unit test covering this condition. Fix the rw cache looking up and
add the unit test case.

Fixes: 32fe60e8c429 ("util/disk_cache: Support combined foz ro and non-foz rw caches")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Juston Li <justonli@google.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20595>

dzn: No need to add another bind flag for clears if one is already present

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

dzn: Lower tg4 offsets

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

dzn: Implement point coord

Since we don't support wide points, this isn't a useful feature, but the CTS
requires a particular point coord value for the single rasterized pixel, based
on where the original point coord fell within the pixel. Since we're not doing
a quad, we don't get free interpolation like the GL driver does, so split the
logic between vertex (transform point center into screen space) and pixel
(compute delta between current pixel/sample and point center).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

dzn: Lower fragcoord wtrans

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

dzn: Use the right variable for heap slots when prepping resolves

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

microsoft/compiler: Set the advanced texture ops flag correctly

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

microsoft/compiler: Fill out and sort the shader/module flags

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

microsoft/compiler: For Vulkan, centroid should be ignored on position

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

microsoft/compiler: For Vulkan, when shading at sample rate, pos is sample pos

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

nir_lower_fragcoord_wtrans: Support Vulkan shaders

In Vulkan shaders, you might not have all derefs pointing to a variable

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>

util/driconf: add Dune: Spice Wars workaround

As per the bug report the game does not correctly handle a uniform
index of -1 being returned for the unused array element, which
results in rendering issues. So here we skip the uniform array
resizing optimisation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6397
Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20579>

d3d12: Update hard-coded heap sizes and batch limit

Increasing the heap sizes and active batch count reduces flushing
churn when rendering runs out of descriptors.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20589>

Return 'Mesa' for GL_VENDOR for community drivers

Rather than a grab-bag of random values, return 'Mesa' as the GL_VENDOR
string for all community-supported drivers.

Drivers which are primarily developed/maintained by the hardware vendor
retain that vendor's name as the GL_VENDOR string.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16064>

zink: fix the stencil write

Stencil writing also needs to be considered when setting the flag renderpass

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20245>

zink: add a condition to needs_write_s

Previously missing check on the stencil write, condition added to needs_write_s using util_writes_stencil

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20245>

lavapipe: add some safety asserts when beginning rendering

if the render area exceeds the attachment size, this is not only illegal,
it will crash later

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20583>

zink: add a fs base key, fix optimal fs key packing

the optimal fs key gets at most 16 bits, so it's crucial to only use
the ones that are needed in order to conserve bits for things needed
by all drivers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: use optimal key for pipeline library hash

this doesn't really change anything other than making the set collide less

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: unify some shadow tex code in match_tex_dests_instr()

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: fix some weird indentation in zink_set_sampler_views

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: simplify some depth texturing spv

the special-casing here is no longer necessary since multi-component
depth sample ops have already been rewritten by this point

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: put line emulation stuff behind optimal_keys check in draw

these parts of the shader key can't be accessed in optimal_keys mode

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: only flag modules_changed in optimal path if a change has occurred

this should save some cycles when a recalc is a no-op

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

zink: delete dead code

update_gfx_program_optimal() is the real version of this

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20585>

meson/zink: use vk_api_xml variable instead of re-constructing the file path

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20568>

asahi: Fix segfault with null drawbuffer

Fixes fbo-drawbuffers-none piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20569>

agx: Fix missing #include

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20569>

asahi: Implement ARB_texture_mirror_clamp_to_edge

Guessing the enum value, passes texwrap piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20560>

asahi: Implement GL_CLAMP natively

Turns out there's a hardware mode for this. Apple's GL driver uses this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20560>

ci/zink+anv: remove dEQP-GLES31.functional.layout_binding.ubo.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: use the null surface with unused push descriptor binding table entries

Some binding table entries have been identify as unused in the shaders
by the push constant analysis pass. We can just put the null entry in
there.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b49b18f0b7 ("anv: reduce BT emissions & surface state writes with push descriptors")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: return properly typed value for no ubo promoted

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: check that push range actually match binding considered

We can't just check the load_ubo range is contained in the push entry,
we also need to check that the push entry set/binding matches the
load_ubo set/binding.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: don't nullify entries

We'll use those to fill the push constant addresses, so we can't have
them turned to null.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

iris: let isl set tiling mode for external resources

Patch sets memory object external format (which is otherwise
PIPE_FORMAT_NONE for memory objects) before main surface gets
configured. With this we can add a check that when dealing
with external resource that has no modifier set, we let isl
figure out the tiling mode.

Fixes memobj tests on DG2:
   piglit.spec.ext_external_objects.vk-image-display-muliple-textures
   piglit.spec.ext_external_objects.vk-image-display-overwrite
   piglit.spec.ext_external_objects.vk-depth-display
   piglit.spec.ext_external_objects.vk-image-display
   piglit.spec.ext_external_objects.vk-stencil-display

v2: add assert and comment on tiling decision (Ken)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7684
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20473>

radv/rt: use a smaller value to enable scratch

The scratch allocation alignment on GFX11 is small enough that this should
help. Would be nice to someday remove this hack completely though.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>

aco: align scratch size during assembly

This lets us use less scratch if both VGPR spilling and scratch intrinsics
are used.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>

aco/gfx11: reduce scratch allocation alignment

fossil-db (gfx1100):
Totals from 112 (0.08% of 134574) affected shaders:
Scratch: 1513472 -> 1455360 (-3.84%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>

vc4: Fix running process_mux_deps on irrelevant type of instructions

Only ALU and ALU Small Imm instructions have input mux.

Signed-off-by: Qiu Wenbo <qiuwenbo@kylinos.com.cn>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20581>

vc4: Fix RADDR_A field extraction of branch instruction

Signed-off-by: Qiu Wenbo <qiuwenbo@kylinos.com.cn>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20581>

zink: add a bunch of asserts for starting dynamic render

try to avoid any race condition bugs triggering later when they're
harder to catch

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: re-clamp dynamic render area when doing swapchain fixups

this may catch another corner case if a late fixup changes fb size

fixes (lavapipe):
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.clear_render

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: catch a potential corner case with dynamic render and swapchain updates

zink_prep_fb_attachment() calls acquire internally, which means it's theoretically
possible that fixups are required very late in this function

never seen it happen, but who knows

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: split out swapchain render update fixups into separate function

this needs to be more granular for corner cases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: protect against invalid scissored renderpass clears

if the clear region is oob, this is illegal and may crash some drivers

fixes (lavapipe):
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.buffer_age_clear_render
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.buffer_age_render_clear

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: only update framebuffer object during swapchain update if framebuffer exists

otherwise this might be randomly creating an unused framebuffer for dynamic render

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

intel/eu/validate: Check predication and cmod for SEL, CMP, and CMPN

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/eu/validate: Add validation for csel

v2: Also check the condition modifier. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/eu/validate: Add validation for bfi2

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/eu/validate: More validation for logic ops

v2: Use number of source to condition validating src1 instead of using
the opcode. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/compiler: Assert that ARF used is the accumulator

v2: Move the new check to be with similar existing checks. Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/compiler: Validate 3-source instruction source strides

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/compiler: Validate 3-source instruction sources have same base type

This can't be checked in EU validation because the bits to describe the
base type of the individual sources no longer exist.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

aco: Mark more instructions as 16bit on GFX10.

p_cvt_f16_f32_rtne will be lowered to v_cvt_f16_f32 and we already know that
preserves the high bits.

I tested the others on GFX1036.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20574>

aco: use s_delay_alu skip field

fossil-db (gfx1100):
Totals from 130066 (96.65% of 134574) affected shaders:
Instrs: 80208817 -> 71420648 (-10.96%)
CodeSize: 403523036 -> 368370360 (-8.71%)
Latency: 658064779 -> 657935384 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 87698268 -> 87693326 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>

aco: add more dependency instructions under waitcnt class

This makes these instructions free when considering pipeline statistics
and s_delay_alu insertion.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>

aco: improve parse_delay_alu

Use gpr_map to determine how many cycles each dependency of the
s_delay_alu needs. This information helps the pass avoid further
s_delay_alu instructions.

fossil-db (gfx1100):
Totals from 13097 (9.73% of 134574) affected shaders:
Instrs: 30711894 -> 30702692 (-0.03%)
CodeSize: 153462500 -> 153425692 (-0.02%)
Latency: 372758612 -> 372741922 (-0.00%)
InvThroughput: 50164111 -> 50160717 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>

radv/winsys: fill real info for CHIP_GFX1100

From my AMD Radeon 7900 XT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20476>

radv: configure VGT_TF_PARAM directly from the command buffer

The driver re-emits the tessellation domain origin state when a new
pipeline with tessellation is bound, so this can be moved there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>

radv: fix re-emitting tessellation domain origin when it's dynamic

The winding order can be different between pipelines.

Fixes new dEQP-VK.pipeline.pipeline_library.dynamic_control_points.change_*_winding.

Fixes: f22290949d3 ("radv: add support for dynamic tessellation domain origin")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>

util/00-mesa-defaults: add Limbo workaround

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7976
Cc: mesa-stable
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20548>

anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+

This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

As no ANV_PIPE_INVALIDATE_BITS is set as parameter of
anv_add_pending_pipe_bits(),
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one
PIPELINE_CONTROL.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>

iris: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+

This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>

hud: extract float printf modifer selection logic to helper

And use it when printing to a file from hud_graph_add_value.

This turns:
  fps: 59.972473
Into:
  fps: 59.97

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

dri: get rid of LIBGL_SHOW_FPS

The same functionnality can be achieved using GALLIUM_HUD=stdout,fps (and for
now a fallback is doing this if LIBGL_SHOW_FPS=1 is used).

This removes one entry from the vtable and simplify dri3_handle_present_event.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

hud,dri: emulate LIBGL_SHOW_FPS using hud

LIBGL_SHOW_FPS=1 is now almost equivalent to using:

   GALLIUM_HUD=stdout,fps
   GALLIUM_HUD_VISIBLE=false
   GALLIUM_HUD_PERIOD=$LIBGL_SHOW_FPS

so we can drop LIBGL_SHOW_FPS handling in dri and move it to hud.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

hud: add "stdout" option to print values to console

Values gathered by the hud context will be printed to stdout,
prefixed by their name.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>