Stefan Roese [Tue, 25 Aug 2015 11:18:38 +0000 (13:18 +0200)]
arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig file
Introduce a mach-mvebu/Kconfig for all Armada based SoC's.
Signed-off-by: Stefan Roese <sr@denx.de>
Tom Rini [Mon, 19 Oct 2015 22:46:28 +0000 (18:46 -0400)]
Prepare v2015.10
Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sat, 17 Oct 2015 18:58:50 +0000 (12:58 -0600)]
powerpc: Drop old non-generic-board code
This code is no-longer used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:30 +0000 (16:40 -0400)]
sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:31 +0000 (16:40 -0400)]
sbc8641d: increase monitor size from 256k to 384k
Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure. A bisect led to commit
6eed3786c68c8a49d
("net: Move the CMD_NET config to defconfigs"). This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:
u-boot$git describe
6eed3786c68c8a49d
v2015.07-rc1-412-g6eed3786c68c
^^^
u-boot$ls -l ../41*/u-boot.bin
-rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
-rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
u-boot$bc
bc 1.06.95
Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
This is free software with ABSOLUTELY NO WARRANTY.
For details type `warranty'.
256*1024
262144
i.e. we finally broke through the 256k monitor size. Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.
We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:29 +0000 (16:40 -0400)]
sbc8641d: add basic flash setup instructions to README file
...so that I don't have to go work them out from scratch again
by peering at the manual.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:28 +0000 (16:40 -0400)]
sbc8641d: set proper environment sector size.
When debugging an env fail due to too small a malloc pool, it
was noted that the env write was 256k. But the device sector
size is 1/2 that, as can be seen from "fli" output:
Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 131 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 64 bytes
Sector Start Addresses:
FF000000 E RO
FF020000 E RO
FF040000 E RO
FF060000 E RO
FF080000 E RO
FF0A0000 E RO
FF0C0000 E RO
FF0E0000 E RO
FF100000 E RO
FF120000 E RO
[...]
FFF00000 RO
FFF20000 RO
FFF40000 RO
FFF60000 RO
FFF80000 RO
FFFA0000 RO
FFFC0000 RO
FFFE0000 E RO
FFFE8000 RO
FFFF0000 E RO
FFFF8000 RO
=>
The desired env sector is
FFF40000->
FFF60000, or 0x20000 in length,
just after the 256k u-boot image which starts @
FFF00000.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:27 +0000 (16:40 -0400)]
sbc8641d: increase malloc pool size to a sane default
Currently the board fails to save its env, since the env size
is much smaller than the sector size, and the malloc fails for
the pad buffer, giving the user visible symptom of:
Unable to save the rest of sector (253952)
Allow for 1M malloc pool, the same as used on the sbc8548 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Paul Gortmaker [Sat, 17 Oct 2015 20:40:26 +0000 (16:40 -0400)]
sbc8641d: enable command line editing
It is just too painful to use interactively without it.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Andrej Rosano [Wed, 14 Oct 2015 15:45:40 +0000 (17:45 +0200)]
image-fit: Fix signature checking
On signature verification failures fit_image_verify() should
exit with error.
Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Ladislav Michl [Mon, 12 Oct 2015 16:09:14 +0000 (18:09 +0200)]
igep00x0: Use BCH8 ECC
Used NAND chips requires at least 4-bit error correction, so use BCH8
as it is what kernel uses.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Javier Martinez Canillas <javier@osg.samsung.com>
Liviu Dudau [Mon, 19 Oct 2015 10:08:32 +0000 (11:08 +0100)]
vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>
Liviu Dudau [Mon, 19 Oct 2015 10:08:31 +0000 (11:08 +0100)]
vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Fabio Estevam [Wed, 23 Sep 2015 03:50:39 +0000 (00:50 -0300)]
dfu: dfu_sf: Take the start address into account
The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.
For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.
In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.
Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math]
Signed-off-by: Tom Rini <trini@konsulko.com>
Fabio Estevam [Tue, 22 Sep 2015 03:55:00 +0000 (00:55 -0300)]
dfu: dfu_sf: Use the erase sector size for erase operations
SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.
To illustrate the problem:
Copying data from PC to DFU device
Download [=========================] 100% 478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!
In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.
478208 = 7 entire sectors of 64kiB + 19456 bytes.
Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.
Fix the issue by always erasing with the erase sector size.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tom Rini [Mon, 19 Oct 2015 17:32:09 +0000 (13:32 -0400)]
doc/README.scrapyard: Add more entries
- Add deletions from August 30 2015.
- A few from Sept 12, one from Oct 2nd.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 19 Oct 2015 16:24:52 +0000 (12:24 -0400)]
Revert "arm: Remove inetspace_v2_cmc board"
Upon further review when populating README.scrapyard, inetspace_v2_cmc
is a variant on netspace_v2 and not just an orphan config.
This reverts commit
653600a715db49859c06ba5dfb858c15c4108d54.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 19 Oct 2015 15:30:38 +0000 (11:30 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Mon, 19 Oct 2015 15:20:54 +0000 (11:20 -0400)]
Revert "arm: Remove d2net_v2 defconfig file"
Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config. To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.
This reverts commit
1363740e7948a8e4bee8d5adcdf0f63f7782879d.
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 19 Oct 2015 15:05:47 +0000 (11:05 -0400)]
doc/README.scrapyard: Populate recent removals
Add in the commit IDs / dates for boards removed on Sept 2nd.
Signed-off-by: Tom Rini <trini@konsulko.com>
Lubomir Rintel [Wed, 14 Oct 2015 15:17:54 +0000 (17:17 +0200)]
ARM: rpi: add another revision of Raspberry Pi A+
Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Eric Cooper [Mon, 12 Oct 2015 23:18:52 +0000 (19:18 -0400)]
ARM: dockstar: move start of environment area
The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device. This patch moves the environment to a higher address to avoid
that.
Signed-off-by: Eric Cooper <ecc@cmu.edu>
Lokesh Vutla [Thu, 8 Oct 2015 06:01:47 +0000 (11:31 +0530)]
ARM: k2e/l: Apply WA for selecting PA clock source
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tom Rini [Sat, 17 Oct 2015 12:04:11 +0000 (08:04 -0400)]
arch/powerpc/config.mk: Pass -fno-ira-hoist-pressure when possible
There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.
Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 17 Oct 2015 00:21:04 +0000 (20:21 -0400)]
Merge git://git.denx.de/u-boot-socfpga
Dinh Nguyen [Mon, 12 Oct 2015 16:59:04 +0000 (11:59 -0500)]
arm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cyclone5_socdk dts
We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh Nguyen [Thu, 15 Oct 2015 15:13:36 +0000 (10:13 -0500)]
arm: socfpga: enable data/inst prefetch and shared override in the L2
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Anthony Felice [Fri, 9 Oct 2015 20:38:39 +0000 (16:38 -0400)]
vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit
3f353cecc
(vf610: refactor DDRMC code).
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Tom Rini [Fri, 16 Oct 2015 11:19:47 +0000 (07:19 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-samsung
Alison Wang [Wed, 9 Sep 2015 02:22:02 +0000 (10:22 +0800)]
arm: mmu: Add missing volatile for reading SCTLR register
Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.
(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)
Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU and later causes a PCIE VA access
failure.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Tom Rini [Thu, 15 Oct 2015 21:45:39 +0000 (17:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
Fabio Estevam [Tue, 13 Oct 2015 14:01:27 +0000 (11:01 -0300)]
pci: pcie_imx: Fix hang on mx6qp
PCI driver currently hangs on mx6qp.
Toggle the reset bit with the appropriate timings to fix the issue.
Based on the FSL kernel driver implementation.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Thierry Reding [Thu, 20 Aug 2015 09:52:15 +0000 (11:52 +0200)]
armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:52:14 +0000 (11:52 +0200)]
armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tom Rini [Thu, 15 Oct 2015 12:43:38 +0000 (08:43 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Masahiro Yamada [Wed, 30 Sep 2015 12:15:58 +0000 (21:15 +0900)]
ARM: uniphier: fix address mapping in README.uniphier
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Thierry Reding [Thu, 20 Aug 2015 09:52:13 +0000 (11:52 +0200)]
armv8/mmu: Clean up TCR programming
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Stefan Agner [Wed, 14 Oct 2015 17:58:43 +0000 (10:58 -0700)]
arm: vf610twr: improve memory layout
Currently, the device tree relocation is disabled, likely to
keep some DDR3 RAM at the end for Cortex-M4 firmwares. This
can be archived using bootm_size, which limits the image
processing range of the boot commands.
Move the device tree standard load address to a higher address
which aligns better with what we are doing on other boards.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Wed, 14 Oct 2015 02:54:32 +0000 (23:54 -0300)]
colibri_vf: Fix bstlen field
Commit
3f353cecc ("vf610: refactor DDRMC code") changed the original
bstlen field from 3 to 0.
Restore the original value for proper behaviour.
Based on the patch from Anthony Felice <tony.felice@timesys.com>
for the vf610twr board.
Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Stefan Agner [Wed, 14 Oct 2015 05:11:42 +0000 (22:11 -0700)]
mtd: nand: vf610_nfc: resync with upstream Linux version
This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678
Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
If flipped bits are below threshold, also return an empty
OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
to reflect better what they really representing.
The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Wood <scottwood@freescale.com>
Albert ARIBAUD [Wed, 14 Oct 2015 08:46:36 +0000 (10:46 +0200)]
Merge remote-tracking branch 'u-boot/master'
Tom Rini [Tue, 13 Oct 2015 12:37:38 +0000 (08:37 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Tobias Jakobi [Mon, 5 Oct 2015 11:47:53 +0000 (13:47 +0200)]
exynos: more debug and cleanup in do_sdhci_init()
Add more debug printfs in do_sdhci_init() for calls
that can potentially fail.
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tobias Jakobi [Mon, 5 Oct 2015 11:47:52 +0000 (13:47 +0200)]
exynos: be more verbose in process_nodes()
In case sdhci_get_config() or do_sdhci_init() fail, show
the error code that was returned.
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tobias Jakobi [Mon, 5 Oct 2015 11:47:51 +0000 (13:47 +0200)]
exynos: Fix passing of errors in exynos_mmc_init()
exynos_mmc_init() always returns zero, so for the caller
it looks like it never fails.
Correct this by returning the error code of process_nodes().
For process_nodes() do something similar and return early
when do_sdhci_init() fails.
v2: Only fail in process_nodes() if we fail on all
available nodes.
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tobias Jakobi [Mon, 5 Oct 2015 11:47:50 +0000 (13:47 +0200)]
exynos: Properly zero initialize host in s5p_sdhci_init()
This makes sure that setting the host_caps in s5p_sdhci_core_init()
doesn't operate on potentially uninitialized memory.
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Guillaume GARDET [Fri, 9 Oct 2015 12:26:23 +0000 (14:26 +0200)]
odroid: Add boot script (boot.scr) support
Add boot script (boot.scr) support. If no boot script are
found, it boots as usual.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Guillaume GARDET [Fri, 9 Oct 2015 12:26:22 +0000 (14:26 +0200)]
odroid: replace 'fatload' with 'load' to be able to use EXT* partitions
Replace 'fatload' command by 'load', to be able to use EXT*
partitions while keeping FAT partition compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Fabio Estevam [Sat, 3 Oct 2015 17:21:00 +0000 (14:21 -0300)]
ls102xa: Fix reset hang
Since commit
623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit
623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sat, 3 Oct 2015 17:20:59 +0000 (14:20 -0300)]
imx_watchdog: Add a header file for watchdog registers
Create fsl_wdog.h to store the watchdog registers and bit fields.
This can be useful when accesses to the watchdog block are made from other
parts, such as arch/arm/ cpu code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tom Rini [Mon, 12 Oct 2015 15:14:27 +0000 (11:14 -0400)]
Prepare v2015.10-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
Ludger Dreier [Mon, 12 Oct 2015 11:34:24 +0000 (13:34 +0200)]
env_eeprom.c: Correct using saved environment
The changes in
ed6a5d4 unintentionally broke support for reading the
environment saved to eeprom back. To correct this the crc-check and
decision on which environment to use is now moved to env_relocate_spec.
This is done for both the "redundant env" and the "single env" case.
Signed-off-by: Ludger Dreier <ludger.dreier@keymile.com>
Albert ARIBAUD (3ADEV) [Sun, 11 Oct 2015 18:06:39 +0000 (20:06 +0200)]
pcm052: fix MTD partitioning
MTD partitioning in current pcm052 configuration is inconsistent.
Fix it across MTDPARTS_DEFAULT, CONFIG_EXTRA_ENV_SETTINGS, and
CONFIG_ENV_OFFSET[_REDUND].
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tom Rini [Sun, 11 Oct 2015 20:48:36 +0000 (16:48 -0400)]
test/fs/fs-test.sh: Update expected results and TC10 logic
With the changes in
7a3e70c we now get read(2) behavior so trying to
read 2MB with 1MB left in the file results in 1MB read and a warning.
We update the test logic here to make sure we read back 1MB as expected.
This change however changes the overall summary as while EXT4 continues
to not have offset support the test now fails when expected to pass
rather than fails when expected to fail (and we report that as pass).
Signed-off-by: Tom Rini <trini@konsulko.com>
Vladimir Zapolskiy [Sun, 4 Oct 2015 22:18:45 +0000 (23:18 +0100)]
lpc32xx: fix calculation of HCLK PLL output clock
Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Sun, 4 Oct 2015 22:18:24 +0000 (23:18 +0100)]
lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN config
According to ARM PrimeCell PL175 documentation WAIT_OEN config value
is defined without any additional clocks added to the value set by a
client, the change fixes the wrong interface to WAIT_OEN config.
The change also touches a single user of LPC32xx EMC and corrects
configured "output enable delay" value on its side according to the
changed interface.
No functional change intended.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Ezequiel García [Sun, 4 Oct 2015 21:34:42 +0000 (18:34 -0300)]
nand: omap_gpmc: Change correctable bit-flips messages to debug()
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Vagrant Cascadian [Fri, 2 Oct 2015 16:11:51 +0000 (09:11 -0700)]
Fix variation in timestamps caused by timezone differences.
When building with SOURCE_DATE_EPOCH set, avoid use of mktime in
default_image.c, which converts the timestamp into localtime. This
causes variation based on timezone when building u-boot.img and
u-boot-sunxi-with-spl.bin targets.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Tom Rini [Thu, 27 Aug 2015 19:42:41 +0000 (15:42 -0400)]
common/image.c: Make boot_get_ramdisk() perform a check for Android images
In
2dd4632 the check for where a ramdisk is found on an Android image
was got moved into the "normal" loop here, causing people to have to
pass the kernel address in the ramdisk address location in order to have
Android boot still. This changed previous behavior so perform a check
early in the function to see if we have an Android image and if so use
that as where to look for the ramdisk (which is what the rest of the
code here expects). We allow for this to still be overridden with an
explicit ramdisk address to be passed as normal.
Cc: Rob Herring <robh@kernel.org>
Reported-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 26 Aug 2015 19:21:23 +0000 (15:21 -0400)]
tools/mkimage.c: Clarify help text for -D slightly
Try and make it clear that -D will replace all arguments passed to dtc
and is not appending them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Ian Campbell [Tue, 29 Sep 2015 09:27:09 +0000 (10:27 +0100)]
arndale: Apply Cortex-A15 errata #773022 and #774769
We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy
userspace.
However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.
Searching around I found https://bugs.launchpad.net/arndale/+bug/
1081417
which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
and CPU Errata 773022 and 774769.
This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.
The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no
segfaults.
Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.
I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.
Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Rob Herring [Mon, 5 Oct 2015 19:37:07 +0000 (14:37 -0500)]
image: fix support for Android boot images with no ramdisk
If an Android boot image does not contain a ramdisk, make sure rd_len
and rd_data are returned to indicate no ramdisk rather than just relying
on returning an error.
Signed-off-by: Rob Herring <robh@kernel.org>
Julius Werner [Wed, 7 Oct 2015 03:03:53 +0000 (20:03 -0700)]
Add support for LZ4 decompression algorithm
This patch adds support for LZ4-compressed FIT image contents. This
algorithm has a slightly worse compression ration than LZO while being
nearly twice as fast to decompress. When loading images from a fast
storage medium this usually results in a boot time win.
Sandbox-tested only since I don't have a U-Boot development system set
up right now. The code was imported unchanged from coreboot where it's
proven to work, though. I'm mostly interested in getting this recognized
by mkImage for use in a downstream project.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Oct 2015 06:20:37 +0000 (08:20 +0200)]
ppc4xx: Remove lcd4_lwmon5 support
This platform has not gone into production. So lets remove it.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Stefan Roese [Fri, 2 Oct 2015 06:20:36 +0000 (08:20 +0200)]
ppc4xx: Convert lwmon5 board to generic board
Add CONFIG_SYS_GENERIC_BOARD to lwmon5.h and CONFIG_DISPLAY_BOARDINFO
to Kconfig file.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Stefan Roese [Fri, 2 Oct 2015 06:20:35 +0000 (08:20 +0200)]
Revert "powerpc: ppc4xx: remove lwmon5 support"
This reverts commit
8fe11b8901a31d11990488c82bc23612589d57be.
I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Benoît Thébaudeau [Mon, 28 Sep 2015 13:45:32 +0000 (15:45 +0200)]
fs/fat/fat_write: Fix management of empty files
Overwriting an empty file not created by U-Boot did not work, and it
could even corrupt the FAT. Moreover, creating empty files or emptying
existing files allocated a cluster, which is not standard.
Fix this by always keeping empty files clusterless as specified by
Microsoft (the start cluster must be set to 0 in the directory entry in
that case), and by supporting overwriting such files.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Benoît Thébaudeau [Mon, 28 Sep 2015 13:45:31 +0000 (15:45 +0200)]
fs/fat/fat_write: Factor out duplicate code
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Benoît Thébaudeau [Mon, 28 Sep 2015 13:45:30 +0000 (15:45 +0200)]
fs/fat/fat_write: Fix curclust/newclust mix-up
curclust was used instead of newclust in the debug() calls and in one
CHECK_CLUST() call, which could skip a failure case.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Benoît Thébaudeau [Mon, 28 Sep 2015 13:45:29 +0000 (15:45 +0200)]
fs/fat/fat_write: Merge calls to set_cluster()
set_contents() had uselessly split calls to set_cluster(). Merge these
calls, which removes some cases of set_cluster() being called with a
size of zero.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Benoît Thébaudeau [Mon, 28 Sep 2015 13:45:28 +0000 (15:45 +0200)]
fs/fat/fat_write: Fix buffer alignments
set_cluster() was using a temporary buffer without enforcing its
alignment for DMA and cache. Moreover, it did not check the alignment of
the passed buffer, which can come directly from applicative code or from
the user.
This could cause random data corruption, which has been observed on
i.MX25 writing to an SD card.
Fix this by only passing ARCH_DMA_MINALIGN-aligned buffers to
disk_write(), which requires the introduction of a buffer bouncing
mechanism for the misaligned buffers passed to set_cluster().
By the way, improve the handling of the corresponding return values from
disk_write():
- print them with debug() in case of error,
- consider that there is an error is disk_write() returns a smaller
block count than the requested one, not only if its return value is
negative.
After this change, set_cluster() and get_cluster() are almost
symmetrical.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Igor Grinberg [Thu, 8 Oct 2015 18:12:25 +0000 (21:12 +0300)]
ti: omap3: config: remove 1 from boolean define
CONFIG_TWL4030_POWER is a boolean define variable. It is either defined
or not defined and should not have a value assigned to it.
Remove the value.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Ryan Harkin [Fri, 9 Oct 2015 16:18:08 +0000 (17:18 +0100)]
vexpress64: juno: use /dev/sda2
This patch changes the default "root=" parameter to "/dev/sda2".
Many linux based distros use /dev/sda1 for their boot partition; this is
often not a rootfs that can be used by the "root=" parameter.
Linaro images use /dev/sda1 as a boot partition, although this of a
different nature to a distro image. Linaro uses /dev/sda2 for the rootfs
partition.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:07 +0000 (17:18 +0100)]
vexpress64: juno: add alternate kernel and device tree filenames
The latest Juno firmware stores the files in NOR flash as "norkern" for
kernel binary, "board.dtb" for the device tree binary.
The "old" firmware used the name "Image" for the kernel binary and
"juno" for the device tree binary.
Rather than just change the default U-Boot configuration to use the new
names, breaking users with the old firmware, attempt to load the default
filename first. If that fails, attempt to load the alternate filename.
I've echo'd that we are loading the alternate file to counter the
output from "afs load" shown if the first load attempt fails. For
example, I see output like this on my Juno board when it's configured
the with the "old" firmware:
image "norkern" not found in flash
Loading Image instead of norkern
loaded region 0 from
08500000 to
80000000,
00AB6318 bytes
image "board.dtb" not found in flash
Loading juno instead of board.dtb
loaded region 0 from
0A000000 to
83000000,
00003188 bytes
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:06 +0000 (17:18 +0100)]
vexpress64: juno: add optional initrd
Some OS images require an initrd on Juno.
If the file ramdisk.img exists in NOR flash, then we load it and pass
the address to the kernel. Otherwise, we pass the "-" parameter as
before.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:05 +0000 (17:18 +0100)]
common/armflash: load_image returns success or failure
Change the load_image so that it returns success or failure of the
command (using CMD_RET_SUCCESS or CMD_RET_FAILURE).
This way, hush scripts can optionally load different files depending
upon the system configuration.
A simple example:
if afs load ${kernel_name} ${kernel_addr}; then echo loaded; else echo \
not loaded; fi
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:04 +0000 (17:18 +0100)]
common/armflash: add command to check if image exists
Add a command to the ARM flash support to check if an image exists or
not.
If the image is found, it will return CMD_RET_SUCCESS, else
CMD_RET_FAILURE. This allows hush scripts to conditionally load images.
A simple example:
if afs exists ${kernel_name}; then echo found; else echo \
not found; fi
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:03 +0000 (17:18 +0100)]
vexpress64: juno: add androidboot.hardware=juno
Linaro's Juno Android builds requires the androidboot.hardware parameter
be set to a know board name.
Non-Android kernels ignore this extra parameter because they don't
contain code to parse it.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:02 +0000 (17:18 +0100)]
vexpress64: fvp dram: add DRAM configuration
Create an additional FVP configuration to boot images pre-loaded into
DRAM.
Sometimes it's preferential to boot the model by loading the files
directly into DRAM via model parameters, rather than using
SemiHosting.
An example of model parmaters that are used to pre-load the files
into DRAM:
--data cluster0.cpu0=Image@0x80080000 \
--data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \
--data cluster0.cpu0=uInitrd@0x84000000
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Update board/armltd/vexpress64/Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
Ryan Harkin [Fri, 9 Oct 2015 16:18:01 +0000 (17:18 +0100)]
vexpress64: increase max gunzip size
vexpress64 kernels are usually over 8 MBytes in length, so setting the
max uImage length to 64 Mbytes should give us plenty of scope for
expansion.
I mostly chose this length to match other board configs that use
"(64 << 20)".
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Ryan Harkin [Fri, 9 Oct 2015 16:18:00 +0000 (17:18 +0100)]
vexpress64: Kconfig: tidy up
The FVP and Juno settings were identical, but duplicated, so I removed
the duplication with this patch.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Adjust logic to keep if/endif in the file]
Signed-off-by: Tom Rini <trini@konsulko.com>
Ryan Harkin [Fri, 9 Oct 2015 16:17:59 +0000 (17:17 +0100)]
vexpress64: fix checkpatch warnings
This patch fixes a couple of checkpatch warnings on the vexpress64 config.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yao Yuan [Tue, 15 Sep 2015 10:28:20 +0000 (18:28 +0800)]
configs: ls1021atwr: Enable DSPI for LS1021ATWR
DSPI2 can be verified when boot from QSPI now.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Yao Yuan [Tue, 15 Sep 2015 10:28:19 +0000 (18:28 +0800)]
mtd: sf: Add support AT26DF081A chip
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Yuan Yao [Wed, 30 Sep 2015 07:35:15 +0000 (13:05 +0530)]
dm: dts: ls1021a-twr: Enable DSPI2 on LS1021ATWR
Erratum A-008022 has been fixed on LS1021A Rev2.0.
So we can use DSPI2 now, this patch enable DSPI2
in dts for LS1021ATWR.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Mirza Krak [Tue, 8 Sep 2015 08:30:49 +0000 (10:30 +0200)]
spi: tegra20: Add support for mode selection
Respect the mode passed in set_mode ops.
Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 7 Sep 2015 20:08:50 +0000 (01:38 +0530)]
spi: zynq_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 7 Sep 2015 19:56:29 +0000 (01:26 +0530)]
spi: xilinx_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Siarhei Siamashka [Thu, 8 Oct 2015 20:22:46 +0000 (23:22 +0300)]
sunxi: Fix USB regulators in Linksprite_pcDuino_defconfig
The pcDuino1 board unconditionally provides 5V to USB host
receptacles. The pcDuino2 board has a voltage regulator,
controlled by the PD2 pin which is pulled-up by default
(so that the USB power is also enabled by default).
Not specifying pins for enabling USB power in the defconfig
means that the PH3 and PH6 pins are driven high by default.
The PH6 pin is available on the Arduino-compatible expansion
header and touching it is not nice (this may be even dangerous,
depending on what kind of role is assigned to this particular
pin by various Arduino shields).
This patch explicitly configures the USB VBUS pins to "",
which means that no pins should be touched. The patch has
been tested on a pcDuino2 board and USB still works.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Siarhei Siamashka [Thu, 8 Oct 2015 20:22:45 +0000 (23:22 +0300)]
sunxi: Fix pcDuino reliability by downclocking DRAM to 360MHz
Linksprite_pcDuino_defconfig is a generic config for pcDuino1 and
pcDuino2 boards. The pcDuino2 board exists at least in two variants
(with DDR3 chips from HYNIX or NANYA). At least one pcDuino2 board
with HYNIX DDR3 fails the lima-memtester reliability test unless
the DRAM clock speed is reduced to 360MHz.
A detailed analysis report, generated by the a10-tpr3-scan tool with
the explanations why the DRAM is failing at 408MHz, is available at:
http://linux-sunxi.org/index.php?title=User:Ssvb/pcDuino2_with_HYNIX_DDR3_reliability_test&oldid=15152
http://web.archive.org/web/
20151008190210/http://linux-sunxi.org/User:Ssvb/pcDuino2_with_HYNIX_DDR3_reliability_test
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tom Rini [Fri, 9 Oct 2015 13:55:33 +0000 (09:55 -0400)]
Merge git://git.denx.de/u-boot-x86
Bin Meng [Wed, 7 Oct 2015 09:13:18 +0000 (02:13 -0700)]
pci: Fix expansion ROM programming for multi-function devices
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 8 Oct 2015 07:04:36 +0000 (03:04 -0400)]
Merge git://git.denx.de/u-boot-arc
Tom Rini [Thu, 8 Oct 2015 07:03:41 +0000 (03:03 -0400)]
Merge git://git.denx.de/u-boot-dm
Alexey Brodkin [Sun, 4 Oct 2015 13:10:26 +0000 (16:10 +0300)]
board: axs10x - cap max SDIO clock value to bus/2
It turned out with some boards (FPGA firmwares?) and cards combos
current clock settings doesn't work as expected leading to strange
card freezes or corrupted data being read from the card.
Especially this was seen with Transcend 2Gb cards shipped as a part of
ARC SDP:
----------------->8---------------
AXS# mmcinfo
Device: Synopsys Mobile storage
Manufacturer ID: 74
OEM: 4a60
Name: SDC
Tran Speed:
50000000
Rd Block Len: 512
SD version 3.0
High Capacity: No
Capacity: 1.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
AXS# fatload mmc 0
** Unrecognized filesystem type **
----------------->8---------------
With this change that problem is fixed.
Note "Tran Speed" above doesn't match clock value set in DW MMC.
It is max value for card's speed class.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Troy Kisky [Tue, 15 Sep 2015 01:06:31 +0000 (18:06 -0700)]
imximage: fix commands other than write_data
When CHECK_BITS_SET was added, they forgot to add
a new command table, and instead overwrote the
previous table.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Troy Kisky [Mon, 21 Sep 2015 21:02:48 +0000 (14:02 -0700)]
imximage: header.length of 4 is valid
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Simon Glass [Sat, 3 Oct 2015 17:21:16 +0000 (11:21 -0600)]
sandbox: Correct operaion of 'reset' command
Currently 'reset' only works with the test device tree. When run without a
device tree, or with the normal device tree, the following error is
displayed:
Reset not supported on this platform
Fix the driver and the standard device tree to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Simon Glass [Sat, 12 Sep 2015 14:45:20 +0000 (08:45 -0600)]
dm: test: Show the amount of leaked memory on error
Adjust the memory leak tests to show the amount of memory leaked. This can
be a useful signal as to what is wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 12 Sep 2015 14:45:19 +0000 (08:45 -0600)]
dm: core: Don't use pinctrl for the root device
Currently when driver model starts up it finds the root uclass and the
pinctrl uclass. This is because even the root node handles pinctrl
processing.
But this is not useful. The root node is not a real hardware device so
cannot require any particular pinmux settings. Also it means that the
memory leak tests fails, since they end up freeing more memory than
they allocate: the marker it set after the root device and pinctrl
uclass are allocated, and later once the pinctrl uclass is freed the memory
used by driver model is less than when the marker was set.
If a platform needs 'core' pin mulitplex settings it can do this with
a driver that is probed on start-up. It would be an abuse of the root node
to use this for pinctrl.
To avoid this problem, only process pinctrl settings for non-root nodes.
Signed-off-by: Simon Glass <sjg@chromium.org>