agx: Assert vertex_id, instance_id are VS-only

We can get them in other shaders transiently due to merging shader stages, but
they need to be lowered since the hardware versions only exist in the hardware
VS. So the compiler should never see them outside VS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>

asahi: Copy CSO stride

Fixes: 76725452239 ("gallium: move vertex stride to CSO")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>

agx: Use more barriers

Fixes flakiness in
KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>

agx: Fix extraneous bits with b2b32

From expanding mov_imm to take a 64-bit immediate. this worked by accident
before. Fixes brief regression in
dEQP-GLES31.functional.compute.shared_var.basic_type.bvec3.

Fixes: dbd98aa24d1 ("agx: Fix 64-bit immediate moves")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>

nir: Add load_sysval_agx intrinsic

For merging shader stages, it will be useful to express a load from an explicit
GL "descriptor set", so we can represent things like UBO loads with merged
shaders where UBOs can come from either stage. To do so, we add an intrinsic
representing a load from the driver's uniform tables, indexed like "descriptor
sets" with "bindings".

In principle, a layered GL-on-Vulkan implementation would use literal descriptor
sets for each stage, so I feel comfortable with the analogy here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>

anv: Advertise Vulkan 1.3 on Android 13

Older versions of Android rejected newer versions of Vulkan,[1] but Android
13 devices are 'strongly recommended' to support Vulkan 1.3.[2]

[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4781
[2] https://source.android.com/docs/compatibility/13/android-13-cdd#7142_vulkan

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24816>

panfrost/ci: Disable T720

Timing out and preventing merges. The lab needs to fix the devices and likely
add more coverage before this can be re-enabled.

The rest of the Panfrost/Collabora farm seems ok, it's just the T720 devices.

See https://gitlab.freedesktop.org/mesa/mesa/-/jobs/47910575 which at the time
of pushing has been waiting for t720 job to start for 45 minutes. This will
allow us to merge code today.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

anv: Do fast clear color initialization more delicately

Fixes: b4198e79 ("anv/cmd_buffer: Initalize the clear color struct for CNL+")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9464
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24768>

intel/isl: Don't over-allocate CLEAR_COLOR size to use whole cache line

At the time this was added to fix some test failures. But it seems that
the failures were happening due to missing cache flushes, so
this extra space is no longer neccessary.

Fixes: 37b4eacc ("intel/isl: Resize clear color buffer to full cacheline")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24768>

aco: fix u2f16 with 32bit input

The vulkan spec says all conversions are correctly rounded, so if the input
is larger than the largest fp16 value, we need to return MAX_FLOAT/inf
instead of cutting off the msbs.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24826>

aco: add adjust_bpermute_dst helper

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>

aco: clarify bpermute pseudo opcode names

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>

aco: fix p_bpermute_gfx6's exec save/restore with wave32

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>

aco: fix p_bpermute_gfx6 with input at non-zero byte

Same as the other bpermute pseudo instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>

anv/android: Add support for AHARDWAREBUFFER_FORMAT_YV12

The default MediaCodec software video decoder returns frames in this
format.

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24388>

anv/android: Fix importing hardware buffers with planar formats

Currently, we try to fetch the color aspect of the format and convert that
to an ISL format, which is then used to convert the pixel stride to bytes.
This does not work with planar formats because they don't have a color
aspect, and the planes can be of different sizes anyway, so may not have
the same byte stride. Change to calculate the stride individually for each
plane.

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24388>

aco: rework printing shader stages

To avoid printing "unknown" for shader object when eg. VS and TCS
are compiled separately.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24810>

CODEOWNERS: Add @flynnjiang for VirGL video

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24570>

radv: advertise NV_device_generated_commands_compute

This extension introduces a token for implementing DGC compute, it's
only intended to be used by vkd3d-proton.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

radv: allow DGC on the compute queue

DGC cmdbuf on ACE are executed as IB1 without chaining because IB2
isn't supported on ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

radv: implement NV_device_generated_commands_compute

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

radv: prepare radv_prepare_dgc() for DGC compute

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

radv: prepare radv_get_sequence_size() for DGC compute

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

radv: track the pipeline bind point for indirect commands layout

This will be used to implement DGC compute.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>

zink: sanitize optimal keys

shader keys represent pipeline states which trigger variants, but not
all shaders are affected by certain states

this adds some sanitizing for the optimal path to ignore shader variants
which won't have any effect for the currently bound shaders, thus reducing
the number of pipelines compiled (both unoptimized and optimized)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>

zink: use the "set" optimal key for prog last_variant_hash for consistency

this is the key that has been set during program update for reuse
everywhere else, and everything else in the driver uses it

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>

zink: don't start multiple cache jobs for the same program

if there's already a cache job in flight then starting a second one
is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>

frontends/va: Add BT.709 as supported postproc color standard

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>

gallium/auxiliary/vl: Don't set csc matrix in video_buffer/rgb_to_yuv_layer

It's now handled in va frontend instead.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>

frontends/va: Set csc matrix in postproc

Set correct matrix according to format, color standard and range.

Change default value for color range when not explicitly specified.
Use limited range for YUV and full range for RGB.

This also adds support for converting from full range YUV to RGB.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>

gallium/auxiliary/vl: Add BT.709 full csc matrix

Used for converting from full range YUV.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>

blorp: Drop unnecessary assertions in blorp_can_hiz_clear_depth

We already checks for the alignment and the multislice surface, we don't
need to add assertions around those two.

fixes: 37fcbb375cb ("blorp: Disable unaligned partial HIZ fast clears for HIZ_CCS too")
closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9684

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24837>

util: Decouple disk cache from EGL_ANDROID_blob_cache

Just because the user / system-integrater doesn't want shader disk
cache, doesn't mean they don't want EGL_ANDROID_blob_cache to work.
We've kind of already solved this for the android case, so just
generalize that solution.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9520
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24636>

intel/fs: Simplify compute_start_end().

Now that we have moved the screening up, we can simplify the code.  No
change in shader-db steam performance, n=10.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24702>

intel/fs: Move the defin[]/defout[] screening up to livein[]/liveout[] setup.

This keeps us from having to run the loop to propagate up quite so much.

steam shader-db time -1.86356% +/- 0.941498% (n=10).  There's a small
scheduling effect, since previously the scheduler wasn't considering
defin/defout:

cycles helped:   shaders/closed/steam/amnesia-the-dark-descent/high/241.shader_test FS SIMD16: 11428 -> 11422 (-0.05%) (scheduled: scheduled)
cycles helped:   shaders/humus-volumetricfogging2/1.shader_test FS SIMD32: 13832 -> 13800 (-0.23%) (scheduled: scheduled)
cycles helped:   shaders/tesseract/479.shader_test FS SIMD32:      9330 -> 8644 (-7.35%) (scheduled: scheduled)

cycles HURT:   shaders/robclark-shaders/android/angle/aztec_ruins/36.shader_test FS SIMD32: 7870 -> 7940 (0.89%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/57.shader_test FS SIMD32: 7870 -> 7940 (0.89%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/54.shader_test FS SIMD32: 7870 -> 7940 (0.89%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/android/angle/aztec_ruins/30.shader_test FS SIMD32: 8726 -> 8808 (0.94%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/51.shader_test FS SIMD32: 8726 -> 8808 (0.94%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/48.shader_test FS SIMD32: 8726 -> 8808 (0.94%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_4_off/129.shader_test TCS SIMD8: 3911 -> 3979 (1.74%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_4_off/109.shader_test TCS SIMD8: 3911 -> 3979 (1.74%) (scheduled: scheduled)

total cycles in shared programs: 313096438 -> 313096306 (<.01%)
cycles in affected programs: 92200 -> 92068 (-0.14%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24702>

intel/fs: Move defin/defout setup to the start of the loop.

Refactor for the next commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24702>

nir/opt_move: fix handling of if-condition

By accident, this used the parent of the nir_src which is a nir_if
instead of the parent of the SSA value.

Totals from 10814 (8.10% of 133461) affected shaders: (GFX11)
Instrs: 21759185 -> 21757190 (-0.01%); split: -0.02%, +0.01%
CodeSize: 112320272 -> 112316008 (-0.00%); split: -0.02%, +0.01%
SpillSGPRs: 11220 -> 11212 (-0.07%)
SpillVGPRs: 911 -> 903 (-0.88%); split: -1.54%, +0.66%
Latency: 258334759 -> 258316073 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 31428650 -> 31426394 (-0.01%); split: -0.02%, +0.01%
VClause: 309119 -> 309090 (-0.01%); split: -0.01%, +0.01%
SClause: 657028 -> 657150 (+0.02%); split: -0.03%, +0.04%
Copies: 1434209 -> 1432420 (-0.12%); split: -0.28%, +0.15%
Branches: 481804 -> 481801 (-0.00%)
PreSGPRs: 829995 -> 829966 (-0.00%)
PreVGPRs: 758249 -> 758253 (+0.00%)

Fixes: 8a78706643ecad8a1f303cc9358873abc29978b4 ('nir: refactor nir_opt_move')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24695>

nir/lower_gs_intrinsics: Remove end primitive for points

EndPrimitive() for points is entirely pointless, so just remove it when lowering
EndPrimitive to simplify the IR. This is (maybe) an optimization everywhere, and
will be relied on for correctness on Asahi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24798>

nir/print: Print access qualifiers for intrinsics

Instead of printing an opaque integer that needs to be manually decoded.
Example output:

    32x4   %7 = @image_load (%4 (0x0), %6, %5 (0x0), %4 (0x0)) (image_dim=2D, image_array=false, format=r8g8b8a8_snorm, access=readonly|reorderable, range_base=0, dest_type=float32)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24798>

compiler/types: Use smaller keys for explicit_matrix_types table

Instead of using the name as key, use a shorter struct type.
Only build a name string if we are adding a new entry to the table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>

compiler/types: Extract get_explicit_matrix_instance() function

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>

compiler/types: Use smaller keys for array_types table

Instead of building a string, build a short struct type and use
that as key.  The only caveat here is ensure there either there's
no internal padding or the internal padding is always the same.
Use a static assert to ensure we are in the former case.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>

compiler/types: Use ralloc for the key in array_types

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>

ci/deqp: backport fix for dEQP-EGL.functional.wide_color.*_888_colorspace_*

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24808>

rusticl: add cl_khr_expect_assume

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Andrey Alekseenko <al42and@gmail.com>
Tested-by: Yifeng Li <tomli@tomli.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23115>

spirv/nir_to_spirv: add expect assume op codes

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23115>

blorp: Disable unaligned partial HIZ fast clears for HIZ_CCS too.

Fixes MSAA scissored fast clears under zink and ANGLE.

Fixes: e488773b29d9 ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24225>

radv: Stop updating the stack_size in insert_rt_case

There are two paths that call insert_rt_case:
- Traversal shader: The stack size is ignored.
- Monolithic raygen shader: The stack sizes of the inlined shaders are
                            accounted for in compute_rt_stack_size.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

aco: Do not fixup registers if there are no shader calls

Frees up some registers when using monolithic compilation.

Quake II RTX and Control (with monolithic compilation):

Totals from 10 (29.41% of 34) affected shaders:
MaxWaves: 77 -> 98 (+27.27%)
Instrs: 49047 -> 48984 (-0.13%); split: -0.16%, +0.03%
CodeSize: 260420 -> 259880 (-0.21%); split: -0.25%, +0.04%
VGPRs: 1328 -> 1104 (-16.87%)
Latency: 477134 -> 479377 (+0.47%); split: -0.05%, +0.52%
InvThroughput: 137763 -> 114108 (-17.17%)
VClause: 1318 -> 1286 (-2.43%); split: -2.66%, +0.23%
SClause: 1295 -> 1293 (-0.15%); split: -0.54%, +0.39%
Copies: 7838 -> 7782 (-0.71%); split: -0.82%, +0.10%
Branches: 2592 -> 2589 (-0.12%)
PreSGPRs: 874 -> 796 (-8.92%)
PreVGPRs: 1283 -> 1013 (-21.04%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

radv/rt: Split stage initialization and hashing

The dependency chain is: init stages -> compute pipeline key -> hash
stages.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

radv/rt: Insert rt_return_amd before lowering shader calls

Also skips running nir_lower_shader_calls for the traversal shader. This
will be used to skip the pass and the rt_return_amd insertion for
monolithic raygen shaders.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

radv/rt: Add and use radv_build_traversal

Moves most of the build code to a helper which will be useful for adding
inline traversal.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

radv/rt: Do not apply stack_ptr for non-recursive stages

stack_ptr is set to 0.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

radv/rt: Remove some dead code

- call_idx_base was used for resume shaders in the shader call loop
- hit attribs are lowered elsewhere
- stack_size is set in radv_pipeline_rt.c

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>

nv/codegen: Remove Function::buildDefSets

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Delete periodicMask32

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Delete unused OP_CONSTRAINT

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv50_ir_ra: Delete unused functions

Wrap the file in an anonymous namespace and delete any code that
gcc warns is unused.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Remove unused clipVertexOutput var

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Merge from_common into from_nir

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Remove fragCoord variable.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Delete OP_EXP, OP_LOG

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Delete OP_WRSV

It's never generated by anything.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nv/codegen: Fix an uninitialized variable warning

The warning was actually a false positibe, but CI failed with:
error: 'nvirOp' may be used uninitialized [-Werror=maybe-uninitialized]

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>

nir/load_store_vectorize: Handle intrinsics with constant base

This includes nir_load_stack and nir_store_stack, which are vectorized
in nir_lower_shader_calls. If not adjusted, we end up loading from
the wrong base.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9596
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9587
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24789>

iris: implement a dummy depth flush for Wa_14016712196

Emit depth flush after state that sends implicit depth flush. These
states are:

 3DSTATE_HIER_DEPTH_BUFFER
 3DSTATE_STENCIL_BUFFER
 3DSTATE_DEPTH_BUFFER
 3DSTATE_CPSIZE_CONTROL_BUFFER

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24689>

anv: implement a dummy depth flush for Wa_14016712196

Emit depth flush after state that sends implicit depth flush. These
states are:

 3DSTATE_HIER_DEPTH_BUFFER
 3DSTATE_STENCIL_BUFFER
 3DSTATE_DEPTH_BUFFER
 3DSTATE_CPSIZE_CONTROL_BUFFER

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24689>

nir: unify lower_find_msb with has_{find_msb_rev,uclz}

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>

nir: unify lower_bitfield_extract with has_bfe

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>

nir: unify lower_bitfield_insert with has_{bfm,bfi,bitfield_select}

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>

ac/sqtt,radv/sqtt: Add and use marker for separate RT compilation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

radv/sqtt: Handle separately-compiled RT pipelines

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

radv/sqtt: Write LDS size metadata in code objects

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

radv/sqtt: Unregister records based on hash

RT pipelines have multiple hashes used in records, so don't always use
the pipeline hash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

radv/sqtt: Move record filling to helper function

RT shaders construct records differently, but this piece of code is
common to all types of pipelines.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

ac/rgp: Add metadata for separate-compiled RT stages

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

ac/rgp: Write lds_size metadata

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

ac/sqtt,radv: Split internal and API hash in PSO correlations

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

ac/msgpack: make fixstrs a const char

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>

etnaviv: Fully replicate back stencil config

The blob replicates both the value mask as well as the stencil reference
of the back-facing stencil to the front-facing stencil. This fixes the
remaining failures in the following dEQPs:

   dEQP-GLES2.functional.fbo.render.*_stencil_index8

Fixes: c8ccd63911d ("etnaviv: Fix depth stencil ops on GC880/GC2000")
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4867>

anv: Update Wa_16014390852 for MTL

On MTL Wa_16014390852 is fixed on B0 stepping so we can't use a macro
check anymore for this workaround.

cc: mesa-stable

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24812>

aco: implement create_tcs_jump_to_epilog()

This implements jumping from the main TCS to the epilog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

aco: allow SGPRs operands with p_jump_to_epilog

For TCS epilogs, we will have to pass SGPRs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

aco: adjust TCS epilogs for RADV

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

aco: fix jumping from main TCS to epilog on GFX9+

On GFX9+, VS is merged with TCS which means this function is called
twice and the epilog was emitted in both shader parts.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

radv: add tcs_out_patch_fits_subgroup to radv_tcs_epilog_key

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

radv: declare shader arguments for TCS epilogs

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

radv: stop declaring the scratch offset argument for TCS epilogs

ACO skip it for epilogs now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

radv: use the maximum possible workgroup size for TCS epilogs

It's similar to when the patch control points value is dynamic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>

ac/surface: limit RADEON_SURF_NO_TEXTURE to color surfaces

For z surfaces, flags.texture should be based on
RADEON_SURF_TC_COMPATIBLE_HTILE alone.  Otherwise, addrlib could pick a
_X/_T swizzle mode for a MSAA depth texture, which is said to be broken:

  When _X/_T swizzle mode was used for MSAA depth texture, TC will get zplane
  equation from wrong address within memory range a tile covered and use the
  garbage data for compressed Z reading which finally leads to corruption.

Fixes: de0885cdb89 ("amd/surface: add RADEON_SURF_NO_TEXTURE flag")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24767>

lavapipe: use vk_buffer_range common code.

trivial switch over.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24822>

lavapipe: use vk_buffer common code.

This is a trivial swapover to the common runtime code for buffers.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24822>

zink: handle patch variable locations for separate shaders better

these don't overlap with other locations so they can keep whatever their
current assignments are

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24757>

zink: wait on async fence during ctx program removal

removed=true implies that no async jobs are outstanding

fixes #9580

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24811>

llvmpipe/cs: drop tgsi for compute/mesh/task shader internals.

This drops the info from the compute shader infrastructure.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24804>

llvmpipe/cs: convert to using tgsi->nir

Step 1 to removing tgsi info from llvmpipe

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24804>

llvmpipe/fs: move some tgsi checks in nir path to nir code.

This just does the equivalent checks using NIR instead of tgsi
translated info.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24804>

gallivm/nir: avoid using params->info

This shouldn't be needed.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24804>

llvmpipe/fs: drop cbuf 0 since it's lowered now.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24804>

gallivm: drop unused info parameter

This isn't used.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24804>