radeonsi: turn sh_base[PIPE_SHADER_VERTEX] into a constant in emit_draw_packets

HAS_TESS will also be used in the next commit

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>

spirv: Re-emit constants at their uses

Right now, spirv_to_nir places all constants at the top of the function
and has a hash table to de-duplicate them.  This change drops the hash
table and starts re-emitting constants more-or-less at their uses.  This
is more consistent with what we do in GLSL -> NIR translation.  It is,
however, a change to SPIR-V -> NIR translation which will likely affect
other optimizations in unexpected ways so it should be evaluated
separately.

This gives some good saves for spills/fills for Intel, without causing
any significant regressions on RADV, because it is using the
nir_opt_reuse_constants() pass.  In the long run that should be superseded
by some form of GCM.

```
Intel TGL results for Intel fossils:

Totals:
Instrs: 183287977 -> 183269431 (-0.01%); split: -0.07%, +0.06%
Cycles: 18224600804 -> 18223114114 (-0.01%); split: -0.16%, +0.15%
Spill count: 111031 -> 108377 (-2.39%); split: -2.45%, +0.06%
Fill count: 221781 -> 216479 (-2.39%); split: -2.39%, +0.00%
Scratch Memory Size: 4355072 -> 4180992 (-4.00%); split: -5.31%, +1.32%

Totals from 43684 (6.54% of 667704) affected shaders:
Instrs: 38289482 -> 38270936 (-0.05%); split: -0.33%, +0.28%
Cycles: 7166415272 -> 7164928582 (-0.02%); split: -0.40%, +0.38%
Spill count: 93747 -> 91093 (-2.83%); split: -2.90%, +0.07%
Fill count: 190943 -> 185641 (-2.78%); split: -2.78%, +0.00%
Scratch Memory Size: 3127296 -> 2953216 (-5.57%); split: -7.40%, +1.83%
```

```
RADV GFX1100 results for radv fossils:

Totals:
Instrs: 71623708 -> 71624667 (+0.00%); split: -0.00%, +0.01%
CodeSize: 369324312 -> 369334744 (+0.00%); split: -0.00%, +0.01%
SpillSGPRs: 13586 -> 13582 (-0.03%)
SpillVGPRs: 911 -> 910 (-0.11%); split: -0.55%, +0.44%
Latency: 632887831 -> 632880378 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 81674859 -> 81676684 (+0.00%); split: -0.00%, +0.01%
VClause: 1273752 -> 1273727 (-0.00%); split: -0.00%, +0.00%
SClause: 2409593 -> 2409078 (-0.02%); split: -0.02%, +0.00%
Copies: 4063579 -> 4064425 (+0.02%); split: -0.05%, +0.07%
Branches: 1196723 -> 1196720 (-0.00%); split: -0.00%, +0.00%

Totals from 16244 (12.17% of 133461) affected shaders:
Instrs: 31116807 -> 31117766 (+0.00%); split: -0.01%, +0.01%
CodeSize: 160316656 -> 160327088 (+0.01%); split: -0.01%, +0.01%
SpillSGPRs: 12270 -> 12266 (-0.03%)
SpillVGPRs: 835 -> 834 (-0.12%); split: -0.60%, +0.48%
Latency: 344388549 -> 344381096 (-0.00%); split: -0.01%, +0.00%
InvThroughput: 43043761 -> 43045586 (+0.00%); split: -0.01%, +0.01%
VClause: 433221 -> 433196 (-0.01%); split: -0.01%, +0.00%
SClause: 900825 -> 900310 (-0.06%); split: -0.06%, +0.00%
Copies: 1989000 -> 1989846 (+0.04%); split: -0.11%, +0.15%
Branches: 676625 -> 676622 (-0.00%); split: -0.00%, +0.00%
```

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>

radv: Use nir_opt_reuse_constants()

Right now, this won't change much the shaders since most of the NIR constants
are reused in the NIR generated by SPIR-V, but will make radv resilient to
when that behavior change.

```
RADV GFX1100 results for radv fossils:

Totals:
Instrs: 71623585 -> 71623708 (+0.00%); split: -0.00%, +0.00%
CodeSize: 369326156 -> 369324312 (-0.00%); split: -0.00%, +0.00%
SpillSGPRs: 13576 -> 13586 (+0.07%)
Latency: 632889681 -> 632887831 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 81674616 -> 81674859 (+0.00%); split: -0.00%, +0.00%
SClause: 2409601 -> 2409593 (-0.00%); split: -0.00%, +0.00%
Copies: 4063438 -> 4063579 (+0.00%); split: -0.00%, +0.01%
Branches: 1196703 -> 1196723 (+0.00%)
PreSGPRs: 4242897 -> 4243061 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 3926739 -> 3926742 (+0.00%)

Totals from 217 (0.16% of 133461) affected shaders:
Instrs: 353567 -> 353690 (+0.03%); split: -0.04%, +0.07%
CodeSize: 1790200 -> 1788356 (-0.10%); split: -0.15%, +0.04%
SpillSGPRs: 8 -> 18 (+125.00%)
Latency: 5152817 -> 5150967 (-0.04%); split: -0.05%, +0.01%
InvThroughput: 664273 -> 664516 (+0.04%); split: -0.03%, +0.06%
SClause: 10164 -> 10156 (-0.08%); split: -0.10%, +0.02%
Copies: 24225 -> 24366 (+0.58%); split: -0.32%, +0.90%
Branches: 7116 -> 7136 (+0.28%)
PreSGPRs: 13351 -> 13515 (+1.23%); split: -0.16%, +1.39%
PreVGPRs: 11583 -> 11586 (+0.03%)
```

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>

nir: Add nir_opt_reuse_constants()

Currently SPIR-V does pull all the NIR constants it creates into the
first block, but we plan to change that behavior to let those constants
be defined as they are used.

This pass was written to provide a fallback to the old behavior, it will
be used for radv to avoid regressions when performing the SPIR-V change.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>

r600: use correct cso pointer for fetch shader

Fixes: 76725452 (gallium: move vertex stride to CSO)

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9567

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24728>

ci/freedreno: handle disabling farm properly for each FD/Collabora farm

To acknowledge for disable freedreno or collabora farm, split definitions into:
 - google-* (a306, a530, a630)
 - collabora-* (a618, a660)

This let us control when jobs will run. This rules gets also used in zink.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>

ci/freedreno: switch references, the farm-rules takes care about this

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>

ci/freedreno: the tag belongs to the apq8016 only

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>

ci/zink: drop a630, which we currently have very low amount available

It's disabled anyway.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>

ci: remove LAVA prefix from variables which can be used also elsewhere

At least these two can be easily used in bare-metal or Labgrid setups.

Currently I already have MR for implementing these for Labgrid.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>

Revert "vk/wsi/x11: handle geometry updating more asynchronously"

This reverts commit 36d5b58317179e5db32800743ef0faed4655b9fb.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24742>

rusticl/kernel: optimize nir between lowering io and explicit types

This is required to get rid of unneeded memory operations, like direct
scratch stores/loads to the same location.

Fixes: 66c6061491a ("rusticl/kernel: get rid of initial function_temp type lowering")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24734>

nouveau: take glsl_type ref unconditionally

Calling into tgsi_to_nir requires it, which we are running into with vdpau
and potential other state-trackers still handing us TGSIs over.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9481
Fixes: 5889c13fcd4 ("nv50,nvc0: Use ttn for tgsi shaders by default")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24740>

ci: rename *.log to *.txt to work around gitlab bug

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24620>

vk/graphics: fix CWE handling with DS3

VkPipelineColorBlendStateCreateInfo::attachmentCount cannot be used to
generate the CWE mask since it cannot be read if enough dynamic state is in use

instead just pass the max mask and let drivers figure it out

cc: mesa-stable

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24673>

etnaviv: switch to float_to_ubyte(..)

The blob generates following values for e.g. this call.
  glBlendColor(0.002000f, 0.018000f, 0.030000f, 1.0)

  0xff010508, /*   [01424] PE.ALPHA_BLEND_COLOR := B=0x8,G=0x5,R=0x1,A=0xff */

etnaviv's etna_cfloat_to_uint8(..) creates different values.

  0.002000: 0x0
  0.018000: 0x4
  0.030000: 0x7

The same applies for the alpha reference value.

Lets drop this hand-rolled conversion helper to get the same values as
blob.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24727>

anv: remove assert, size is asserted in the runtime

Otherwise gets hit on Android CTS tests.

Reported-by: Chris Spencer <spencercw@gmail.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24722>

vulkan/runtime: change assert to match specification needs

Otherwise gets hit on Android CTS tests.

Reported-by: Chris Spencer <spencercw@gmail.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24722>

glthread: sync for VDPAU sync functions

They should sync according to the spec.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24528>

ci: disable duplicated pipelines triggered by marge

When Marge rebases, it creates two pipelines, one in the author's account
due to the rebase and another one in the target account due to the merge
request event. Depending on the order they appear, Marge erroneously
check the author's pipeline, and since it doesn't have the rights to
start this pipeline, Marge fails to merge because it timed out (since the
pipeline never got run).

Fix this by disabling the author's pipeline (source of type "push") when
a merge request is open.

We only disable when the pipeline is triggered by marge to not affect
running ci_run_n_monitor.py script

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24730>

docs: add one more 23.1.x release

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24735>

docs: update calendar for 23.1.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24735>

docs: add sha256sum for 23.1.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24735>

docs: add release notes for 23.1.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24735>

freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads.

We don't emit tex descriptors for the SSBOs, so if we took this path we'd
fault.

Fixes: 75eb0d2891c2 ("freedreno/ir3: Allow isam for non-bindless ssbo loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24682>

ci/freedreno: Skip some tests on a5xx that destabilize other tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24682>

nir/opt_large_constants: Handle small float arrays

Handles small arrays of integer, positive floats.

RADV fossils:

Totals from 65 (0.05% of 131205) affected shaders:
Instrs: 30001 -> 29936 (-0.22%); split: -0.39%, +0.18%
CodeSize: 165676 -> 164996 (-0.41%); split: -0.53%, +0.12%
Latency: 126873 -> 127178 (+0.24%); split: -0.29%, +0.53%
InvThroughput: 26640 -> 26895 (+0.96%); split: -0.48%, +1.44%
VClause: 425 -> 371 (-12.71%)
SClause: 982 -> 981 (-0.10%); split: -0.92%, +0.81%
Copies: 2072 -> 1939 (-6.42%); split: -6.52%, +0.10%
PreVGPRs: 1553 -> 1537 (-1.03%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>

nir/opt_large_constants: Add Small constant handling

Adds handling for constant arrays that can be lowered to
'(imm >> bit_index) & bit_mask' instead of constant loads.

RADV fossils:

Totals from 70 (0.05% of 131205) affected shaders:
Instrs: 31441 -> 31260 (-0.58%); split: -0.59%, +0.02%
CodeSize: 172104 -> 170568 (-0.89%)
VGPRs: 2608 -> 2616 (+0.31%)
Latency: 296687 -> 280859 (-5.33%); split: -5.34%, +0.00%
InvThroughput: 65491 -> 65696 (+0.31%); split: -0.11%, +0.42%
VClause: 671 -> 646 (-3.73%)
SClause: 1014 -> 964 (-4.93%)
Copies: 1742 -> 1564 (-10.22%); split: -10.51%, +0.29%
PreSGPRs: 2039 -> 2036 (-0.15%)
PreVGPRs: 2014 -> 2017 (+0.15%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>

nir/large_constants: Add read/write_const_values helpers

The write helper is just pulling code we already have out into a helper
and flipping the order of the loop and the switch.  The read helper will
be useful in the next commit where we add small constant support.  This
keeps the two helpers right next to each other in the file where they're
easy to compare and we can ensure that they stay in sync.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>

nir/large_constants: Use nir_component_mask_t

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>

nil: Add support for G8B8_G8R8_UNORM and B8G8_R8G8_UNORM

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>

nvk: Enable MIDPOINT_CHROMA_SAMPLES_BIT for multi-planar formats only

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>

nvk: Enable SEPARATE_RECONSTRUCTION_FILTER_BIT for multi-planar formats only

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>

nir: Clean up nir_op_is_vec() and its callers

The nir_op_is_vec() helper I added in 842338e2f0bd ("nir: Add a
nir_op_is_vec helper") treats nir_op_mov as a vec even though the
semanitcs of the two are different.  In retrospect, this was a mistake
as the previous three fixup commits show.  This commit splits the helper
into two: nir_op_is_vec() and nir_op_is_vec_or_mov() and uses the
appropriate helper at each call site.  Hopefully, this rename will
encurage any future users of these helpers to think about nir_op_mov as
separate from nir_op_vecN and we can avoid these bugs.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>

nir: Don't handle nir_op_mov in get_undef_mask in opt_undef

It's unnecessary because earlier parts of the pass will ensure that a
mov of undef is turned into an undef.  It's also wrong because
nir_op_mov has different semantics from nir_op_vecN when it comes to how
sources map to destination components.

Fixes: 5f26c21e6246 ("nir: Expand opt_undef to handle undef channels in a store intrinsic")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>

nir: Handle nir_op_mov properly in opt_shrink_vectors

If the opcode is a mov, it falls into the nir_alu_src_is_trivial_ssa
case, not the vec case.

Fixes: 94eff7ccd866 ("nir: shrink phi nodes in nir_opt_shrink_vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>

nir: Fix nir_op_mov handling in nir_collect_src_uniforms

For mov we need to follow the swizzle for the destination component, not
grab swizzle[0] for some random source.

Fixes: a406fff78a57 ("nir/inline_uniforms: support vector uniform")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>

nir: Rework nir_scalar_chase_movs a bit

The cases in the if are the same as the cases we're using for the early
break.  Just check the things and break if it's not a handleable case.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>

radv: vectorize scratch access

fossil-db (gfx1100):
Totals from 20 (0.01% of 133461) affected shaders:
Instrs: 49421 -> 49134 (-0.58%)
CodeSize: 251668 -> 249604 (-0.82%); split: -0.83%, +0.01%
Latency: 178126 -> 178412 (+0.16%); split: -0.16%, +0.32%
InvThroughput: 23565 -> 23646 (+0.34%); split: -0.05%, +0.39%
VClause: 957 -> 943 (-1.46%)
Copies: 5770 -> 5801 (+0.54%); split: -0.36%, +0.90%
PreVGPRs: 1368 -> 1359 (-0.66%)

Regressions seem to be a couple of cases of bad RA luck.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>

radv: vectorize RT stack access

fossil-db (gfx1100):
Totals from 10 (0.01% of 133461) affected shaders:
MaxWaves: 176 -> 174 (-1.14%)
Instrs: 39260 -> 38710 (-1.40%)
CodeSize: 202272 -> 197288 (-2.46%)
VGPRs: 888 -> 900 (+1.35%)
Latency: 82306 -> 81762 (-0.66%); split: -0.68%, +0.02%
InvThroughput: 11182 -> 11158 (-0.21%); split: -0.52%, +0.30%
VClause: 721 -> 700 (-2.91%)
SClause: 1147 -> 1148 (+0.09%); split: -0.17%, +0.26%
Copies: 3625 -> 3891 (+7.34%)
PreVGPRs: 819 -> 845 (+3.17%); split: -0.37%, +3.54%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>

nir/opt_load_store_vectorize: support scratch access

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>

nir/lower_shader_calls: fix align_offset

I don't think this does anything at the moment, because all accesses are
scalar aligned.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>

radv/gfx11: re-enable 0001/1110 clear values

Since 87444bb7ab4b27b1394af2ac2592110b6500352b, vi_alpha_is_on_msb always
returned false here. The new version matches radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>

radv: support 128bpp comp-to-single with all colors

Previously, it was restricted to clear colors where R==G==B, but it seems
to work if that isn't the case.

This restriction was probably a leftover from before comp-to-single.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>

radv: fix 128bpp comp-to-single clears

We were clearing GB to A, instead of R.

This fixes some red tinting in Overwatch 2 when shadow quality is set to
"Ultra".

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 7451eb1d6112 ("radv: implement DCC fast clears with comp-to-single")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9446
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>

radv: disable 64-bit color attachments

These work in some circumstances (dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc),
but I'm not sure if they work in all, blending certainly doesn't work and
this probably wasn't intended in the first place.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 01bd012edd20 ("amd: fix 64-bit integer color image clears")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>

meson: Rename dri-vdpau.dyn to dri.dyn

File 'src/gallium/targets/dri-vdpau.dyn' is now shared by multiple
targets and not just VDPAU, so renamed it to 'dri.dyn' as suggested
by Marek Olšák.

Related link:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23177#note_2030493

Suggested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24569>

turnip: Move sysmem clears to the first subpass that uses them.

This is a partial fix for the case where
VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT and the aliased attachment clears
the attachment that was last used in a previous subpass (we have to move
the stores to the last used subpass, as well).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>

turnip: Move gmem clears and loads to the first subpass that uses them.

This will help us share gmem space between attachments that aren't used at
the same time.  It's also a correctness fix for
VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT, because they're supposed to
happen at the first subpass using the attachment, not the start of the
renderpass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>

turnip: Save the renderpass's clear values in the cmdbuf state.

For delaying clears to subpass begin time, I needed to save these until
later.  Turns out this cleans up a good bit of threading these values all
through the command buffer setup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>

turnip: Skip emitting empty CP_COND_REG_EXEC.

If we ended up emitting no code to be conditionally run, then drop the
whole conditional exec packet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>

turnip: Track the first/last subpass an attachment is used in.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>

vulkan/util: Make multialloc succeed with 0 allocations.

I wanted to use it for the attachments and clear values of a
vkCmdBeginRenderPass(), but both can be 0 count.  In that case, we would
end up with vk_default_alloc(0,0) because nothing had set the alignment,
and assertion fail instead of allocating 0 bytes.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>

Revert "intel/fs: only avoid SIMD32 if strictly inferior in throughput"

This reverts commit 6b494745be0900a67004d6f3e4b730c3cd67da79.

The logic is not entirely correct: the comparison is between two
static-analysis estimates of a dynamic system with variables that aren't
captured by the shader source, so using ">" will always have greater potential
to cause regressions whenever the performance difference between the two builds
is something not captured by the static model, no matter how much the model is
improved.

Reference: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9262
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24615>

iris: ensure stalling pipe control before fast clear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24718>

etnaviv: fix null pointer dereference

Fixes: 734b15186bf ("etnaviv: Stop passing around nir_dest")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24717>

docs: upgrade bootstrap to 5.3.1

Bootstrap 5.3.1 is out, implementing the color fix we introduced to make
dark-mode more readable. So let's update to that, and drop our override.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24670>

nouveau: add exported GEM handles to the global list

Adding GEM handles to the global list is necessary to allow
maintaining a single reference count for handles that are shared
between multiple buffer objects.

Since exported handles can end up being shared with other buffer
objects, as in the case that drmPrimeHandleToFD() and gbm_bo_import()
are called externally to Mesa, they too must be added to the global
list.

Unfortunately, doing this properly requires a new libdrm API. Use
the best possible option for now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9552

Signed-off-by: Dor Askayo <dor.askayo@gmail.com>
Acked-by: Karol Herbst <git@karolherbst.de>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24648>

nv50/ir: Remove few nvc0 specific defines from nv50-specific header.

Compile, and run-tested on nv92

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7259>

nv50: fix code uploads bigger than 0x10000 bytes

The hardware has a max limit on how much data we can upload in one go via
the 2D engine. Just split the uploads up.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9571
Acked-by: M Henning <drawoc@darkrefraction.com>
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24706>

radeonsi: remove unused arg of get_tcs_tes_buffer_address

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: part mode standalone tcs support aco compile

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: add si_aco_build_shader_part

Now it only has tcs epilog build, will add more prolog/epilog to it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: change si_fill_aco_options args

Prepare to be shared with prolog/epilog generation which
does not have si_shader param.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: add si_get_tcs_epilog_args

For shared with aco tcs epilog creation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: remove separate_prolog arg from prolog/epilog build

It's always true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: extract si_llvm_build_shader_part

Prepare for aco code path.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: fill part mode tcs aco shader info

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: share si_get_tcs_out_patch_stride with aco

Move it out of llvm to be shared with aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: support upload multi part shader binary

Need to split shader binary into exec and data part, then combine
exec and data of all shader parts separately. So const data symbols
in code need to be relocated.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

radeonsi: add exec_size to shader binary

Used by aco binary to split exec code and const data when combine
multi part shader binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>

aco: use semantic location as io temp index

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

ac/nir/tess: move tess factor output out of control flow

For radeonsi aco compile which can't handle outputs without
nir_lower_io_to_temporaries().

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco,radeonsi: save const addr to symbol

For radeonsi to relocation const data when combine multiple
shader parts to a single one. So the final shader binary will
begin with exec code of all parts then const data.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: skip scratch init when no scratch arg provide

epilog does not use scratch so has no scratch arg.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: don't emit s_endpgm for tcs with epilog

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: add tcs epilog generation for radeonsi

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: add pending_lds_access option for insert waitcnt

For tcs epilog to add p_barrier at the beginning to sync
main shader part tess factor LDS write.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: allow tcs with epilog to keep nir store output instruction

Used to same tess factor outputs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: add tcs end regs for epilog usage

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: move jump to epilog out of ic_merged_wave_info

TCS may be wrapped with if/else when merged shader. Jump
to epilog or end with regs should not be inside it.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aco: add p_end_with_regs pseudo instruction

Used by radeonsi shader parts to pass args from one part to another.
It has variable number of operands to reserve fixed registers with
wanted value.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>

aux/trace: trace video_buffer method return vals

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: unwrap refrence frames in picture_desc

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: wrap video_codec & video_buffer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: add context video methods

Preliminary support without wrapping video_codec or video_buffer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: add screen video methods

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: fix set_hw_atomic_buffers method name

Fixes: b2dc63ed8ce ("aux/trace: Add pipe_context::set_hw_atomic_buffers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: move trace_sample_view logic

it's defined in tr_texture, so it makes sense and is more
re-usable to have it's logic there.
Also documented the magic number used for private refcounting

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: deduplicate enum dump macro work

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

aux/trace: skip multi-line comments in enums2names

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>

gallium/dri: fix dri2_from_names

`createImageFromNames` uses fourcc, not dri_image_formats

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8547
Fixes: 433ca3127a3 ("st/dri: replace format conversion functions with single mapping table")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24597>

intel/isl: Remove Wa_22011186057

This is a ADL-P workaround of a pre-production stepping, with RPL-P
already being sold we can remove this workaround.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24699>

intel/isl: Remove unknown workaround

The way this workaround is implemented, it is being applied to all
gfx 12 platforms(TGL, ADL, RKL, RPL, DG1, DG2 and MTL) but it was
supposed to be fixed in TGL B0.
Unfortunately I did not found any workaround number that would match it.

But as all released platforms don't ship to customers with revision == 0
this workaround was never being applied and can be safely removed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24699>

nir: s/nir_instr_ssa_def/nir_instr_def/

Generated by sed:

    sed -i -e 's/nir_instr_ssa_def/nir_instr_def/g' src/**/*.h src/**/*.c src/**/*.cpp

Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24703>

nir: s/live_ssa_def/live_def/

Generated mostly with sed:

    sed -i -e 's/live_ssa_def/live_def/g' src/compiler/nir/nir.h src/compiler/nir/*.c

Plus three fixups in various Intel drivers.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24703>

nir s/nir_get_ssa_scalar/nir_get_scalar/

Generated with sed:

    sed -i -e 's/nir_get_ssa_scalar/nir_get_scalar/g' src/**/*.h src/**/*.c src/**/*.cpp

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24703>

nir: Rename nir_instr_type_ssa_undef to nir_instr_type_undef

We already renamed the type, we just need to rename the enum and the
casting helper functions.

Generated with sed:

    sed -i -e 's/nir_instr_type_ssa_undef/nir_instr_type_undef/g' src/**/*.h src/**/*.c src/**/*.cpp
    sed -i -e 's/nir_instr_as_ssa_undef/nir_instr_as_undef/g' src/**/*.h src/**/*.c src/**/*.cpp

and two tiny whitespace fixups in lima.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24703>

zink: use real A8_UNORM when possible

this is tricky because drivers are exposing their native support, but
that support may not fit the specific needs of the format

as such, (almost) every use of format where alpha emulation workarounds are
present now need to add a second layer of workarounds in order to handle
the case of possibly-genuine A8 (which might also be emulated A8 even if
the driver supports A8 for some things)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24685>

zink: use maintenance5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24685>