Francisco Jerez [Tue, 17 May 2016 14:02:38 +0000 (16:02 +0200)]
clover/llvm: Factor out compiler option tokenization.
Reviewed-by: Serge Martin <edb+mesa@sigluy.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Francisco Jerez [Sat, 25 Jun 2016 23:52:55 +0000 (16:52 -0700)]
clover/llvm: Factor out target string parsing.
Reviewed-by: Serge Martin <edb+mesa@sigluy.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Francisco Jerez [Sat, 25 Jun 2016 23:52:11 +0000 (16:52 -0700)]
clover/llvm: Collect #ifdef mess into a separate file.
This gets rid of most ifdef's from the invocation.cpp code -- Only a
couple of them are left which will be removed differently in the
following commits.
Reviewed-by: Serge Martin <edb+mesa@sigluy.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Francisco Jerez [Tue, 17 May 2016 14:02:35 +0000 (16:02 +0200)]
clover/llvm: Drop dead code.
This ifdef'ed out code was meant to handle compilation into TGSI, but
it doesn't seem likely that it will ever be useful even if the TGSI
back-end is resurrected because the TGSI bitcode can just be plumbed
through in ELF format and dealt with as a regular "native" back-end.
Reviewed-by: Serge Martin <edb+mesa@sigluy.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Francisco Jerez [Tue, 28 Jun 2016 06:24:59 +0000 (23:24 -0700)]
clover/llvm: Drop support for LLVM < 3.6.
Reviewed-by: Serge Martin <edb+mesa@sigluy.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Serge Martin [Tue, 17 May 2016 14:02:33 +0000 (16:02 +0200)]
clover: Bump required LLVM version to 3.6.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Ilia Mirkin [Fri, 8 Jul 2016 18:24:38 +0000 (14:24 -0400)]
mesa: set _NEW_BUFFERS when updating texture bound to current buffers
When a glTexImage call updates the parameters of a currently bound
framebuffer, we might miss out on revalidating whether it is complete.
Make sure to set _NEW_BUFFERS which will trigger the revalidation in
that case.
Also while we're at it, fix the fb parameter passed in to the eventual
RenderTexture call.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94148
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Ilia Mirkin [Fri, 8 Jul 2016 16:35:11 +0000 (12:35 -0400)]
meta/texsubimage: tex_image is always non-null, avoid confusing code
Probably a copy-paste from mesa_meta_pbo_GetTexSubImage where tex_image
may apparently be null.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Ilia Mirkin [Fri, 8 Jul 2016 03:46:28 +0000 (23:46 -0400)]
st/mesa: return appropriate mesa format for ETC texture formats
Even when the backend driver does not support ETC formats, we handle the
decoding into an uncompressed backing texture. However as far as core
mesa is concerned, it's an ETC texture and we should return the relevant
ETC mesa format. This condition can get hit when using glTexStorage to
create the texture object.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Fri, 8 Jul 2016 22:41:03 +0000 (18:41 -0400)]
mesa: etc2 online compression is unsupported, don't attempt it
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Ben Skeggs [Sat, 9 Jul 2016 00:06:44 +0000 (10:06 +1000)]
nvc0: initial support for GP100 GPUs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Samuel Pitoiset [Mon, 11 Jul 2016 20:25:05 +0000 (22:25 +0200)]
nvc0: use a define for the driver constant buffer size
This might avoid mistakes if the size is bumped in the future.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 11 Jul 2016 19:26:25 +0000 (21:26 +0200)]
nvc0: fix the driver cb size when draw parameters are used
The size of the driver constant buffer for each stage should be 2048
and not 512 because it has been increased recently for buffers/images.
While we are at it, do the same change for indirect draws.
This fixes all ARB_shader_draw_parameters tests on GM107.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Sun, 10 Jul 2016 14:19:46 +0000 (16:19 +0200)]
nvc0/ir: fix images indirect access on Fermi
This fixes the following piglits:
arb_arrays_of_arrays-basic-imagestore-mixed-const-non-const-uniform-index
arb_arrays_of_arrays-basic-imagestore-mixed-const-non-const-uniform-index2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Marek Olšák [Fri, 1 Jul 2016 18:43:29 +0000 (20:43 +0200)]
st/mesa: remove st_dump_program_for_shader_db
replaced by MESA_SHADER_CAPTURE_PATH in core Mesa
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 18:09:47 +0000 (20:09 +0200)]
gallivm: set LLVMNoUnwindAttribute on all intrinsics
RadeonSI stats: Mostly 0% difference, but Valley shows a small improvement:
Application Files SGPRs VGPRs SpillSGPR SpillVGPR Code Size LDS Max Waves Waits
unigine_valley 278 0.00 % -0.29 % 0.00 % 0.00 % 0.01 % 0.00 % 0.17 % 0.00 %
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Francesco Ansanelli [Sat, 9 Jul 2016 08:16:29 +0000 (10:16 +0200)]
i965: fix ignored qualifiers warning
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nicolai Hähnle [Sat, 9 Jul 2016 17:44:13 +0000 (19:44 +0200)]
gallium/u_queue: assert that users must wait on fences before destroying them
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Nicolai Hähnle [Sat, 9 Jul 2016 17:40:51 +0000 (19:40 +0200)]
gallium/u_queue: guard fence->signalled checks with fence->mutex
I have seen a hang during application shutdown that could be explained by the
following race condition which this patch fixes:
1. Worker thread enters util_queue_fence_signal, sets fence->signalled = true.
2. Main thread calls util_queue_job_wait, which returns immediately.
3. Main thread deletes the job and fence structures, leaving garbage behind.
4. Worker thread calls pipe_condvar_broadcast, which gets stuck forever because
it is accessing garbage.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Chad Versace [Thu, 7 Jul 2016 23:04:59 +0000 (16:04 -0700)]
anv/dump: Fix post-blit memory barrier
Swap srcAccessMask and dstAccessMask.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chad Versace [Thu, 7 Jul 2016 23:04:58 +0000 (16:04 -0700)]
anv/dump: Fix vkCmdPipelineBarrier flags
'true' is not valid for VkDependencyFlags.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Wed, 15 Jun 2016 23:13:46 +0000 (16:13 -0700)]
anv/dump: Add support for dumping framebuffers
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 15 Jun 2016 22:08:09 +0000 (15:08 -0700)]
anv/dump: Add a barrier for the source image
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 15 Jun 2016 22:01:45 +0000 (15:01 -0700)]
anv/dump: Refactor the guts into helpers
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 15 Jun 2016 21:30:07 +0000 (14:30 -0700)]
anv/dump: Use anv_minify instead of hand-rolling it
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 14 Jun 2016 00:08:59 +0000 (17:08 -0700)]
anv/dump: Take an aspect in dump_image_to_ppm
Reviewed-by: Chad Versace <chad.versace@intel.com>
Nicolai Hähnle [Fri, 8 Jul 2016 17:12:00 +0000 (19:12 +0200)]
radeonsi: fix bad assertion in si_emit_sample_mask
The blitter sets mask == 1, which is fine since it doesn't use smoothing.
Fixes a regression introduced in commit
5bcfbf91.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Matt Turner [Thu, 23 Jun 2016 06:11:27 +0000 (23:11 -0700)]
glx: Fix for commit
2c86668694.
Ian suggested these changes in his review and I made them, but I pushed
the old version of the patch.
Emil Velikov [Fri, 8 Jul 2016 23:09:51 +0000 (00:09 +0100)]
docs: add news item and link release notes for 12.0.0/12.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Jul 2016 23:02:13 +0000 (00:02 +0100)]
docs: add sha256 checksums for 12.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
edfc17a19a17e8dae41a703a9cb4b9eb3c255c34)
Emil Velikov [Fri, 8 Jul 2016 22:45:44 +0000 (23:45 +0100)]
docs: add release notes for 12.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
04277f058d00238937e664cf546c43b16cea7b2b)
Emil Velikov [Fri, 8 Jul 2016 22:47:39 +0000 (23:47 +0100)]
docs: add sha256 checksums for 12.0.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
3a146a789c5aa45e0de52bff764c2b371dd253aa)
Emil Velikov [Thu, 7 Jul 2016 12:39:06 +0000 (13:39 +0100)]
docs: Update 12.0.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
8b06176f310f65628ce136b90a99005278ba5e0d)
Matt Turner [Thu, 23 Jun 2016 06:11:27 +0000 (23:11 -0700)]
glx: Undo memory allocation checking damage.
This partially reverts commit
d41f5396f3cb619729021390c273f838d92f11fb.
That untested commit broke the tex-skipped-unit piglit test and the
arbvparray Mesa demo when run with indirect GLX.
state->array_state is used during initialization, so its assignment cannot be
moved to the end of the function.
The backtrace looked like:
Program received signal SIGSEGV, Segmentation fault.
0x00007ffff77c7a5c in __glXGetActiveTextureUnit (state=0x6270e0) at indirect_vertex_array.c:1952
1952 return state->array_state->active_texture_unit;
(gdb) bt
0 0x00007ffff77c7a5c in __glXGetActiveTextureUnit (state=0x6270e0) at indirect_vertex_array.c:1952
1 0x00007ffff77cbf62 in get_client_data (gc=0x626f50, cap=34018, data=0x7fffffffd7a0) at single2.c:159
2 0x00007ffff77cce51 in __indirect_glGetIntegerv (val=34018, i=0x7fffffffd830) at single2.c:498
3 0x00007ffff77c4340 in __glXInitVertexArrayState (gc=0x626f50) at indirect_vertex_array.c:193
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Colin McDonald [Thu, 23 Jun 2016 02:19:30 +0000 (19:19 -0700)]
glx: Fix indirect multi-texture GL_DOUBLE coordinate arrays.
There is no draw arrays protocol support for multi-texture coordinate
arrays, so it is implemented by sending batches of immediate mode
commands from emit_element_none in indirect_vertex_array.c. This sends
the target texture unit (which has been previously setup in the
array_state header field), followed by the texture coordinates. But for
GL_DOUBLE coordinates the texture unit must be sent *after* the texture
coordinates. This is documented in the glx protocol description, and can
also be seen in the indirect.c immediate mode commands generated from
gl_API.xml. Sending the target texture unit in the wrong place can crash
the remote X server.
To fix this required some more extensive changes to
indirect_vertex_array.c and indirect_vertex_array_priv.h, in order to
remove the texture unit value out of the array_state "header" field, and
send it separately.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61907
Colin McDonald [Thu, 23 Jun 2016 02:11:55 +0000 (19:11 -0700)]
glx: Correct opcode typos in __indirect_glTexCoordPointer.
At the same time, replace opcode numbers with names in
__indirect_glVertexAttribPointer.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61907
Colin McDonald [Thu, 23 Jun 2016 02:07:49 +0000 (19:07 -0700)]
glx: Call __glXInitVertexArrayState() with a usable gc.
For each indirect context the indirect vertex array state must be initialised
by __glXInitVertexArrayState in indirect_vertex_array.c. As noted in the
routine header it requires that the glx context has been setup prior to the
call, in order to test the server version and extensions.
Currently __glXInitVertexArrayState is called from indirect_bind_context in
indirect_glx.c, as follows:
state = gc->client_state_private;
if (state->array_state == NULL) {
glGetString(GL_EXTENSIONS);
glGetString(GL_VERSION);
__glXInitVertexArrayState(gc);
}
But, the gc context is not yet usable at this stage, so the server queries
fail, and __glXInitVertexArrayState is called without the server version and
extension information it needs. This breaks multi-texturing as
glXInitVertexArrayState doesn't get GL_MAX_TEXTURE_UNITS. It probably also
breaks setup of other arrays: fog, secondary colour, vertex attributes.
To fix this I have moved the call to __glXInitVertexArrayState to the end of
MakeContextCurrent in glxcurrent.c, where the glx context is usable.
Fixes a regression caused by commit
4fbdde889c. Fixes ARB_vertex_program
usage in the arbvparray Mesa demo when run with indirect GLX and also
the tex-skipped-unit piglit test when run with indirect GLX.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61907
Christian König [Thu, 7 Jul 2016 09:27:21 +0000 (11:27 +0200)]
radeon/uvd: simplify sending context buffer message
Just send it whenever it is allocated.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Christian König [Thu, 7 Jul 2016 09:22:32 +0000 (11:22 +0200)]
radeon/uvd: fix contex buffer destruction in the error path
Destroying a not allocated buffer is harmless.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Christian König [Thu, 7 Jul 2016 09:20:30 +0000 (11:20 +0200)]
radeon/uvd: move polaris fw check into radeon_video.c v2
It's actually not very clever to claim to support H.264
and then fail to create a decoder.
v2: prefix FW macro with UVD_.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Christian König [Thu, 7 Jul 2016 08:56:23 +0000 (10:56 +0200)]
radeon/video: fix coding style in radeon_video.c v2
v2: fix other tabs as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Brian Paul [Wed, 6 Jul 2016 23:24:18 +0000 (17:24 -0600)]
svga: simplify/fix 1D/2D array resource copies
Fixes the one of the piglit arb_copy_image-targets tests for 1D arrays.
Previously, we were applying the 1D array z/face adjustment twice.
Also simplify the copy_region_vgpu10() function. It never has to copy
multiple array layers/slices. The Mesa code for glCopyImageSubData does
the loop over slices/faces.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 6 Jul 2016 23:10:52 +0000 (17:10 -0600)]
mesa: print number of samples in renderbuffer_storage error msg
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Brian Paul [Wed, 6 Jul 2016 23:21:36 +0000 (17:21 -0600)]
svga: remove unused variable
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 6 Jul 2016 21:25:55 +0000 (15:25 -0600)]
svga: add dumping for more device commands
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Wed, 6 Jul 2016 21:25:23 +0000 (15:25 -0600)]
svga: silence a couple unused variable warnings
Signed-off-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Thu, 30 Jun 2016 20:08:25 +0000 (13:08 -0700)]
svga: rebind using render target surfaces in hw draw state
Currently when we rebind framebuffer resources at the beginning of
the command buffer, we use the color buffer surfaces saved in the context
hw clear state. But the surfaces could be different from the actual
emitted render target surfaces if any of the color buffer surfaces
is also used for shader resource, in that case, we create
a backed surface for the collided render target surface. So to rebind
the framebuffer resources correctly, use the render target surfaces saved
in the context hw draw state.
Tested with Heaven, Lightsmark2008, MTT piglit, glretrace, conform.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Tue, 8 Mar 2016 19:18:51 +0000 (11:18 -0800)]
svga: invalidate gb surface before it is reused
With this patch, a guest-backed surface will be invalidated
using the SVGA_3D_CMD_INVALIDATE_GB_SURFACE command before
the surface is reused. This fixes the updating dirty image error
from the device when a surface is reused.
v2: Instead of invalidating the surface when it is reused,
send the invalidate command before the surface is put into
the recycle pool.
v3: (1) surface invalidate is a noop operation in Linux winsys, since
surface invalidation is not needed for DMA path.
(2) Instead of invalidating the surface content in
svga_screen_surface_destroy() when a surface is to be destroyed,
it is done in svga_screen_cache_flush() when the surface is
no longer referenced in a command buffer and is ready to
be moved to the unused list. At this point, the surface will
be moved to the invalidate list. When the surface invalidation
is submitted, the surface will be moved to the unused list.
Tested with piglit, glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Brian Paul [Tue, 17 May 2016 16:44:01 +0000 (10:44 -0600)]
svga: fix use of provoking vertex control
If the SVGA3D_DEVCAP_DX_PROVOKING_VERTEX query returns false, never
define rasterizer state objects with provokingVertexLast set. Despite
what the device reports, it may interpret the provokingVertexLast flag
anyway. This fixes an issue when using capability clamping.
Tested with piglit provoking-vertex and glsl-fs-flat-color tests.
VMware bug 1550143.
Reviewed-by: <charmainel@vmware.com>
Nayan Deshmukh [Tue, 5 Jul 2016 18:17:56 +0000 (23:47 +0530)]
vl: add half pixel to v_tex before adding offsets
Since pixel center lies at 0.5, add half_pixel to vtex
before adding offsets to it.
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Samuel Pitoiset [Tue, 5 Jul 2016 12:01:34 +0000 (14:01 +0200)]
nvc0/ir: remove unused resource info loading helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 5 Jul 2016 12:01:33 +0000 (14:01 +0200)]
nvc0/ir: refactor the surfaces info loading logic
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 5 Jul 2016 12:01:32 +0000 (14:01 +0200)]
nvc0/ir: move the shift left op inside loadTexHandle()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Nicolai Hähnle [Wed, 6 Jul 2016 21:51:05 +0000 (23:51 +0200)]
radeonsi: disable multi-threading when shader dumps are enabled
Otherwise, shader dumps can become interleaved and unusable.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 7 Jul 2016 07:28:25 +0000 (09:28 +0200)]
radeonsi: use multi-threaded compilation in debug contexts
We only have to stay single-threaded when debug output must be synchronous.
This yields better parallelism in shader-db runs for me.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 7 Jul 2016 07:25:31 +0000 (09:25 +0200)]
st/mesa: set debug callback async flag
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 7 Jul 2016 07:11:17 +0000 (09:11 +0200)]
gallium: add async flag to pipe_debug_callback
v2: fix typo db -> cb
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Jul 2016 14:55:08 +0000 (16:55 +0200)]
radeonsi: catch a potential state tracker error with non-MSAA FBs
At least st/mesa ensures this, so I'd rather not handle deviations in radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Jul 2016 14:33:43 +0000 (16:33 +0200)]
radeonsi: explicitly choose center locations for 1xAA on Polaris
Unlike SC, the small primitive filter does not automatically use center
locations in 1xAA mode, so this is needed to avoid artifacts caused by
the small primitive filter discarding triangles that it shouldn't.
As a side effect of how the effective number of samples is now calculated,
this patch also avoids submitting the sample locations for line/poly smoothing
when they're not really needed.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Jul 2016 12:26:47 +0000 (14:26 +0200)]
r600g: call cayman_emit_msaa_sample_locs only when needed
In the case of nr_samples <= 1, that function is (currently) a no-op anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Thu, 7 Jul 2016 18:50:44 +0000 (11:50 -0700)]
mesa: Mark R*32F formats as filterable when an extension is present.
GL_OES_texture_float_linear marks R32F, RG32F, RGB32F, and RGBA32F
as texture filterable.
Fixes glGenerateMipmap GL errors when visiting a WebGL demo in Chromium:
http://www.iamnop.com/particles
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Engestrom [Wed, 6 Jul 2016 21:02:42 +0000 (22:02 +0100)]
i965/blorp: fix indentation level
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Francisco Jerez [Fri, 1 Jul 2016 00:49:18 +0000 (17:49 -0700)]
i965: Fix remaining flush vs invalidate race conditions in brw_emit_pipe_control_flush.
This hardware race condition has caused problems several times already
(see "i965: Fix cache pollution race during L3 partitioning set-up.",
"i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs." and
"i965: intel_texture_barrier reimplemented"). The problem is that
whenever we attempt to both flush and invalidate multiple caches with
a single pipe control command the flush and invalidation happen in
reverse order, so the contents flushed from the R/W caches aren't
guaranteed to become visible from the invalidated caches after the
PIPE_CONTROL command completes execution if some concurrent rendering
workload happened to pollute any of the invalidated R/O caches in the
short window of time between the invalidation and flush.
This makes sure that brw_emit_pipe_control_flush() has the effect
expected by most callers of making the contents flushed from any R/W
caches visible from the invalidated R/O caches.
Cc: "12.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 1 Jul 2016 04:15:26 +0000 (21:15 -0700)]
i965: Make room in the batch epilogue for three more pipe controls.
Review carefully, it sucks to have to keep track of the number of
command packet dwords emitted in the batch epilogue manually. The
MI_REPORT_PERF_COUNT_BATCH_DWORDS calculation was obviously wrong.
Cc: "12.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 1 Jul 2016 02:41:49 +0000 (19:41 -0700)]
i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.
There were two places in the driver doing a pipe control VF cache
flush, one of them was missing this workaround, move it down into
brw_emit_pipe_control_flush to make sure we don't miss it again.
Cc: "12.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Francisco Jerez [Fri, 1 Jul 2016 02:39:24 +0000 (19:39 -0700)]
i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
Shouldn't cause any functional changes at this point, but we have
forgotten to apply this workaround several times in the past, make
sure it doesn't happen again.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Frank Binns [Mon, 20 Jun 2016 08:00:37 +0000 (09:00 +0100)]
egl: restrict swap_available dri2_egl_display field to X11
This field is only ever set and read by the X11 platform.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Guillaume Charifi [Mon, 20 Jun 2016 13:27:33 +0000 (15:27 +0200)]
egl: Fix the bad surface attributes combination checking for pbuffers. (v3)
Fixes a regression induced by commit
a0674ce5c41903ccd161e89abb149621bfbc40d2:
When EGL_TEXTURE_FORMAT and EGL_TEXTURE_TARGET were both specified (and
both != EGL_NO_TEXTURE), an error was instantly triggered, before the
other one had even a chance to be checked, which is obviously not the
intended behaviour.
v2: Full commit hash, remove useless variables.
v3: [chadv] Add Fixes footers.
Fixes: piglit "spec/egl 1.4/eglcreatepbuffersurface and then glclear"
Fixes: piglit "spec/egl 1.4/largest possible eglcreatepbuffersurface and then glclear"
Signed-off-by: Guillaume Charifi <guillaume.charifi@sfr.fr>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Eric Engestrom [Wed, 6 Jul 2016 13:31:31 +0000 (14:31 +0100)]
egl/display: remove unnecessary code and make it easier to read
Remove the two first level `if` as they will always be true, and
flatten the two remaining `if`.
No functional change.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Gurchetan Singh [Thu, 30 Jun 2016 22:20:34 +0000 (15:20 -0700)]
mesa: Make single-buffered GLES representation internally consistent
There are a few places in the code where clearing and reading are done on
incorrect buffers for GLES contexts. See comments for details. This
fixes 75 GLES3 dEQP tests on the surfaceless platform with no regressions.
v2: Corrected unclear comment
v3: Make the change in context.c instead of get.c
v4: Removed whitespace
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Emil Velikov [Thu, 7 Jul 2016 10:51:13 +0000 (11:51 +0100)]
bugzilla_mesa.sh: Drop "Bug " from sed command
After a recent Bugzilla update the word is no longer in the title. Thus
the script ended up producing bogus HTML.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Akihiko Odaki [Sun, 26 Jun 2016 01:54:35 +0000 (10:54 +0900)]
mesa: don't install GLX files if GLX is not built
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Akihiko Odaki <akihiko.odaki.4i@stu.hosei.ac.jp>
[Emil Velikov: Drop guards around dri_interface.h, add stable tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Timothy Arceri [Wed, 15 Jun 2016 00:43:12 +0000 (10:43 +1000)]
nir: add glsl_dvec_type() helper
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mathias Fröhlich [Fri, 1 Jul 2016 05:13:46 +0000 (07:13 +0200)]
osmesa: Export OSMesaCreateContextAttribs.
Since the function is exported like any other
public api function and put in the header
as if you could link against it, export it also
from shared objects.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Timothy Arceri [Wed, 6 Jul 2016 03:14:37 +0000 (13:14 +1000)]
i965: consolidate generation check
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Wed, 6 Jul 2016 02:41:02 +0000 (12:41 +1000)]
i965: don't copy VS attribute work arounds for HSW+
These workarounds are not required for HSW and above so stop
copying them at VS key generation which is called at draw time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 10 Jun 2016 11:57:49 +0000 (21:57 +1000)]
i965: add double packing support to tess stages
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 10 Jun 2016 04:23:58 +0000 (14:23 +1000)]
i965: add double support packing support to gs inputs
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 10 Jun 2016 02:50:45 +0000 (12:50 +1000)]
nir: add glsl_double_type() helper
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 22 May 2016 12:48:53 +0000 (22:48 +1000)]
i965: add indirect packing support to gs load inputs
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Mon, 23 May 2016 06:32:50 +0000 (16:32 +1000)]
i965: add indirect packing support for tcs and tes
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 20 May 2016 00:29:06 +0000 (10:29 +1000)]
i965: add component packing support for tcs
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 19 May 2016 06:58:48 +0000 (16:58 +1000)]
i965: add component packing support for tes
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 19 May 2016 05:58:51 +0000 (15:58 +1000)]
i965: add component packing support for gs
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Wed, 18 May 2016 00:26:05 +0000 (10:26 +1000)]
nir: use the same driver location for packed varyings
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Mon, 23 May 2016 06:46:46 +0000 (16:46 +1000)]
nir: add new intrinsic field for storing component offset
This offset is used for packing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Wed, 6 Jul 2016 16:09:15 +0000 (17:09 +0100)]
i965/docs: update Intel Linux Graphics URLs
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Chad Versace [Wed, 6 Jul 2016 20:13:18 +0000 (13:13 -0700)]
anv: gitignore anv_timestamp.h
Tom Stellard [Tue, 17 May 2016 18:10:51 +0000 (18:10 +0000)]
radeon/llvm: Use alloca instructions for larger arrays
We were storing arrays in vectors, which was leading to some really bad
spill code for large arrays. allocas instructions are a better fit for
arrays and LLVM optimizations are more geared toward dealing with
allocas instead of vectors.
For arrays that have 16 or less 32-bit elements, we will continue to use
vectors, because this will force LLVM to store them in registers and
use indirect registers, which is usually faster for small arrays.
In the future we should use allocas for all arrays and teach LLVM
how to store allocas in registers.
This fixes the piglit test:
spec/glsl-1.50/execution/geometry/max-input-component
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Tue, 17 May 2016 14:48:42 +0000 (14:48 +0000)]
radeon/llvm: Add helpers for loading and storing data from arrays.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Tue, 17 May 2016 17:51:00 +0000 (17:51 +0000)]
radeon/llvm: Remove uses_temp_indirect_addressing() function
bld->indirect_files is never set, so this function always returns false.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Emil Velikov [Wed, 6 Jul 2016 15:18:21 +0000 (16:18 +0100)]
anv: vulkan: remove the anv_device.$(OBJEXT) rule
Atm the actual rule will expand to foo.o which is used for static
libraries only.
Thus the automake manual recommendation [to use OBJEXT] won't help us,
since since we're working with a shared library.
Thus let's 'demote' the file and add it back to BUILT_SOURCES. This will
manage all the complexity for us, at the (existing expense) of working
only with the all, check and install targets.
The crazy (why the issue was hard to spot):
If the dependencies (.deps/*.Plo) are already created one can alter the
anv_device.$(OBJEXT) line and/or nuke it all together. That won't lead
to any warnings/issues, even though the Makefile is regenerated.
Moral of the story:
Always rm -rf top_builddir or don't resolve the dependencies manually
and use BUILT_SOURCES.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96825
Fixes:
d7a604c3f7a ("anv: use cache uuid based on the build timestamp.")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Rob Clark [Tue, 5 Jul 2016 19:41:26 +0000 (15:41 -0400)]
vbo: fix attr reset
In bc4e0c4 (vbo: Use a bitmask to track the active arrays in vbo_exec*.)
we stopped looping over all the attributes and resetting all slots.
Which exposed an issue in vbo_exec_bind_arrays() for handling GENERIC0
vs. POS.
Split out a helper which can reset a particular slot, so that
vbo_exec_bind_arrays() can re-use it to reset POS.
This fixes an issue with 0ad (and possibly others).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Rob Clark [Sat, 2 Jul 2016 12:02:51 +0000 (08:02 -0400)]
list: fix list_replace() for empty lists
Before, it would happily copy list_head next/prev (ie. pointer to the
*from* list_head), leaving things in a confused state and causing much
mayhem.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Sun, 26 Jun 2016 17:56:42 +0000 (13:56 -0400)]
gallium: un-inline pipe_surface_desc
Want to re-use this struct, so un-inline it.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Sat, 11 Jun 2016 13:21:10 +0000 (09:21 -0400)]
gallium/util: make util_copy_framebuffer_state(src=NULL) work
Be more consistent with the other u_inlines util_copy_xyz_state()
helpers and support NULL src.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 1 Jul 2016 14:18:34 +0000 (16:18 +0200)]
winsys/amdgpu: avoid flushed depth when possible
If a depth/stencil texture has no mipmaps, we can always get a layout that is
compatible with DB and TC.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 30 Jun 2016 18:04:54 +0000 (20:04 +0200)]
gallium/radeon: add depth/stencil_adjusted output to surface computation
This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga,
though it's basically a function of the memory configuration so could affect
other parts as well.
Fixes piglit "unaligned-blit * stencil downsample" and various
"fbo-depth-array *stencil*" tests.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 30 Jun 2016 15:22:54 +0000 (17:22 +0200)]
gallium/radeon: allocate only the required plane for flushed depth
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 29 Jun 2016 12:30:37 +0000 (14:30 +0200)]
radeonsi: decompress to flushed depth texture when required
v2: s/dirty_level_mask/stencil_dirty_level_mask/ in stencil case
Reviewed-by: Marek Olšák <marek.olsak@amd.com>