wlei [Tue, 20 Sep 2022 16:37:43 +0000 (09:37 -0700)]
[llvm-profgen] Remove CommaSeparated option from perf file cl
There could be comma in one perf file path, since at this point it only support one file as input, there is no need for the `llvm::cl::MiscFlags::CommaSeparated` option.
Reviewed By: hoy, wenlei
Differential Revision: https://reviews.llvm.org/D134287
natashaknk [Wed, 21 Sep 2022 16:29:17 +0000 (09:29 -0700)]
[mlir][tosa] Revert added support for dynamic height/weight for pooling in tosa-to-linalg
Partial rollback to D133389
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D134370
Joel E. Denny [Wed, 21 Sep 2022 16:26:11 +0000 (12:26 -0400)]
[lit] Increase FileCheck verbosity temporarily
This is to help debug the failure
28412d1800e3 caused and
f47a5df92d48
failed to fix at:
<https://lab.llvm.org/buildbot/#/builders/216/builds/10117>
Konstantina [Mon, 1 Aug 2022 23:14:39 +0000 (16:14 -0700)]
[NFC][NewGVN] Remove OpIsSafeForPHIOfOpsHelper()
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D130949
Ashay Rane [Mon, 19 Sep 2022 07:38:47 +0000 (02:38 -0500)]
[llvm] prefix linker flag on non-MSVC compilers with `-Wl,`
Prior to this patch, a Windows build of llvm-lto using clang failed with
the error: `LTO.def: unknown file type`. The reason for this failure is
that .DEF files are used by the linker not by the clang compiler. The
MSVC compiler+linker handles this transparently, but if we're using
clang (or gcc), then we need to tell the compiler to forward this flag
to the linker. This patch adds the necessary `-Wl` flag to fix the
problem.
Reviewed By: rnk, mstorsjo
Differential Revision: https://reviews.llvm.org/D134165
Akira Hatanaka [Sat, 25 Jun 2022 20:19:52 +0000 (13:19 -0700)]
[Sema] Reject array element types whose sizes aren't a multiple of their
alignments
In the following code, the first element is aligned on a 16-byte
boundary, but the remaining elements aren't:
```
typedef char int8_a16 __attribute__((aligned(16)));
int8_a16 array[4];
```
Currently clang doesn't reject the code, but it should since it can
cause crashes at runtime. This patch also fixes assertion failures in
CodeGen caused by the changes in https://reviews.llvm.org/D123649.
Differential Revision: https://reviews.llvm.org/D133711
Joel E. Denny [Wed, 21 Sep 2022 16:06:41 +0000 (12:06 -0400)]
[lit] Try to fix new test from
28412d1800e3 under Windows
`llvm/utils/lit/tests/Inputs/shtest-define/value-escaped.txt` broke at
least at <https://lab.llvm.org/buildbot/#/builders/216/builds/10114>.
The problem appears to be a non-portable `echo` command line.
Philip Reames [Wed, 21 Sep 2022 16:04:42 +0000 (09:04 -0700)]
[SDAG] Split handling of VPLoad/VPGather and VPStore/VPScatter [nfc]
The merged routines are not-idiomatic, and the code sharing that results is prettty minimal. The confusion factor is not justified.
J. Ryan Stinnett [Wed, 21 Sep 2022 15:52:44 +0000 (16:52 +0100)]
[LangRef][Docs] Fix RST header length for GC intrinsics
This fixes up the header length which regressed in
8c1a9e3cf37cb2aa6e67934e56796284efa42806.
Kazu Hirata [Wed, 21 Sep 2022 15:50:30 +0000 (08:50 -0700)]
[ModuleInliner] Factor out common code in InlineOrder.cpp (NFC)
This patch factors out common code in InlineOrder.cpp.
Without this patch, the model is to ask classes like SizePriority and
CostPriority to compare a pair of call sites:
bool hasLowerPriority(const CallBase *L, const CallBase *R) const override {
while these priority classes have their own caches of priorities:
DenseMap<const CallBase *, PriorityT> Priorities;
This model results in a lot of duplicate code like hasLowerPriority
and updateAndCheckDecreased.
This patch changes the model so that priority classes just have two
methods to compute a priority for a given call site and to compare two
previously computed priorities (as opposed to call sites).
Facilities like hasLowerPriority and updateAndCheckDecreased move to
PriorityInlineOrder along with the map from call sites to their
priorities. PriorityInlineOrder becomes a template class so that it
can accommodate different priority classes.
Differential Revision: https://reviews.llvm.org/D134149
J. Ryan Stinnett [Wed, 21 Sep 2022 15:44:58 +0000 (16:44 +0100)]
[LangRef][Docs] Align RST syntax for GC intrinsics
This changes the GC intrinsics to use the same header styling as the others.
Joel E. Denny [Wed, 21 Sep 2022 15:32:05 +0000 (11:32 -0400)]
[lit] Implement DEFINE and REDEFINE directives
These directives define per-test lit substitutions. The concept was
discussed at
<https://discourse.llvm.org/t/iterating-lit-run-lines/62596/10>.
For example, the following directives can be inserted into a test file
to define `%{cflags}` and `%{fcflags}` substitutions with empty
initial values, which serve as the parameters of another newly defined
`%{check}` substitution:
```
// DEFINE: %{cflags} =
// DEFINE: %{fcflags} =
// DEFINE: %{check} = %clang_cc1 %{cflags} -emit-llvm -o - %s | \
// DEFINE: FileCheck %{fcflags} %s
```
The following directives then redefine the parameters before each use
of `%{check}`:
```
// REDEFINE: %{cflags} = -foo
// REDEFINE: %{fcflags} = -check-prefix=FOO
// RUN: %{check}
// REDEFINE: %{cflags} = -bar
// REDEFINE: %{fcflags} = -check-prefix=BAR
// RUN: %{check}
```
Of course, `%{check}` would typically be more elaborate, increasing
the benefit of the reuse.
One issue is that the strings `DEFINE:` and `REDEFINE:` already appear
in 5 tests. This patch adjusts those tests not to use those strings.
Our prediction is that, in the vast majority of cases, if a test
author mistakenly uses one of those strings for another purpose, the
text appearing after the string will not happen to have the syntax
required for these directives. Thus, the test author will discover
the mistake immediately when lit reports the syntax error.
This patch also expands the documentation on existing lit substitution
behavior.
Reviewed By: jhenderson, MaskRay, awarzynski
Differential Revision: https://reviews.llvm.org/D132513
Chris Bieneman [Wed, 21 Sep 2022 15:29:26 +0000 (10:29 -0500)]
[NFC] Add GitHub issues to HLSL FIXME comments
In order to make this easier to track I've filed issues for each of the
HLSL FIXME comments that I can find. I may have missed some, but I want
this to be the new default mode.
Matt Arsenault [Wed, 21 Sep 2022 15:25:04 +0000 (11:25 -0400)]
AMDGPU: Move test to correct location
This is not a MIR printer/parser test, so it belongs with the ordinary
codegen tests.
rkayaith [Wed, 7 Sep 2022 16:42:52 +0000 (12:42 -0400)]
[mlir][llvm] Support pointer entries in data layout translation
This adds support for pointer DLTI entries in LLVMIR export, e.g.
```
// translated to: p0:32:64:128
#dlti.dl_entry<!llvm.ptr, dense<[32,64,128]> : vector<3xi32>>
// translated to: p1:32:32:32:64
#dlti.dl_entry<!llvm.ptr<1>, dense<[32,32,32,64]> : vector<4xi32>>
```
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D133434
Anders Langlands [Wed, 21 Sep 2022 15:12:48 +0000 (11:12 -0400)]
Add clang_CXXMethod_isDeleted function
Adds a function to check if a method has been deleted by copy-pasting
the existing implementation of clang_CXXMethod_isDefaulted and changing
it to call CXXMethod::isDeleted() instead.
Differential Revision: https://reviews.llvm.org/D133924
bixia1 [Wed, 21 Sep 2022 13:59:09 +0000 (06:59 -0700)]
[mlir][memref] Add realloc op.
Add memref.realloc and canonicalization of the op. Add conversion patterns for
lowering the op to LLVM using unaligned alloc or aligned alloc based on the
conversion option.
Add filecheck tests for parsing and converting the op. Add an integration test.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D133424
Alexey Bataev [Wed, 21 Sep 2022 14:18:06 +0000 (07:18 -0700)]
[SLP]Fix write-after-bounds.
Mask might be larger than the NumElts-OffsetBeg, need to use actual
indices to avoid acces out of bounds.
Nikita Popov [Wed, 21 Sep 2022 14:52:25 +0000 (16:52 +0200)]
[InstSimplify] Add additional simplifyWithOpReplaced() vector tests (NFC)
Florian Hahn [Wed, 21 Sep 2022 14:50:29 +0000 (15:50 +0100)]
[llvm-reduce] Update NoChunks initializer to be in line with AllChunks.
Without this patch, the assertion triggers below on the test case,
because we are using different oracles for the verification.
Assertion failed: (Targets == NoChunksCounter.count() && "number of chunks changes when reducing"), function runDeltaPass, file Delta.cpp, line 272.
Graham Hunter [Tue, 20 Sep 2022 11:17:32 +0000 (12:17 +0100)]
[NFC][LV] Scalarizing test for masked vector calls
Simon Pilgrim [Wed, 21 Sep 2022 14:24:33 +0000 (15:24 +0100)]
[LoopVectorize] Fix test name - the test is for fshl not cttz intrinsic costs
zhijian [Wed, 21 Sep 2022 13:38:13 +0000 (09:38 -0400)]
[AIX] change "llvm-nm" to "env OBJECT_MODE=any llvm-nm" in clang/test for AIX OS
Summary:
since default object mode of llvm-nm is change to -X32 (from default -Xany) in patch https://reviews.llvm.org/D132494.In order not effect the test cases in clang/test we need to change "llvm-nm" to "env OBJECT_MODE=any llvm-nm" in clang/test for AIX OS
Reviewers: James Henderson,David Tenty, Hubert Tong
Differential Revision: https://reviews.llvm.org/D134284
Matt Arsenault [Mon, 19 Sep 2022 20:54:18 +0000 (16:54 -0400)]
LICM: Pass through AssumptionCache
Sanjay Patel [Wed, 21 Sep 2022 12:56:25 +0000 (08:56 -0400)]
[AArch64] add tests for fadd -> fma combines; NFC
The transform to create a final fma was added with:
D132837 /
c98a46fee6f4043276eac
These tests are intended to show the minimal fast-math-flags
necessary to enable the fold: currently only the final fadd
needs to have "reassoc".
Alex Richardson [Tue, 20 Sep 2022 13:42:32 +0000 (13:42 +0000)]
Add all constant physical registers to callee preserved masks
This allows MachineCopyPropagation to eliminate copies of constant registers
such as zero registers. They were previously not being eliminated as the
check for MO.clobbersPhysReg(AvailSrc) would return true for constant
registers such as MIPS $zero.
To avoid having to manually add the zero registers to all CalleeSavedRegs
instantiations in tablegen, I instead added a new isConstant bit to the
Register and set this for MIPS, RISC-V, and AArch64 zero registers.
RegisterInfoEmitter.cpp looks at this flag and adds all constant registers
to the preserved register mask.
This may also benefit other passes but so far I have only seen differences
in MachineCopyPropagation. In the future it might make sense to generate
`isConstantPhysReg()` from this information.
Original source: https://github.com/CTSRD-CHERI/llvm-project/commit/
8588d8b81458ed6d87b674893e7752e6a6915574
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D131958
Alex Richardson [Tue, 20 Sep 2022 13:40:37 +0000 (13:40 +0000)]
Add a baseline test for D131958
This test shows that the save of MIPS $zero to a callee-saved register
is not elided by the machine-cp pass.
Differential Revision: https://reviews.llvm.org/D131957
Oleg Shyshkov [Wed, 21 Sep 2022 12:47:21 +0000 (12:47 +0000)]
[mlir] Move getDimsOfType to StructuredOpsUtils.h.
Summary:
This change will bring all helpers that work with iterator types to one place.
Currently getDimsOfType is is declared in Linalg.h, but not directly included by
LinalgInterfaces. It worked so far only because all the places that include
LinalgInterfaces.h also include Linalg.h directly or indirectly.
Differential Revision: https://reviews.llvm.org/D134350
Simon Pilgrim [Wed, 21 Sep 2022 12:48:15 +0000 (13:48 +0100)]
[CostModel][X86] Add vbmi2 costs for funnelshift/rotate intrinsics
Add costs for the funnel shift instructions - fixes some discrepancies I was hitting with costs numbers from the 'cost-tables vs llvm-mca' script D103695
Sanjay Patel [Wed, 21 Sep 2022 12:03:48 +0000 (08:03 -0400)]
[InstCombine] don't canonicalize shl+sub to mul+add
This stops Negator from transforming:
`C1 - shl X, C2 --> mul X, (1<<C2) + C1`
...in the general case. There does not seem to be any analysis
benefit to using mul in IR, and there's definitely downside in
codegen (particularly when the multiply has to be expanded).
If `C1` is 0, then there's a stronger argument that the single
mul is a better canonicalization than negate-of-shl, but we may
want to remove that too.
This was noted as a potential conflict for D133667.
Differential Revision: https://reviews.llvm.org/D134310
Louis Dionne [Wed, 21 Sep 2022 12:38:00 +0000 (08:38 -0400)]
Revert "[llvm] Remove libcxx, libcxxabi and libunwind from supported LLVM_ENABLE_PROJECTS"
This reverts commit
887b8bd733ea36aaa5d9b0a2b45df16c6f6bb6a4 while we
work on resolving issues brought up in https://reviews.llvm.org/D132480.
Simon Pilgrim [Wed, 21 Sep 2022 12:34:32 +0000 (13:34 +0100)]
[CostModel][X86] Add vbmi2 test coverage for funnelshift/rotate intrinsics
vbmi2 has vector funnel shift support that we should be costing correctly
Simon Pilgrim [Wed, 21 Sep 2022 11:55:59 +0000 (12:55 +0100)]
[CostModel][X86] Remove out of date TODO
ROTR constant and uniform-constant tests were added some time ago by
2fe1076a0888b4cdc22abc33ef2e5d9a7d8de1b1
Matheus Izvekov [Sun, 28 Aug 2022 20:26:01 +0000 (22:26 +0200)]
[clang] AST: SubstTemplateTypeParmType support for non-canonical underlying type
This change allows us to represent in the AST some specific
circumstances where we substitute a template parameter type
which is part of the underlying type of a previous substitution.
This presently happens in some circumstances dealing with
substitution of defaulted parameters of template template
parameters, and in some other cases during concepts substitution.
The main motivation for this change is for the future use in the
implementation of template specialization resugaring, as this will
allow us to represent a substitution with sugared types.
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Differential Revision: https://reviews.llvm.org/D132816
Ivan Butygin [Sun, 18 Sep 2022 21:34:20 +0000 (23:34 +0200)]
[mlir] Allow negative strides and offset in StridedLayoutAttr
Negative strides are useful for creating reverse-view of array. We don't have specific example for negative offset yet but will add it for consistency.
Differential Revision: https://reviews.llvm.org/D134147
Michał Górny [Tue, 20 Sep 2022 09:04:06 +0000 (11:04 +0200)]
[clang] [Driver] Support multiple configuration files
Support specifying multiple configuration files via multiple `--config`
options. When multiple files are specified, the options from subsequent
files are appended to the options from the initial file.
While at it, remove the incorrect assertion about CfgFileName being
non-empty. It can be empty if `--config ""` is passed, and it makes
sense to report it as non-existing file rather than crash.
Differential Revision: https://reviews.llvm.org/D134270
Wei Yi Tee [Wed, 21 Sep 2022 10:37:52 +0000 (10:37 +0000)]
[clang][dataflow] Remove deprecated `transfer(const Stmt *, ...)` API.
Reviewed By: gribozavr2
Differential Revision: https://reviews.llvm.org/D134318
Simon Pilgrim [Wed, 21 Sep 2022 11:00:09 +0000 (12:00 +0100)]
[CostModel][X86] Add CostKinds test coverage for funnelshift/rotate intrinsics
Wei Yi Tee [Wed, 21 Sep 2022 09:01:00 +0000 (09:01 +0000)]
[clang][dataflow] Remove deprecated overloads of `checkDataflow` in `TestingSupport.h`.
Reviewed By: gribozavr2
Differential Revision: https://reviews.llvm.org/D134081
Kazushi (Jam) Marukawa [Sun, 18 Sep 2022 06:26:57 +0000 (15:26 +0900)]
[VE] Remove obsolete ANDrm patterns
Remove obsolete ANDrm patterns for MIMM operands. We add these
translations to optimize commonly used cast operations before
we support MIMM operands directly by each isntruction. Such
translations are obsolete now.
Reviewed By: efocht
Differential Revision: https://reviews.llvm.org/D134341
Nikita Popov [Wed, 21 Sep 2022 10:03:53 +0000 (12:03 +0200)]
[InstSimplify] Add vector tests for simplifyWithOpReplaced (NFC)
Thomas Symalla [Fri, 26 Aug 2022 07:14:10 +0000 (09:14 +0200)]
[ISel] Enable generating more fma instructions.
This patch changes a FADD / FMUL => FMA ISel pattern implemented
in D80801 so that it peeks through more than one FMA.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D132837
David Green [Wed, 21 Sep 2022 09:46:43 +0000 (10:46 +0100)]
[AArch64] Lower scalar sqxtn intrinsics to use fp registers
The llvm.aarch64.neon.scalar.sqxtn.i32.i64 intrinsics take and return
integer types, but operate on fp registers. This can create some
inefficiencies in their lowering, where the registers are converted to
fp a little too late. This patch adds lowering for the intrinsics,
creating bitcasts to/from fp types to allow nicer folding later when the
instructions are selected, especially around insert/extracts.
Differential Revision: https://reviews.llvm.org/D134024
Jay Foad [Wed, 21 Sep 2022 09:42:23 +0000 (10:42 +0100)]
[AMDGPU] Update checks in mad_u64_u32.ll. NFC.
Matthias Springer [Wed, 21 Sep 2022 02:20:23 +0000 (11:20 +0900)]
[mlir][tensor][bufferize] Implement getBufferType for Expand/CollapseShapeOp
This function must be implemented for all ops, where the result memref type is different from the input memref type.
Differential Revision: https://reviews.llvm.org/D134331
Graham Hunter [Wed, 21 Sep 2022 08:54:14 +0000 (09:54 +0100)]
[LAA] Fix ICE with scAddExpr in forked pointers
The IR from https://github.com/llvm/llvm-project/issues/57368 results
in an assert firing when trying to create a runtime check for the
forked pointer. One of the forks is fine since it's loop invariant,
but the other is a scAddExpr (containing a scAddRecExpr, so not
invariant) when RtCheck::insert expects a scAddRecExpr.
This is a simple fix to just avoid forks which aren't AddRec or
loop invariant. We can allow it as a forked pointer later with
more work.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D133020
Valentin Clement [Wed, 21 Sep 2022 09:19:13 +0000 (11:19 +0200)]
[flang] Handle parent component of extended derived-type
Parent component refers to the parent derived-type of an extended type.
The parent component is skipped when a specififc component is
referred to. This is fine since all the components in extended type
are available in the type itself. When the parent component is referred,
it need to be taken into account correctly.
This patch fixes the case when the parent component is referred. In a
box, an approriate slice is created or updated to point to the first
component of the parent component. For scalar, a simple conversion to
the parent component type is done.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D134170
eopXD [Wed, 21 Sep 2022 09:04:27 +0000 (02:04 -0700)]
[NFC][Scalarizer] Let testcase be auto-generated from update_test_check
The current `CHECK` lines are hand-written. Changing them to auto-generated lines.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D134340
Kazushi (Jam) Marukawa [Sun, 18 Sep 2022 01:26:07 +0000 (10:26 +0900)]
[VE][NFC] Change to use l2i/i2l to simplify code
We previously added l2i/i2l macros to simpily EXTRACT_SUBREG/INSERT_SUBREG
conversions. This patch changes VEInstrInfo.td to use such macros to
simplify existing code.
Reviewed By: efocht
Differential Revision: https://reviews.llvm.org/D134118
Kazushi (Jam) Marukawa [Sat, 17 Sep 2022 09:04:06 +0000 (18:04 +0900)]
[VE] Add maxnum and minnum
Add maxnum and minnum for float and double. Lowering is already
implemented, so this patch changes them legal and adds regression
tests.
Reviewed By: efocht
Differential Revision: https://reviews.llvm.org/D134108
Kazushi (Jam) Marukawa [Sat, 17 Sep 2022 09:04:06 +0000 (18:04 +0900)]
[VE] Change to expand FMA
VE has fused multiply-add instruction for only vector calculations. This
patch forces to expand scalar FMA to multiply and add instructions.
This patch also adds regression test.
Reviewed By: efocht
Differential Revision: https://reviews.llvm.org/D134107
David Green [Wed, 21 Sep 2022 08:54:17 +0000 (09:54 +0100)]
[AArch64] Insert/Extract of bitcast patterns
This adds some quick tablegen patterns for vector_insert(bitcast(..))
and bitcast(vector_extract(..)), allowing us to avoid a round-trip
through GPRs.
Differential Revision: https://reviews.llvm.org/D134022
David Sherwood [Tue, 20 Sep 2022 15:28:34 +0000 (16:28 +0100)]
[AArch64][SME] Disable inlining when SME attributes require smstart/smstop or lazy-save.
Inlining must be disabled when the call-site needs to toggle PSTATE.SM or
when the callee's function body is executed in a different streaming mode than
its caller. This is needed because function calls are the boundaries for
streaming mode changes.
More details about the SME attributes and design can be found
in D131562.
Differential Revision: https://reviews.llvm.org/D131581
Nikita Popov [Wed, 7 Sep 2022 08:20:20 +0000 (10:20 +0200)]
[MemorySSA] Remove PerformedPhiTranslation flag
I believe this is no longer necessary, as the underlying problem
has been fixed in a different way: Nowadays, we will adjust the
location size to beforeOrAfterPointer() if the pointer is not loop
invariant. This makes merging results translated across loop
backedges safe.
The two tests in phi-translation.ll show an improvement while still
being correct: The loads in the loop no longer alias with noalias
pointers, but still alias with the store in the entry block (which
they originally did not -- this is the bug that
PerformedPhiTranslation originally fixed).
Differential Revision: https://reviews.llvm.org/D133404
Jean Perier [Wed, 21 Sep 2022 08:23:45 +0000 (10:23 +0200)]
[flang] Limit shape inquiries rewrite to associate construct entity
The previous code was rewriting all shape inquires on associate
construct entities to inquires on the associated expression or variable.
This is is incorrect because at the point of inquiry, some statement
between the association and the inquiry may have modified the expression
operands or variable in a way that changes its shapes or bounds.
For instance, in the example below, expression rewrites was previously
replacing `size(x, 1)` by `size(p, 1)` which is invalid if p is a
pointer.
```
associate(x => p + 1)
call call_that_may_modify_p_shape()
print *, size(x, 1)
end associate
```
This change restricts rewrites of shape inquiries on associate construct entity
to use the associated expression shape and bounds if and only if the
shape/bounds are compile time constant. Otherwise, this may be invalid.
Differential Revision: https://reviews.llvm.org/D133857
Thomas Symalla [Wed, 21 Sep 2022 08:15:55 +0000 (10:15 +0200)]
[NFC][AMDGPU] Pre-commit test for D132837.
Pre-commit an additional fmac test for D132837.
Bjorn Pettersson [Fri, 16 Sep 2022 12:54:40 +0000 (14:54 +0200)]
[SROA] Check typeSizeEqualsStoreSize in isVectorPromotionViable
Commit
de3445e0ef15c4209 (https://reviews.llvm.org/D132096) made
changes to isVectorPromotionViable basically doing
// Create Vector with size of V, and each element of type Ty
...
uint64_t ElementSize = DL.getTypeStoreSizeInBits(Ty).getFixedSize();
uint64_t VectorSize = DL.getTypeSizeInBits(V).getFixedSize();
...
VectorType *VTy = VectorType::get(Ty, VectorSize / ElementSize, false);
Not quite sure why it uses the TypeStoreSize for the ElementSize,
but the new vector would only match in size with the old vector in
situations when the TypeStoreSize equals the TypeSize for Ty.
Therefore this patch adds a typeSizeEqualsStoreSize check as yet
another condition for allowing the the new type as a promotion
candidate.
Without this fix the new @test15 test would fail with an assert
like this:
opt: ../lib/Transforms/Scalar/SROA.cpp:1966:
auto isVectorPromotionViable(llvm::sroa::Partition &,
const llvm::DataLayout &)
::(anonymous class)::operator()(llvm::VectorType *,
llvm::VectorType *) const:
Assertion `DL.getTypeSizeInBits(RHSTy).getFixedSize() ==
DL.getTypeSizeInBits(LHSTy).getFixedSize() &&
"Cannot have vector types of different sizes!"' failed.
...
#8 isVectorPromotionViable(...)::$_10::operator()...
#9 llvm::SROAPass::rewritePartition(...)
#10 llvm::SROAPass::splitAlloca(...)
#11 llvm::SROAPass::runOnAlloca(...)
#12 llvm::SROAPass::runImpl(...)
#13 llvm::SROAPass::run(...)
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D134032
River Riddle [Wed, 21 Sep 2022 01:11:08 +0000 (18:11 -0700)]
[mlir] Update tests to use kEmitAccessorPrefix_Prefixed
These aren't user facing, so just flip them directly to prefixed.
River Riddle [Wed, 21 Sep 2022 01:12:32 +0000 (18:12 -0700)]
[mlir][NFC] Tidy up the doc comment on CastInfo for Types
This had quite a few grammatical errors and typos.
River Riddle [Tue, 20 Sep 2022 23:42:59 +0000 (16:42 -0700)]
[mlir] Update Attributes to use the new casting infra
This allows for using the llvm namespace cast methods instead
of the ones on the Attribute class. The Attribute class methods
are kept for now, but we'll want to remove these eventually
(with a really long lead time).
Differential Revision: https://reviews.llvm.org/D134327
Adrian Kuegel [Wed, 21 Sep 2022 05:51:36 +0000 (07:51 +0200)]
[mlir][Bazel] Port
f5fe92f69385
Mark de Wever [Sat, 27 Aug 2022 11:43:51 +0000 (13:43 +0200)]
[libc++] Use Clang-16 for c++17.
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D132788
Chen Zheng [Fri, 16 Sep 2022 05:48:44 +0000 (01:48 -0400)]
[MachineCycle][NFC] add a cache for block and its top level cycle
This solves https://github.com/llvm/llvm-project/issues/57664
Reviewed By: sameerds
Differential Revision: https://reviews.llvm.org/D134019
Michał Górny [Tue, 20 Sep 2022 09:29:19 +0000 (11:29 +0200)]
[clang] [docs] Improve formatting & fix typo in config docs
Fix teletype formatting in configuration file documentation to use
double backticks rather than single backticks. Cover some more names
with this formatting. Correct the name of config file for `clang-cl`
invocation.
Differential Revision: https://reviews.llvm.org/D134271
Jennifer Yu [Tue, 20 Sep 2022 08:38:34 +0000 (01:38 -0700)]
[Clang][OpenMP] Codegen generation for has_device_addr claues.
This patch add codegen support for the has_device_addr clause. It use
the same logic of is_device_ptr. But passing &var instead pointer to var
to kernal.
Differential Revision: https://reviews.llvm.org/D134268
Mehdi Amini [Wed, 21 Sep 2022 03:54:32 +0000 (03:54 +0000)]
Revert "[mlir][tensor] Support more cases in MergeConsecutiveExtractSlice"
This reverts commit
5d4603a02d0c3e0106b10d245322b1d2072c0c3d.
The Dialect/Tensor/fold-consecutive-insert-extract-slice.mlir test is
failing when built with GCC
Kevin Gleason [Tue, 20 Sep 2022 21:49:08 +0000 (21:49 +0000)]
Fix -fuse-ld to be linker flag in feature detection check
Discovered an issue working in StableHLO when attempting to build with `-Wall -Werror`:
https://github.com/openxla/stablehlo/pull/137
Currently, if `LLVM_USE_LLD` and `-DCMAKE_CXX_FLAGS="${CMAKE_CXX_FLAGS} -Wall -Werror"`
are both specified for build, the build will error with:
```
-- Performing Test CXX_SUPPORTS_CUSTOM_LINKER - Failed
CMake Error at /usr/local/google/home/gleasonk/Coding/llvm-build/lib/cmake/llvm/HandleLLVMOptions.cmake:309 (message):
Host compiler does not support '-fuse-ld=lld'
...
$ cat <build_dir>/CMakeFiles/CMakeError.log
...
clang: error: argument unused during compilation: '-fuse-ld=lld' [-Werror,-Wunused-command-line-argument]
```
It looks like other repos have hit this same issue:
- https://github.com/golang/go/issues/41527 (mentioned in comment)
- https://github.com/iree-org/iree/pull/7450
This can be reproduced in llvm-project with the following build command:
```
# Compile command taken from https://mlir.llvm.org/getting_started/
# and modified for use case
cmake -G Ninja ../llvm \
-DLLVM_ENABLE_PROJECTS=mlir \
-DLLVM_BUILD_EXAMPLES=ON \
-DLLVM_TARGETS_TO_BUILD="X86;NVPTX;AMDGPU" \
-DCMAKE_BUILD_TYPE=Release \
-DLLVM_ENABLE_ASSERTIONS=ON \
-DCMAKE_CXX_COMPILER=clang++ \
-DCMAKE_C_COMPILER=clang \
-DLLVM_ENABLE_LLD=ON \
-DCMAKE_CXX_FLAGS="${CMAKE_CXX_FLAGS} -Wall -Werror"
```
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D134206
Christopher Bate [Tue, 20 Sep 2022 20:54:35 +0000 (14:54 -0600)]
[mlir][SCF] Fix loop pipelining unable to handle ops with regions
This change allows the SCF LoopPipelining transform to handle ops with
nested regions within the pipelined `scf.for` body. The op and nested
regions are treated as a single unit from the transform's perspective.
This change also makes explicit the requirement that only ops whose
parent Block is the loop body Block are allowed to be scheduled by the
caller.
Reviewed By: ThomasRaoux, nicolasvasilache
Differential Revision: https://reviews.llvm.org/D133965
Emmmer [Wed, 21 Sep 2022 03:52:04 +0000 (11:52 +0800)]
[LLDB][RISCV] Fix UndefinedBehaviorSanitizer in RISCVEmulatorTester
Craig Topper [Wed, 21 Sep 2022 03:26:48 +0000 (20:26 -0700)]
[RISCV] Remove support for the unratified Zbt extension.
This extension does not appear to be on its way to ratification.
Out of the unratified bitmanip extensions, this one had the
largest impact on the compiler.
Posting this patch to start a discussion about whether we should
remove these extensions. We'll talk more at the RISC-V sync meeting this
Thursday.
Reviewed By: asb, reames
Differential Revision: https://reviews.llvm.org/D133834
Fangrui Song [Wed, 21 Sep 2022 03:13:30 +0000 (20:13 -0700)]
[Driver] Fix -f[no-]unwind-tables -Wunused-command-line-argument after
4388b56d525c08ce3cf941cfbad2428b0e1695b0
jacquesguan [Tue, 30 Aug 2022 09:17:55 +0000 (17:17 +0800)]
[RISCV] Support peephole optimization to fold vmerge.vvm that has tail agnostic policy and unmasked intrinsics.
This patch supports the tail agnostic part of D130442.
Reviewed By: fakepaper56
Differential Revision: https://reviews.llvm.org/D132923
Ting Wang [Wed, 21 Sep 2022 01:21:06 +0000 (21:21 -0400)]
[PowerPC][NFC] Add virtual call to show redundant spill of vector registers
Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D133921
Volodymyr Sapsai [Tue, 20 Sep 2022 00:46:01 +0000 (17:46 -0700)]
[modules] Fix error "malformed or corrupted AST file: 'SourceLocation remap refers to unknown module...'".
When a framework can be found at a new location, all references to it in
the module cache become outdated. When we try to load such outdated .pcm
file, we shouldn't change any already loaded and processed modules.
If `Module` has `ASTFile`, it means we've read its AST block already and
it is too late to undo that. If `ASTFile` is `None`, there is no value
in setting it to `None` again. So we don't reset `ASTFile` in
`ModuleManager::removeModules` at all.
rdar://
97216258
Differential Revision: https://reviews.llvm.org/D134249
Kazu Hirata [Wed, 21 Sep 2022 00:41:58 +0000 (17:41 -0700)]
[clang] Fix an unused variable warning
This patch fixes:
clang/lib/Driver/ToolChains/PS4CPU.cpp:159:14: error: unused
variable 'IsPS5' [-Werror,-Wunused-variable]
Changpeng Fang [Wed, 21 Sep 2022 00:25:52 +0000 (17:25 -0700)]
AMDGPU: Implicit kernel arguments related optimization when uniform-workgroup-size=true
Summary:
Under code object version 5, ockl_get_local_size returns the value computed by the expression:
workgroup_id < hidden_block_count ? hidden_group_size : hidden_remainder
For functions with the attribute uniform-work-group-size=true. we can evaluate workgroup_id < hidden_block_count
as true, and thus hidden_group_size is returned for ockl_get_local_size.
With uniform-workgroup-size=true, this work also set all remainders to zero, and if there
is reqd_work_group_size, we also set work-group-size to the required value from the metadata.
Reviewers:
arsenm and bcahoon
Differential Revision:
https://reviews.llvm.org/D131276
Lei Zhang [Wed, 21 Sep 2022 00:16:42 +0000 (20:16 -0400)]
[mlir][tensor] NFC: name various Transforms/ files consistently
Use a suffix to make clear what the contents inside each file
are.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D134202
Lei Zhang [Wed, 21 Sep 2022 00:00:49 +0000 (20:00 -0400)]
[mlir][tensor] Support more cases in MergeConsecutiveExtractSlice
This commit adds utility functions to perform general merging of
OffsetSizeAndStrideOpInterface by supporting producer rank
reducing and non-unit strides.
With it we can extend MergeConsecutiveExtractSlice to support
more cases.
Co-authored-by: Mahesh Ravishankar <ravishankarm@google.com>
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D134294
Fangrui Song [Wed, 21 Sep 2022 00:12:44 +0000 (17:12 -0700)]
[ELF] Make -V an alias for -v
In GNU ld,
* --version skips linker input processing.
* -v and -V keep processing if there is any input file. -V has more
information we don't support.
We currently make -V an alias for --version which skips input processing.
On many `*-freebsd` and `powerpc-*` targets, `gcc -v` passes `-V` to ld
and expects to process input. Make -V an alias for -v to provide
compatibility.
Fix https://github.com/llvm/llvm-project/issues/57859
Fangrui Song [Wed, 21 Sep 2022 00:05:35 +0000 (17:05 -0700)]
[ELF][test] Improve -v and --version tests
Shubham Sandeep Rastogi [Tue, 20 Sep 2022 23:58:14 +0000 (16:58 -0700)]
Change isLittleEndian to follow llvm style and add an accessor
Differential Revision: https://reviews.llvm.org/D134290
Lei Zhang [Tue, 20 Sep 2022 23:52:19 +0000 (19:52 -0400)]
[mlir][tensor] Merge consecutive insert_slice/extract_slice ops
Consecutive tensor.insert_slice/tensor.extract_slice can be
created for the case like tiling convolution and then downsizing
2-D convolutions into 1-D ones. It hinders further transformations.
So adding these patterns to clean it up.
Given that bufferization is sensitive and have requirements over
the IR structure (see https://reviews.llvm.org/D132666),
these patterns are put in Transforms/ with separate entry points
for explicit collection.
Reviewed By: ThomasRaoux, mravishankar
Differential Revision: https://reviews.llvm.org/D133871
Michael Jones [Fri, 16 Sep 2022 18:19:38 +0000 (11:19 -0700)]
[libc] add strerror
Strerror maps error numbers to strings. Additionally, a utility for
mapping errors to strings was added so that it could be reused for
perror and similar.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D134074
Jakub Kuderski [Tue, 20 Sep 2022 23:00:32 +0000 (19:00 -0400)]
[mlir][arith] Fix constant naming in integration tests. NFC.
Suggested by @antiagainst in D134321.
Jakub Kuderski [Tue, 20 Sep 2022 22:51:20 +0000 (18:51 -0400)]
[mlir][arith] Add integration tests for addi emulation
This includes tests with the exact expected values and comparison-based tests.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134321
Michael Berg [Tue, 20 Sep 2022 22:54:16 +0000 (15:54 -0700)]
[DSE] Add value type info checks for masked store candidates in Dead Store Elimination.
The type information of the store values can diverge when checking for valid
mask store candidates to eliminate via DSE. This patch checks for equivalence
wrt to size and element count.
Reviewed By: fhahn, rui.zhang
Differential Revision: https://reviews.llvm.org/D132700
Matheus Izvekov [Tue, 20 Sep 2022 13:18:20 +0000 (15:18 +0200)]
[clang] Fix missing template arguments in AST of access to member variable template
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Differential Revision: https://reviews.llvm.org/D134295
Stanley Winata [Tue, 20 Sep 2022 22:28:40 +0000 (15:28 -0700)]
[mlir][spirv] Query target environment for mapping memory space
Checks spirv::TargetEnv from op to see if it contains either Kernel or Shader capabilities.
If it does, then it will set the memory space mapping accordingly.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134317
Xiang Li [Mon, 22 Aug 2022 23:57:48 +0000 (16:57 -0700)]
[HLSL] Support PCH for cc1 mode
Add HLSLExternalSemaSource as ExternalSemaSource instead of ASTContext::ExternalSource when PCH is included.
This allows a different external source to be set for the AST context.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D132421
Nirvedh Meshram [Mon, 19 Sep 2022 18:05:58 +0000 (11:05 -0700)]
[mlir][spirv] Add casting ops to/from generic storage space
Reviwed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134217
Matthew Voss [Tue, 20 Sep 2022 21:44:56 +0000 (14:44 -0700)]
[PS4] Always enable the .debug_aranges section when using LTO
This flag enables the .debug_aranges section by passing a flag to LLD
and our internal linker. This also adds a new routine that will generate
the correct flag for our internal linker or set of flags for LLD when
given a list of LLVM options. That ensures multiple LLVM codegen options
can be passed to either linker consistently.
Differential Revision: https://reviews.llvm.org/D134296
Pengxuan Zheng [Tue, 20 Sep 2022 00:21:21 +0000 (17:21 -0700)]
[LLD][COFF] Support /MAPINFO flag
This patch adds support for link.exe's /MAPINFO flag to lld-link.exe.
Here is a description of the flag from Microsoft
(https://learn.microsoft.com/en-us/cpp/build/reference/mapinfo-include-information-in-mapfile?view=msvc-170):
The /MAPINFO option tells the linker to include the specified information in a
mapfile, which is created if you specify the /MAP option. EXPORTS tells the
linker to include exported functions.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D134247
Lei Zhang [Tue, 20 Sep 2022 21:31:16 +0000 (17:31 -0400)]
[mlir][linalg] Swap tensor.extract_slice(linalg.fill)
This commit adds a pattern to swap
```
tensor.extract_slice(linalg.fill(%cst, %init))
```
into
```
linalg.fill(%cst, tensor.extract_slice(%init))
```
when the linalg.fill op have no other users.
This helps to reduce the fill footprint.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D134102
Stanley Winata [Tue, 20 Sep 2022 21:16:52 +0000 (17:16 -0400)]
[mlir][spirv] Lower max/min vector.reduction for OpenCL
Templatizing vector reduction to enable lowering from
vector.reduction max/min to CL ops.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134313
Louis Dionne [Tue, 20 Sep 2022 21:22:00 +0000 (17:22 -0400)]
[NFC] Fix typo in comment
Naje George [Tue, 9 Aug 2022 00:07:42 +0000 (17:07 -0700)]
[flang] Add semantics test for atomic_add subroutine
Reviewed By: ktras
Differential Revision: https://reviews.llvm.org/D131535
Joshua Batista [Tue, 20 Sep 2022 21:04:08 +0000 (16:04 -0500)]
[HLSL] remove unnecessary abs attributes
remove abs non-elementwise attribute statements, stick to elementwise.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D134312
Kai Nacke [Mon, 19 Sep 2022 16:03:32 +0000 (16:03 +0000)]
[GISel] TreeMatcher: always skip leaves if they don't care
In `GIMatchTreeOpcodePartitioner::applyForPartition()`, the loop over
the possible leaves skip a leaf if the instruction does not care
about the instruction.
When processing the referenced operands in the next loop the same
leaves need to be skipped.
Later, when these leaves are added to all partitions, the bit vector
must be resized first before the bit representing the leaf is set.
This fixes a crash in llvm-tblgen.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D134192
Matt Arsenault [Tue, 20 Sep 2022 18:58:52 +0000 (14:58 -0400)]
AtomicExpand: Use correct pointer size for integer
This was using the default address space.
Matt Arsenault [Tue, 20 Sep 2022 18:51:33 +0000 (14:51 -0400)]
AMDGPU: Add baseline test for expansion of 16-bit local atomics
The expansion is currently using the wrong pointer size.