zijunzhao [Thu, 20 Jan 2022 09:30:51 +0000 (09:30 +0000)]
add tsan shared library
Add tsan shared library on Android. Only build tsan when minSdkVersion is above 23.
Reviewed By: danalbert, vitalybuka
Differential Revision: https://reviews.llvm.org/D108394
Matt Arsenault [Wed, 19 Jan 2022 16:06:25 +0000 (11:06 -0500)]
AMDGPU/GlobalISel: Directly diagnose return value use for FP atomics
Emit an error if the return value is used on subtargets that do not
support them. Previously we were falling back to the DAG on selection
failure, where it would emit this error and then fail again.
Nikolas Klauser [Thu, 20 Jan 2022 12:53:59 +0000 (13:53 +0100)]
[libc++] basic_string::resize_and_overwrite: Adopt LWG3645 (Not voted in yet)
Adopt LWG3645, which fixes the value categories of basic_string::resize_and_overwrite
https://timsong-cpp.github.io/lwg-issues/3645
Reviewed By: ldionne, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D116815
Roman Lebedev [Thu, 20 Jan 2022 17:31:47 +0000 (20:31 +0300)]
[NFC][SimplifyCFG] Add some tests for `invoke` merging
Sam Clegg [Thu, 20 Jan 2022 02:41:39 +0000 (18:41 -0800)]
[lld][WebAssemlby] Convert test to check disassembly output. NFC
Differential Revision: https://reviews.llvm.org/D117739
Nadav Rotem [Thu, 20 Jan 2022 17:25:45 +0000 (09:25 -0800)]
optimize icmp-ugt-ashr
This diff optimizes the sequence icmp-ugt(ashr,C_1) C_2. InstCombine
already implements this optimization for sgt, and this patch adds
support ugt. This patch adds the check for UGT.
@craig.topper came up with the idea and proof:
define i1 @src(i8 %x, i8 %y, i8 %c) {
%cp1 = add i8 %c, 1
%i = shl i8 %cp1, %y
%i.2 = ashr i8 %i, %y
%cmp = icmp eq i8 %cp1, %i.2
;Assume: C + 1 == (((C + 1) << y) >> y)
call void @llvm.assume(i1 %cmp)
; uncomment for the sgt case
%j = shl i8 %cp1, %y
%j.2 = sub i8 %j, 1
%cmp2 = icmp ne i8 %j.2, 127
;Assume (((c + 1 ) << y) - 1) != 127
call void @llvm.assume(i1 %cmp2)
%s = ashr i8 %x, %y
%r = icmp sgt i8 %s, %c
ret i1 %r
}
define i1 @tgt(i8 %x, i8 %y, i8 %c) {
%cp1 = add i8 %c, 1
%j = shl i8 %cp1, %y
%j.2 = sub i8 %j, 1
%r = icmp sgt i8 %x, %j.2
ret i1 %r
}
declare void @llvm.assume(i1)
This change is related to the optimizations in D117252.
Differential Revision: https://reviews.llvm.org/D117365
Valentin Clement [Thu, 20 Jan 2022 17:30:09 +0000 (18:30 +0100)]
[flang][NFC] Remove unused/duplicated kStridePosInDim
kStridePosInDim is a duplicate of kDimStridePos and is not used. Just
remove it.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D117784
Fraser Cormack [Thu, 20 Jan 2022 17:07:11 +0000 (17:07 +0000)]
[RISCV] Add tests for commuted vector/scalar VP patterns
This patch adds a variety of tests checking that we can match
vector/scalar instructions against masked VP intrinsics when the splat
is on the LHS. At this stage, we can't, despite us having
ostensibly-commutable ISel patterns for them. The use of V0 as the mask
operand interferes with the auto-generated ISel table.
Matt Arsenault [Wed, 19 Jan 2022 15:45:37 +0000 (10:45 -0500)]
AMDGPU/GlobalISel: Stop handling llvm.amdgcn.buffer.atomic.fadd
This code is not structured to handle the legacy buffer intrinsics and
was miscompiling them.
Matt Arsenault [Wed, 19 Jan 2022 02:08:01 +0000 (21:08 -0500)]
AMDGPU/GlobalISel: Fix selection of gfx90a FP atomics
The struct/raw forms for the buffer atomics now work as
expected. However, we're incorrectly handling the legacy form (which
we probably shouldn't handle at all). We also are not diagnosing the
use of the return value on gfx908. These will be addressed separately.
Matt Arsenault [Sun, 16 Jan 2022 00:16:03 +0000 (19:16 -0500)]
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
This was inheriting the mesa behavior, and as far as I know nobody is
using opencl kernels with amdpal. The isMesaKernel check was
irrelevant because this property needs to be held for all functions.
Random06457 [Thu, 20 Jan 2022 17:03:49 +0000 (20:03 +0300)]
[mips] Improve vr4300 mulmul bugfix pass
When compiling with dwarf info, the mfix4300 flag introduced in
https://reviews.llvm.org/D116238 can miss some occurrences of the vr4300
mulmul bug if a debug instruction happens to be between two `muls`
instructions. This change skips debug instructions in order to fix
the mulmul bug detection.
Fixes https://github.com/llvm/llvm-project/issues/53094
Differential Revision: https://reviews.llvm.org/D117615
Lucas Prates [Mon, 10 Jan 2022 10:19:27 +0000 (10:19 +0000)]
[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
The GlobalISel combiner currently uses sign extension when manipulating
the LHS constant when combining a sequence of the following sequence of
machine instructions into a single constant:
```
%0:_(s32) = G_CONSTANT i32 <CONSTANT>
%1:_(p0) = G_INTTOPTR %0:_(s32)
%2:_(s64) = G_CONSTANT i64 <CONSTANT>
%3:_(p0) = G_PTR_ADD %1:_, %2:_(s64)
```
This causes an issue when the bit width of the first contant and the
target pointer size are different, as G_INTTOPTR has no sign extension
semantics.
This patch fixes this by capture an arbitrary precision in when matching
the constant, allowing the matching function to correctly zero extend
it.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D116941
Sjoerd Meijer [Thu, 20 Jan 2022 16:56:31 +0000 (16:56 +0000)]
[FuncSpec] Add a reference, and some other clarifying comments. NFC.
Philip Reames [Thu, 20 Jan 2022 16:53:01 +0000 (08:53 -0800)]
{SLP] Delete dead code in favor of proper assert [NFC]
Philip Reames [Thu, 20 Jan 2022 16:46:06 +0000 (08:46 -0800)]
[SLP] Reduce nesting depth in calculateDependencies via for loop and early continue [NFC]
Sander de Smalen [Thu, 20 Jan 2022 15:13:32 +0000 (15:13 +0000)]
[ScalableVectors] Warn instead of error for invalid size requests.
This was intended to be fixed by D98856, but that only seemed to have
the desired behaviour when compiling to assembly using `-S`, not when
compiling into an object file or executable. Given that this was not
the intention of D98856, this patch fixes the behaviour.
Adrian Prantl [Thu, 20 Jan 2022 16:35:33 +0000 (08:35 -0800)]
Add missing include to fix modular build
Adrian Prantl [Thu, 20 Jan 2022 16:33:08 +0000 (08:33 -0800)]
Add missing include to fix modular build
Philip Reames [Thu, 20 Jan 2022 16:23:51 +0000 (08:23 -0800)]
[SLP] Add an asser to make a non-obvious precondition clear [NFC]
Michael Kruse [Thu, 20 Jan 2022 14:18:08 +0000 (08:18 -0600)]
[OpenMPIRBuilder] Detect and fix ambiguous InsertPoints for createParallel.
When a Builder methods accepts multiple InsertPoints, when both point to
the same position, inserting instructions at one position will "move" the
other after the inserted position since the InsertPoint is pegged to the
instruction following the intended InsertPoint. For instance, when
creating a parallel region at Loc and passing the same position as AllocaIP,
creating instructions at Loc will "move" the AllocIP behind the Loc
position.
To avoid this ambiguity, add an assertion checking this condition and
fix the unittests.
In case of AllocaIP, an alternative solution could be to implicitly
split BasicBlock at InsertPoint, using the first as AllocaIP, the second
for inserting the instructions themselves. However, this solution is
specific to AllocaIP since AllocaIP will always have to be first. Hence,
this is an argument to generally handling ambiguous InsertPoints as API
sage error.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D117226
Nico Weber [Thu, 20 Jan 2022 16:02:06 +0000 (11:02 -0500)]
[gn build] (manually) port
f29256a64a
Nikita Popov [Thu, 20 Jan 2022 15:48:19 +0000 (16:48 +0100)]
[InstSimplify] Add test for load of non-integral pointer (NFC)
Mubashar Ahmad [Thu, 20 Jan 2022 15:20:57 +0000 (15:20 +0000)]
[Clang][AArch64][ARM] Unaligned Access Test Fix
Test fixed for the unaligned access warning.
Nikita Popov [Thu, 20 Jan 2022 15:25:22 +0000 (16:25 +0100)]
[InstSimplify] Add test for reinterpret load of pointer type (NFC)
Simon Pilgrim [Thu, 20 Jan 2022 15:15:46 +0000 (15:15 +0000)]
[X86] lowerToAddSubOrFMAddSub - lower 512-bit ADDSUB patterns to blend(fsub,fadd)
AVX512 doesn't provide a ADDSUB instruction, but if we've built this from a build vector of scalar fsub/fadd elements we can still lower to blend(fsub,fadd)
Mircea Trofin [Thu, 20 Jan 2022 05:19:53 +0000 (21:19 -0800)]
[MLGO] Improved support for AOT cross-targeting scenarios
The tensorflow AOT compiler can cross-target, but it can't run on (for
example) arm64. We added earlier support where the AOT-ed header and object
would be built on a separate builder and then passed at build time to
a build host where the AOT compiler can't run, but clang can be otherwise
built.
To simplify such scenarios given we now support more than one AOT-able
case (regalloc and inliner), we make the AOT scenario centered on whether
files are generated, case by case (this includes the "passed from a
different builder" scenario).
This means we shouldn't need an 'umbrella' LLVM_HAVE_TF_AOT, in favor of
case by case control. A builder can opt out of an AOT case by passing that case's
model path as `none`. Note that the overrides still take precedence.
This patch controls conditional compilation with case-specific flags,
which can be enabled locally, for the component where those are
available. We still keep an overall flag for some tests.
The 'development/training' mode is unchanged, because there the model is
passed from the command line and interpreted.
Differential Revision: https://reviews.llvm.org/D117752
Nikita Popov [Tue, 18 Jan 2022 16:38:08 +0000 (17:38 +0100)]
[DebugInstrRef] Memoize variable order during sorting (NFC)
Instead of constructing DebugVariables and looking up the order
in the comparison function, compute the order upfront and then sort
a vector of (order, instr).
This improves compile-time by -0.4% geomean on CTMark ReleaseLTO-g.
Differential Revision: https://reviews.llvm.org/D117575
Simon Pilgrim [Thu, 20 Jan 2022 14:58:23 +0000 (14:58 +0000)]
[X86] Fix v16f32 ADDSUB test
This was supposed to ensure we're not generating 512-bit ADDSUB nodes, but cut+paste typos meant we weren't generating a full 512-bit pattern
eopXD [Sat, 6 Nov 2021 14:54:58 +0000 (07:54 -0700)]
[Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction
According to v-spec v1.0, `zve-32x` is the new minimum extension to include
to have vector instructions.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D112613
Jan Svoboda [Thu, 20 Jan 2022 14:07:39 +0000 (15:07 +0100)]
[llvm][vfs] Abstract in-memory node creation
The creation of in-memory VFS nodes happens in a single function that deduces what kind of node to create from the arguments. This leads to complicated if-then-else logic that's difficult to cleanly extend.
This patch abstracts away in-memory node creation via a type-erased factory function that's passed instead.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D117648
Jan Svoboda [Thu, 20 Jan 2022 14:05:38 +0000 (15:05 +0100)]
[llvm][vfs] NFC: Virtualize in-memory `getStatus`
This patch virtualizes the `getStatus` function on `InMemoryNode` in LLVM VFS. Currently, this is implemented via top-level function `getNodeStatus` that tries to cast `InMemoryNode *` into each subtype. Virtual functions seem to be the simpler solution here.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D117649
Stephan Herhut [Thu, 20 Jan 2022 13:02:04 +0000 (14:02 +0100)]
[mlir][memref] Add better support for identity layouts in memref.collapse_shape canonicalizer
When computing the new type of a collapse_shape operation, we need to at least
take into account whether the type has an identity layout, in which case we can
easily support dynamic strides. Otherwise, the canonicalizer creates invalid
IR.
Longer term, both the verifier and the canoncializer need to be extended to
support the general case.
Differential Revision: https://reviews.llvm.org/D117772
Stanislav Gatev [Thu, 20 Jan 2022 09:28:25 +0000 (09:28 +0000)]
[clang][dataflow] Intersect ExprToLoc when joining environments
This is part of the implementation of the dataflow analysis framework.
See "[RFC] A dataflow analysis framework for Clang AST" on cfe-dev.
Reviewed-by: xazax.hun
Differential Revision: https://reviews.llvm.org/D117754
Valentin Clement [Thu, 20 Jan 2022 14:18:47 +0000 (15:18 +0100)]
[flang][NFC] Remove extra braces
Noticed during the upstreaming process.
Mubashar Ahmad [Thu, 23 Dec 2021 16:37:44 +0000 (16:37 +0000)]
[Clang][AArch64][ARM] Unaligned Access Warning Added
Added warning for potential cases of
unaligned access when option
-mno-unaligned-access has been specified
Differential Revision: https://reviews.llvm.org/D116221
Nikita Popov [Thu, 20 Jan 2022 13:49:12 +0000 (14:49 +0100)]
[EarlyCSE] Regenerate test checks (NFC)
Florian Hahn [Thu, 20 Jan 2022 13:45:19 +0000 (13:45 +0000)]
[IRGen] Do not overwrite existing attributes in CGCall.
When adding new attributes, existing attributes are dropped. While
this appears to be a longstanding issue, this was highlighted by D105169
which dropped a lot of attributes due to adding the new noundef
attribute.
Ahmed Bougacha (@ab) tracked down the issue and provided the fix in
CGCall.cpp. I bundled it up and updated the tests.
Simon Tatham [Thu, 20 Jan 2022 13:22:34 +0000 (13:22 +0000)]
[AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.
The Armv8-R.64 architecture defines numbered MPU region registers with
indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or
PRLAR0_EL1 (for example). The encodings that they would occupy are
used for the unnumbered PRBAR_ELn and PRLAR_ELn registers.
Reviewed By: labrinea
Differential Revision: https://reviews.llvm.org/D117755
Simon Tatham [Thu, 20 Jan 2022 09:31:11 +0000 (09:31 +0000)]
[MC] Add a disassembly test for Armv8-R sysregs.
This is the counterpart to llvm/test/MC/AArch64/armv8r-sysreg.s,
checking all the same encodings when fed to the disassembler.
Abinav Puthan Purayil [Thu, 20 Jan 2022 09:59:57 +0000 (15:29 +0530)]
[AMDGPU] Set MemoryVT for truncstores in tblgen.
GlobalISelEmitter was skipping these patterns when its predicates were
checked. This patch should allow us to select d16_hi stores in
GlobalISel.
Differential Revision: https://reviews.llvm.org/D117762
Marek Kurdej [Thu, 20 Jan 2022 13:03:18 +0000 (14:03 +0100)]
[clang-format] Indicate source location on test failure. NFC.
Simon Pilgrim [Thu, 20 Jan 2022 12:50:47 +0000 (12:50 +0000)]
[X86] combineConcatVectorOps - remove superfluous Subtarget.hasAVX() check
This function only ever gets called by AVX targets, and we already assert for this at the top of the function
Simon Pilgrim [Thu, 20 Jan 2022 12:47:08 +0000 (12:47 +0000)]
[X86] combineConcatVectorOps - add handling for X86ISD::VSHL/VSRL/VSRA
These can be handled the same as the vector shift by immediate variants that are already handled.
Jay Foad [Thu, 20 Jan 2022 12:31:12 +0000 (12:31 +0000)]
[AMDGPU] Regenerate some MIR checks
Valentin Clement [Thu, 20 Jan 2022 12:34:29 +0000 (13:34 +0100)]
[flang][NFC] Move current inliner files in Dialect directory
This patch just move the files from the Transforms directory to
the Dialect directory.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D117661
Valentin Clement [Thu, 20 Jan 2022 12:33:38 +0000 (13:33 +0100)]
[flang][NFC] Cleanup dependent dialects and make def homogenous
Remove unnecessary dependent dialect and make the definition of the
pass more homogenous with the two others.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D117688
Fraser Cormack [Wed, 19 Jan 2022 17:40:33 +0000 (17:40 +0000)]
[RISCV] Match RVV VF variants also through masked operations
This brings floating-point RVV vector/scalar support more in line with
the integer vector patterns, which can already match '.vx' instructions
with masked operations.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117697
Peter Waller [Thu, 20 Jan 2022 12:01:23 +0000 (12:01 +0000)]
Revert "[AArch64][SVE][VLS] Move extends into arguments of comparisons"
This reverts commit
db04d3e30b3878ae39ef64eb0b0a1538644c7f6a, which
causes a buildbot failure.
Fraser Cormack [Wed, 19 Jan 2022 16:17:59 +0000 (16:17 +0000)]
[RISCV] Optimize lowering of floating-point -0.0
This idea has come up in several reviews -- D115978 and D105902 -- so I
can't take any credit for the idea. Instead of using a constant pool to
lower -0.0, we can emit a sequence of two instructions:
fmv.[hwd].x freg, zero
fsgnjn.[hsd] freg, freg, freg
This is only done when the floating-point type is legal.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117687
Prashant Kumar [Sun, 16 Jan 2022 15:47:03 +0000 (21:17 +0530)]
[MLIR] The return type in the `computeSingleVarRepr` function is modified to include equality expressions.
Earlier `computeSingleVarRepr` was returning a pair of upper bound and
lower bound indices of the inequality contraints that can be expressed
as a floordiv of an affine function. The equality expression can also be
expressed as a floordiv but contains only one index and hence the `LocalRepr`
class is introduced to facilitate this.
Reviewed By: Groverkss
Differential Revision: https://reviews.llvm.org/D117430
David Spickett [Wed, 12 Jan 2022 14:55:31 +0000 (14:55 +0000)]
[lldb] Remove non-address bits from addresses given to memory tag commands
Although the memory tag commands use a memory tag manager to handle
addresses, that only removes the top byte.
That top byte is 4 bits of memory tag and 4 free bits, which is more
than it should strictly remove but that's how it is for now.
There are other non-address bit uses like pointer authentication.
To ensure the memory tag manager only has to deal with memory tags,
use the ABI plugin to remove the rest.
The tag access test has been updated to sign all the relevant pointers
and require that we're running on a system with pointer authentication
in addition to memory tagging.
The pointers will look like:
<4 bit user tag><4 bit memory tag><signature><bit virtual address>
Note that there is currently no API for reading memory tags. It will
also have to consider this when it arrives.
Reviewed By: omjavaid
Differential Revision: https://reviews.llvm.org/D117672
David Spickett [Wed, 12 Jan 2022 13:30:25 +0000 (13:30 +0000)]
[lldb] Rename MemoryTagManager RemoveNonAddressBits to RemoveTagBits
This better describes the intent of the method. Which for AArch64
is removing the top byte which includes the memory tags.
It does not include pointer signatures, for those we need to use
the ABI plugin. The rename makes this a little more clear.
It's a bit awkward that the memory tag manager is removing the whole
top byte not just the memory tags but it's an improvement for now.
Reviewed By: omjavaid
Differential Revision: https://reviews.llvm.org/D117671
Florian Hahn [Thu, 20 Jan 2022 10:22:20 +0000 (10:22 +0000)]
[IRBuilder] Migrate and-folding to value-based FoldAnd.
Similar to the migration of or-folding to FoldOr, there are a few cases
where the fold in IRBuilder::CreateAnd triggered directly. Those have
been updated.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D117431
Valentin Clement [Thu, 20 Jan 2022 09:56:23 +0000 (10:56 +0100)]
[flang][NFC] Fix header guard and comment
Casey Carter [Thu, 20 Jan 2022 09:46:58 +0000 (01:46 -0800)]
[libcxx][test] Use TEST_HAS_BUILTIN in test code
... rather than using `__has_builtin` directly. This both (1) allows a compiler that doesn't speak `__has_builtin` to workaround with preprocessor magic, and (2) avoids diagnostics about things that look like function like macros after `#if` but are not.
eopXD [Sat, 6 Nov 2021 09:05:43 +0000 (02:05 -0700)]
[RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap
Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. This makes
clang_cc1 fail to imply into `zve32x` for the vector extension, and test
cases will have to add ` -target-feature +experimental-zve32x` in order
to work.
This patch fixes it.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D113336
Valentin Clement [Thu, 20 Jan 2022 09:23:47 +0000 (10:23 +0100)]
[flang][NFC] Fix header guard
Fix header guard to fit other files.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D117662
Matthias Springer [Thu, 20 Jan 2022 09:14:59 +0000 (18:14 +0900)]
[mlir][bufferization] Move one-shot bufferization to Bufferization dialect
This commit is the first step towards unifying core bufferization and One-Shot Bufferize.
This commit does not move over the implementations of BufferizableOpInterface yet. This will be done in separate commits. This change does also not move the unit tests yet. The tests will be moved together with op interface implementations and split into separate files.
Differential Revision: https://reviews.llvm.org/D117641
David Spickett [Wed, 19 Jan 2022 16:56:41 +0000 (16:56 +0000)]
[llvm][AArch64] Accept armv8.8 "hbc" and "mops" in .arch_extension directive
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D117693
Victor Perez [Thu, 20 Jan 2022 08:13:00 +0000 (08:13 +0000)]
[LegalizeTypes][VP] Add widening support for vp.gather and vp.scatter
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117557
Marek Kurdej [Thu, 20 Jan 2022 08:35:09 +0000 (09:35 +0100)]
[clang-format] Add tests for aligning `operator=` with `=delete`. NFC.
Also, add test case from https://github.com/llvm/llvm-project/issues/33044.
This was actually fixed in https://github.com/llvm/llvm-project/commit/
480a1fab72f4e367a5986d572914d252c318431d, but there were no tests for delete.
Nikita Popov [Wed, 5 Jan 2022 08:48:17 +0000 (09:48 +0100)]
Reapply [MemCpyOpt] Look through pointer casts when checking capture
This is a recommit of the patch without changes. The reason for
the revert has been addressed in D117679.
-----
The user scanning loop above looks through pointer casts, so we
also need to strip pointer casts in the capture check. Previously
the source was incorrectly considered not captured if a bitcast
was passed to the call.
Nikita Popov [Mon, 13 Dec 2021 09:54:53 +0000 (10:54 +0100)]
Reapply [MemCpyOpt] Make capture check during call slot optimization more precise
This is a recommit of the patch without changes. The reason for
the revert has been addressed in D117679.
-----
Call slot optimization is currently supposed to be prevented if
the call can capture the source pointer. Due to an implementation
bug, this check currently doesn't trigger if a bitcast of the source
pointer is passed instead. I'm somewhat afraid of the fallout of
fixing this bug (due to heavy reliance on call slot optimization
in rust), so I'd like to strengthen the capture reasoning a bit first.
In particular, I believe that the capture is fine as long as a)
the call itself cannot depend on the pointer identity, because
neither dest has been captured before/at nor src before the
call and b) there is no potential use of the captured pointer
before the lifetime of the source alloca ends, either due to
lifetime.end or a return from a function. At that point the
potentially captured pointer becomes dangling.
Differential Revision: https://reviews.llvm.org/D115615
Richard [Thu, 20 Jan 2022 08:21:46 +0000 (01:21 -0700)]
[clang-tidy] Revert documentation change (NFC)
Restore a fix to the list of checks that was undone by a recent commit.
Chenbing.Zheng [Thu, 20 Jan 2022 08:14:28 +0000 (08:14 +0000)]
[RISCV] Add intrinsic for Zbt extension
RV32: fsl, fsr, fsri
RV64: fsl, fsr, fsri, fslw, fsrw, fsriw
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117468
Nikita Popov [Wed, 19 Jan 2022 14:47:13 +0000 (15:47 +0100)]
[MemCpyOpt] Fix metadata merging during call slot optimization
Call slot optimization currently merges the metadata between the
call and the load. However, we also need to merge in the metadata
of the store.
Part of the reason why we might have gotten away with this
previously is that usually the load and the store are the same
instruction (a memcpy), this can only happen if call slot
optimization occurs on an actual load/store pair.
This addresses the issue reported in
https://reviews.llvm.org/D115615#3251386.
Differential Revision: https://reviews.llvm.org/D117679
Nikita Popov [Wed, 19 Jan 2022 13:33:21 +0000 (14:33 +0100)]
[Support] Remove incorrect noalias return attribute in BumpPtrAllocator
The memory returned by the Allocate() function is also otherwise
accessible -- and is indeed accessed by the DestroyAll() method of
SpecificBumpPtrAlloactor. This is a violation of the noalias return
contract.
This should address the issue reported in
https://reviews.llvm.org/D116728#3252464.
Differential Revision: https://reviews.llvm.org/D117664
Jez Ng [Thu, 20 Jan 2022 07:59:12 +0000 (23:59 -0800)]
[lld-macho] Fix grammar in doc
Jino Park [Thu, 20 Jan 2022 07:42:19 +0000 (08:42 +0100)]
[clang-format] Fix bug in parsing `operator<` with template
Fixes https://github.com/llvm/llvm-project/issues/44601.
This patch handles a bug when parsing a below example code :
```
template <class> class S;
template <class T> bool operator<(S<T> const &x, S<T> const &y) {
return x.i < y.i;
}
template <class T> class S {
int i = 42;
friend bool operator< <>(S const &, S const &);
};
int main() { return S<int>{} < S<int>{}; }
```
which parse `< <>` as `<< >`, not `< <>` in terms of tokens as discussed in discord.
1. Add a condition in `tryMergeLessLess()` considering `operator` keyword and `>`
2. Force to leave a whitespace between `tok::less` and a template opener
3. Add unit test
Reviewed By: MyDeveloperDay, curdeius
Differential Revision: https://reviews.llvm.org/D117398
eopXD [Wed, 27 Oct 2021 12:52:20 +0000 (05:52 -0700)]
[RISCV] Add the zve extension according to the v1.0 spec
`zve` is the new standard vector extension to specify varying degrees of
vector support for embedding processors. The `zve` extension is related
to the `zvl` extension and other updates that are added in v1.0.
According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21,
Clang defines macro `__riscv_v_max_elen`, `__riscv_v_max_elen_fp` for
`zve` and it can be used by applications that uses the vector extension.
Authored by: Zakk Chen <zakk.chen@sifive.com> @khchen
Co-Authored by: Eop Chen <eop.chen@sifive.com> @eopXD
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D112408
Lang Hames [Thu, 20 Jan 2022 06:58:37 +0000 (17:58 +1100)]
[ORC] Fix another missing std::move from
9eb4939b862.
Lang Hames [Thu, 20 Jan 2022 06:56:56 +0000 (17:56 +1100)]
[ORC] Fix missing std::move from
9eb4939b862.
Lang Hames [Thu, 20 Jan 2022 03:21:36 +0000 (14:21 +1100)]
[ORC] Allow JITDylib::getDFSLinkOrder and friends to fail for defunct JITDylibs.
Calls to JITDylib's getDFSLinkOrder and getReverseDFSLinkOrder methods (both
static an non-static versions) are now valid to make on defunct JITDylibs, but
will return an error if any JITDylib in the link order is defunct.
This means that platforms can safely lookup link orders by name in response to
jit-dlopen calls from the ORC runtime, even if the call names a defunct
JITDylib -- the call will just fail with an error.
Fangrui Song [Thu, 20 Jan 2022 06:33:32 +0000 (22:33 -0800)]
[ELF] Replace .zdebug string comparison with SHF_COMPRESSED check. NFC
Jonas Devlieghere [Thu, 20 Jan 2022 05:50:51 +0000 (21:50 -0800)]
[dsymutil] Don't print timestamp warning if we have no timestamp
If we have no timestamp (0), don't print the corresponding warning. The
binary holder already successfully ignores these cases, but the warning
for swift interface files was lacking it.
rdar://
86036385
Differential revision: https://reviews.llvm.org/D117333
Johannes Doerfert [Sat, 8 Jan 2022 22:53:19 +0000 (16:53 -0600)]
[OpenMP][AMDGPU] Optimize the linked in math libraries
Once we linked in math files, potentially even if we link in only other
"system libraries", we want to optimize the code again. This is not only
reasonable but also helps to hide various problems with the missing
attribute annotations in the math libraries.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D116906
Jim Lin [Thu, 20 Jan 2022 02:52:26 +0000 (10:52 +0800)]
[M68k][NFC] Rename Bt(BT) to Btst(BTST)
It seems that implementation of Bt refered from x86.
In M68k, Bt(BT) should be renamed to Btst(BTST).
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D117534
Johannes Doerfert [Wed, 3 Nov 2021 16:52:21 +0000 (11:52 -0500)]
[OpenMP] Avoid costly shadow map traversals whenever possible
In the OpenMC app we saw `omp target update` spending an awful lot of
time in the shadow map traversal without ever doing any update there.
There are two cases that allow us to avoid the traversal completely.
The simplest thing is that small updates cannot (reasonably) contain
an attached pointer part. The other case requires to track in the
mapping table if an entry might contain an attached pointer as part.
Given that we have a single location shadow map entries are created,
the latter is actually fairly easy as well.
Differential Revision: https://reviews.llvm.org/D113124
Johannes Doerfert [Wed, 19 Jan 2022 00:56:10 +0000 (18:56 -0600)]
[OpenMP] Introduce an environment variable to disable atomic map clauses
Atomic handling of map clauses was introduced to comply with the OpenMP
standard (see D104418). However, many apps won't need this feature which
can be costly in certain situations. To allow for applications to
opt-out we now introduce the `LIBOMPTARGET_MAP_FORCE_ATOMIC` environment
flag that voids the atomicity guarantee of the standard for map clauses
again, shifting the burden to the user.
This patch also de-duplicates the code that introduces the events used
to enforce atomicity as a cleanup.
Differential Revision: https://reviews.llvm.org/D117627
Heejin Ahn [Sat, 4 Sep 2021 06:31:52 +0000 (23:31 -0700)]
[WebAssembly] Support Wasm EH + Wasm SjLj
D108960 added support for SjLj using Wasm EH instructions, which we call
Wasm SjLj going forward. (We call the old SjLj Emscripten SjLj) But it
did not support using Wasm EH and Wasm SjLj together. So far users of
Wasm EH had to use Wasm EH with Emscripten SjLj, which had a certain
limitation and it suffered from bigger code size increases as well.
This enables using Wasm EH and Wasm SjLj together.
1. This redirects `catchswitch` and `cleanupret` that unwind to caller
to `catch.dispatch.longjmp` BB, which is a `catchswitch` BB that
handles longjmps.
2. D108960 converted all longjmpable `call`s to `invokes` that unwind to
`catch.dispatch.longjmp`. This CL checks if the `call` is embedded
within another `catchpad`, and if so, makes it unwind to its nearest
parent's unwind destination, rather than `catch.dispatch.longjmp`.
This is necessary to preserve the scoping structure.
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D117610
Fangrui Song [Thu, 20 Jan 2022 04:09:41 +0000 (20:09 -0800)]
[ELF] Remove StringRefZ
StringRefZ does not improve performance. Non-local symbols always have eagerly
computed nameSize. Most local symbols's lengths will be updated in either:
* shouldKeepInSymtab
* SymbolTableBaseSection::addSymbol
Its benefit is offsetted by strlen in every call site (sums up to 5KiB code in a
release x86-64 build), so using StringRefZ may be slower.
In a -s link (uncommon) there is minor speedup, like ~0.3% for clang and chrome.
Reviewed By: alexander-shaposhnikov
Differential Revision: https://reviews.llvm.org/D117644
River Riddle [Thu, 20 Jan 2022 03:24:08 +0000 (19:24 -0800)]
[mlir] Fix GCC5 build broken by improper name redefinition
Luo, Yuanke [Wed, 29 Dec 2021 08:05:32 +0000 (16:05 +0800)]
Combine to vpdpbusd when operand is constant and small enough.
Differential Revision: https://reviews.llvm.org/D116363
Ben Shi [Thu, 30 Dec 2021 07:59:30 +0000 (07:59 +0000)]
[AVR] Generate ELPM for loading byte/word from extended program memory
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D116493
Ben Shi [Sat, 18 Dec 2021 10:03:11 +0000 (10:03 +0000)]
[AVR][MC] Generate section '.progmemX.data' for extended flash banks
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D115987
Hsiangkai Wang [Thu, 20 Jan 2022 01:32:53 +0000 (01:32 +0000)]
[RISCV] Add a test to show the bug in the RA caused by reserved BP.
The bug is reported in https://github.com/llvm/llvm-project/issues/53016.
Authored-by: Kito Cheng <kito.cheng@sifive.com>
Differential Revision: https://reviews.llvm.org/D117738
Nico Weber [Thu, 20 Jan 2022 02:15:31 +0000 (21:15 -0500)]
[gn build] (manually) port
30c17e70a4d7
minglotus-6 [Thu, 13 Jan 2022 20:44:15 +0000 (12:44 -0800)]
[llvm-dis] Add an option `dump-thinlto-index-only` in llvm-dis to read ThinLTO minimized code only.
Mircea Trofin [Thu, 20 Jan 2022 01:51:42 +0000 (17:51 -0800)]
[MLGO] Don't run the 'release' mode tests in non-autogenerated cases
Adrian Tong [Tue, 23 Nov 2021 00:11:45 +0000 (00:11 +0000)]
Optimize shift and accumulate pattern in AArch64.
AArch64 supports unsigned shift right and accumulate. In case we see a
unsigned shift right followed by an OR. We could turn them into a USRA
instruction, given the operands of the OR has no common bits.
Differential Revision: https://reviews.llvm.org/D114405
Craig Topper [Thu, 20 Jan 2022 01:52:09 +0000 (17:52 -0800)]
[LoopPeel] Pass TripCount to computePeelCount by value instead of by reference. NFC
The TripCount is not modified by the function so it doesn't need
to be passed by reference. Verified by passing it as const reference
before changing to value.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D117735
Peter Klausler [Tue, 11 Jan 2022 19:24:55 +0000 (11:24 -0800)]
[flang] Accept INDEX(..., BACK=array)
The intrinsic table entry for INDEX mistakenly required
the optional BACK= argument to be scalar, but it's an
elemental intrinsic that can accept a conforming array.
Differential Revision: https://reviews.llvm.org/D117700
Peter Klausler [Tue, 11 Jan 2022 20:28:35 +0000 (12:28 -0800)]
[flang] Accept sparse argument keyword names for MAX/MIN
Accept any keyword argument names of the form "An" for
values of n >= 3 in calls to the intrinsic functions MAX, MIN,
and their variants, so long as "n" has no leading zero and
all the keywords are distinct. Previously, f18 was needlessly
requiring the names to be contiguous. When synthesizing keywords
to characterize the procedure's interface, don't conflict with
the program's keywords.
Differential Revision: https://reviews.llvm.org/D117701
River Riddle [Wed, 19 Jan 2022 02:28:51 +0000 (18:28 -0800)]
[mlir] Make locations required when adding/creating block arguments
BlockArguments gained the ability to have locations attached a while ago, but they
have always been optional. This goes against the core tenant of MLIR where location
information is a requirement, so this commit updates the API to require locations.
Fixes #53279
Differential Revision: https://reviews.llvm.org/D117633
Mohammed Nurul Hoque [Thu, 20 Jan 2022 01:27:02 +0000 (17:27 -0800)]
[RISCV] Add patterns to MIR sign-extension removal pass.
This patch adds a few instruction patterns that generate sign-extended values or propagate them, adding to the pass introduced in https://reviews.llvm.org/D116397
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117465
Peter Klausler [Tue, 11 Jan 2022 18:38:26 +0000 (10:38 -0800)]
[flang] Accept BOZ literals for some actual arguments
Consistent with previously documented policy, in which
BOZ literals are accepted in non-standard-conforming circumstances
where they can be converted to an unambiguous known numeric type,
allow BOZ literals to be passed as an actual argument in a reference
to a procedure whose explicit interface has a corresponding dummy
argument with a numeric type to which the BOZ literal may be
converted. Improve error messages associated with BOZ literal
actual arguments, too: don't emit multiple errors.
Differential Revision: https://reviews.llvm.org/D117698
Peter Klausler [Tue, 11 Jan 2022 19:01:12 +0000 (11:01 -0800)]
[flang] Improve error message (initialized variable in pure subprogram)
When variable with the SAVE attribute appears in a pure subprogram,
emit a more specialized error message if the SAVE attribute was acquired
from static initialization.
Differential Revision: https://reviews.llvm.org/D117699
Joseph Huber [Wed, 19 Jan 2022 19:52:08 +0000 (14:52 -0500)]
[OpenMP] Expand short verisions of OpenMP offloading triples
The OpenMP offloading libraries are built with fixed triples and linked
in during compile time. This would cause un-helpful errors if the user
passed in the wrong expansion of the triple used for the bitcode
library. because we only support these triples for OpenMP offloading we
can normalize them to the full verion used in the bitcode library.
Reviewed By: jdoerfert, JonChesterfield
Differential Revision: https://reviews.llvm.org/D117634
Hsiangkai Wang [Tue, 18 Jan 2022 07:44:27 +0000 (07:44 +0000)]
[docs] Fix typo in the example code in ProgrammersManual.
Differential Revision: https://reviews.llvm.org/D117665