Krzysztof Parzyszek [Sun, 13 Nov 2022 21:10:06 +0000 (15:10 -0600)]
[Hexagon] Use `Register` instead of `unsigned`, NFC
Use `Register` instead of `unsigned` in HexagonInstrInfo,
HexagonRegisterInfo, HexagonFrameLowering, and HexagonHardwareLoops.
Arthur Eubanks [Sun, 13 Nov 2022 22:21:12 +0000 (14:21 -0800)]
[lldb][test] Avoid UB in optimized_code test
Florian Hahn [Sun, 13 Nov 2022 22:05:37 +0000 (22:05 +0000)]
[VectorUtils] Skip interleave members with diff type and alloca sizes.
Currently, codegen doesn't support cases where the type size doesn't
match the alloc size. Skip them for now.
Fixes #58722.
Arthur Eubanks [Sun, 13 Nov 2022 22:02:24 +0000 (14:02 -0800)]
[clang][test] Avoid UB in overload.cl
Krzysztof Parzyszek [Sun, 13 Nov 2022 20:33:26 +0000 (14:33 -0600)]
[Hexagon] Pass Hexagon::PC to InitializeHexagonMCRegisterInfo
That will make MCRegisterInfo::getProgramCounter return the right thing.
Krzysztof Parzyszek [Sun, 13 Nov 2022 20:32:18 +0000 (14:32 -0600)]
[Hexagon] Remove unneeded HexagonRegisterInfo::getRARegister
That function exists in MCRegisterInfo, and is inherited into HRI.
Krzysztof Parzyszek [Sun, 13 Nov 2022 19:56:06 +0000 (13:56 -0600)]
[Hexagon] Reduce the spill alignment for double/quad vector classes
The spill alignment for HVX vectors is always the single vector size,
regardless of whether the class describes vector tuples or not.
Craig Topper [Sun, 13 Nov 2022 19:52:14 +0000 (11:52 -0800)]
[RISCV] Add BREV8 to hasAllWUsers in RISCVSExtWRemoval.
This instruction reverses the bits in each byte. Since we're only
interested in whether the upper 32 bits are used or not, we can
look through them to check their users.
Craig Topper [Sun, 13 Nov 2022 19:34:06 +0000 (11:34 -0800)]
[RISCV] Add PACK/PACKH/PACKW to hasAllWUsers in RISCVSExtWRemoval.
Renato Golin [Sat, 12 Nov 2022 21:48:54 +0000 (21:48 +0000)]
[MLIR] Move JitRunner Options to header, pass to mlirTransformer
This allows the MLIR transformer to see the command line options and
make desicions based on them. No change upstream, but my use-case is to
look at the entry point name and type to make sure I can use them.
Differential Revision: https://reviews.llvm.org/D137861
Krzysztof Parzyszek [Sat, 12 Nov 2022 23:27:59 +0000 (17:27 -0600)]
Move variable declarations out of #if guard, NFC
They are used in other sides of the #if/#else.
Florian Hahn [Sun, 13 Nov 2022 17:38:39 +0000 (17:38 +0000)]
[SimpleLoopUnswitch] Forget SCEVs for replaced phis.
Forget SCEVs based on exit phis in case SCEV looked through the phi.
After unswitching, it may not be possible to look through the phi due to
it having multiple incoming values, so it needs to be re-computed.
Fixes #58868
bzcheeseman [Fri, 11 Nov 2022 19:22:06 +0000 (11:22 -0800)]
[MLIR][Bytecode] Ensure `dataIt` is aligned coming out of `EncodingReader::alignTo`.
This addresses the TODO in the code previously and checks that the address of `dataIt` is properly aligned to the requested alignment.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D137855
Simon Pilgrim [Sun, 13 Nov 2022 17:12:18 +0000 (17:12 +0000)]
[X86] Regenerate combine-movmsk.ll
Adds a AVX check that we lost at some point
Sanjay Patel [Sun, 13 Nov 2022 16:47:21 +0000 (11:47 -0500)]
Revert "[InstCombine] allow more folds for multi-use selects (2nd try)"
This reverts commit
6eae6b3722d9204fa93b772e24afab93406cc143.
This version of the patch results in the same DFSAN bot failure as before,
so my guess about the SimplifyQuery context instruction was wrong.
I don't know what the real bug is.
Sanjay Patel [Sun, 13 Nov 2022 15:19:41 +0000 (10:19 -0500)]
[InstCombine] allow more folds for multi-use selects (2nd try)
The 1st try (
681a6a399022 ) was reverted because it caused
a DataFlowSanitizer bot failure.
This try modifies the existing calls to simplifyBinOp() to
not use a query that sets the context instruction because
that seems like a likely source of failure. Since we already
try those simplifies with multi-use patterns in some cases,
that means the bug is likely present even without this patch.
However, I have not been able to reduce a test to prove that
this was the bug, so if we see any bot failures with this patch,
then it should be reverted again.
The reduced simplify power does not affect any optimizations
in existing, motivating regression tests.
Original commit message:
The 'and' case showed up in a recent bug report and prevented
more follow-on transforms from happening.
We could handle more patterns (for example, the select arms
simplified, but not to constant values), but this seems
like a safe, conservative enhancement. The backend can
convert select-of-constants to math/logic in many cases
if it is profitable.
There is a lot of overlapping logic for these kinds of patterns
(see SimplifySelectsFeedingBinaryOp() and FoldOpIntoSelect()),
so there may be some opportunity to improve efficiency.
There are also optimization gaps/inconsistency because we do
not call this code for all bin-opcodes (see TODO for ashr test).
Simon Pilgrim [Sun, 13 Nov 2022 15:19:30 +0000 (15:19 +0000)]
[X86] Update WriteMPSAD class and remove VMPSADBWrri override
AMD 15h SoG + Agner both indicate there's no difference between MPSADBWrri + VMPSADBWrri - I can't find any data on the folded variant so I've kept the existing numbers
Removes the last X86 override for WriteMPSAD/WritePSADBW classes - removing a further 3 entries from every sched class table
Simon Pilgrim [Sun, 13 Nov 2022 14:54:16 +0000 (14:54 +0000)]
[X86] Remove unnecessary VPSADBW/VDBPSADBW zmm overrides
These match the existing WritePSADBWZ schedule classes
Simon Pilgrim [Sun, 13 Nov 2022 14:49:29 +0000 (14:49 +0000)]
[MCA][X86] Add test coverage for VDBPSADBW instructions
Nico Weber [Thu, 10 Nov 2022 13:59:44 +0000 (08:59 -0500)]
[gn build] Extract gen_arch_intrinsics() template to remove some duplication
No behavior change.
Differential Revision: https://reviews.llvm.org/D137784
Simon Pilgrim [Sun, 13 Nov 2022 14:10:03 +0000 (14:10 +0000)]
[X86] Fix scheduler tag for GFNI YMM instructions
These were hardcoded to XMM width
chenglin.bi [Sun, 13 Nov 2022 11:19:38 +0000 (19:19 +0800)]
[GlobalISel] Correct constant type in matchReassocConstantInnerLHS
When we match a pattern from m_GCst, the register type could be different from original op. So we can't replace the original op to vreg direct.
This code create a new constant with original op type then replace the original op.
Fix #58906
Reviewed By: arsenm, aemerson
Differential Revision: https://reviews.llvm.org/D137778
Simon Pilgrim [Sun, 13 Nov 2022 11:13:30 +0000 (11:13 +0000)]
[X86] Cleanup CVTPD2PS schedule values
The znver1/znver2 schedules for CVTPD2PS were incorrectly double pumping the xmm-load variant instead of the ymm variants (znver1 only)
Also, the xmm-load variant was incorrectly using FP03 instead of just FP3
Confirmed by the AMD SoG 17h tables, Agner + uops.info
Another step towards removing a lot of unnecessary overrides from all the x86 scheduler models - these should hopefully be convertible into regular WriteCvtPD2I classes soon.
Simon Pilgrim [Sun, 13 Nov 2022 09:34:19 +0000 (09:34 +0000)]
[X86] Fix sched class typo - the CVTPD2DQrr instructions were mapping to ZnWriteCVTDQ2PDr instead of ZnWriteCVTPD2DQr
Fangrui Song [Sun, 13 Nov 2022 09:15:54 +0000 (01:15 -0800)]
DecoderEmitter: Simplify addOneOperandFields. NFC
Follow-up to
d1fbdf5bf79219549bc1fde255186d02f646a46f
Fangrui Song [Sun, 13 Nov 2022 08:48:47 +0000 (00:48 -0800)]
[TableGen] Remove unneeded flush and add missing newline
Michał Górny [Sun, 13 Nov 2022 06:27:01 +0000 (07:27 +0100)]
Revert "[InstCombine] allow more folds more multi-use selects"
This reverts commit
681a6a3990226c667fb648952731d2753df2716d.
It broke sanitizer tests (as seen on buildbots), see:
https://reviews.llvm.org/rG681a6a399022#1143137
zhongyunde [Sun, 13 Nov 2022 03:01:45 +0000 (11:01 +0800)]
[AArch64] Optimize more memcmp when the result is tested for [in]equality with 0
We already surpport the or (xor a, b), (xor c, d) with D136244, while it should
capture more cases than just bcmp according the comment on
https://reviews.llvm.org/D136672, so this patch try to fold continuous
comparison series.
Also add a new callsite in LowerSETCC to address some cases folded And in the
stage of `Optimized type-legalized selection`.
Depends on D136244
Reviewed By: dmgreen, bcl5980
Differential Revision: https://reviews.llvm.org/D137721
Mehdi Amini [Thu, 3 Nov 2022 20:53:35 +0000 (20:53 +0000)]
Apply clang-tidy fixes for readability-container-size-empty in ExecutionEngine.cpp (NFC)
Mehdi Amini [Thu, 3 Nov 2022 20:45:39 +0000 (20:45 +0000)]
Apply clang-tidy fixes for readability-identifier-naming in TosaDecomposeConv2D.cpp (NFC)
Roman Lebedev [Sat, 12 Nov 2022 22:58:07 +0000 (01:58 +0300)]
[NFC][Clang] Add some codegen tests for https://github.com/llvm/llvm-project/issues/58798
River Riddle [Sat, 12 Nov 2022 22:38:27 +0000 (14:38 -0800)]
[mlir] Add openInputFile overload that accepts the expected alignment
This just forwards to the alignment parameter on `MemoryBuffer::getFileOrSTDIN`.
River Riddle [Fri, 11 Nov 2022 09:54:45 +0000 (01:54 -0800)]
[MemoryBuffer] Allow optionally specifying desired buffer alignment
Underlying data may have requirements/expectations/etc. about
the run-time alignment. WritableMemoryBuffer currently uses
a 16 byte alignment, which works for many situations but not all.
Allowing a desired alignment makes it easier to reuse WritableMemoryBuffer
in situations of special alignment, and also removes a problem when
opening files with special alignment constraints. Large files generally
get mmaped, which has ~page alignment, but small files go through
WritableMemoryBuffer which has the much smaller alignment guarantee.
Differential Revision: https://reviews.llvm.org/D137820
River Riddle [Thu, 10 Nov 2022 04:59:40 +0000 (20:59 -0800)]
[mlir] Add a new AttrTypeReplacer class to simplify sub element replacements
We currently only have the SubElement interface API for attribute/type
replacement, but this suffers from several issues; namely that it doesn't
allow caching across multiple replacements (very common), and also
creates a somewhat awkward/limited API. The new AttrTypeReplacer class
allows for registering replacements using a much cleaner API, similarly to
the TypeConverter class, removes a lot of manual interaction with the
sub element interfaces, and also better enables large scale replacements.
Differential Revision: https://reviews.llvm.org/D137764
River Riddle [Wed, 9 Nov 2022 20:39:04 +0000 (12:39 -0800)]
[mlir] Don't include the attribute self type in a `params` directive
The self type is handled separately from normal parameters, and
the use of the params directive currently breaks attributes that
want to use it (e.g. in a struct directive).
Differential Revision: https://reviews.llvm.org/D137732
Dave Lee [Sat, 12 Nov 2022 22:16:41 +0000 (14:16 -0800)]
[lldb] Revert SBFileSpec.fullpath path separator fix
Primarily reverts
5223366416fb.
Dave Lee [Sat, 12 Nov 2022 22:11:43 +0000 (14:11 -0800)]
[lldb] Complete fix of test after
5223366416fb
Dave Lee [Sat, 12 Nov 2022 22:09:35 +0000 (14:09 -0800)]
[lldb] Fix test after
5223366416fb
Aiden Grossman [Sat, 12 Nov 2022 01:54:01 +0000 (01:54 +0000)]
[Docs] Minor Fixups in Advanced Builds Documentation
This patch makes some minor fixups in the PGO section of the advanced
builds documentation in preparation for some future changes. Some minor
formatting and wording changes are included to hopefully make the
documentation more clear.
Reviewed By: sylvestre.ledru
Differential Revision: https://reviews.llvm.org/D137880
Matt Arsenault [Sat, 12 Nov 2022 17:57:07 +0000 (09:57 -0800)]
AMDGPU: Add some tests for i1 sitofp/uitofp-like selects
Matt Arsenault [Sat, 12 Nov 2022 18:03:55 +0000 (10:03 -0800)]
AMDGPU: Switch some tests to generated checks
Guray Ozen [Sat, 12 Nov 2022 12:02:02 +0000 (13:02 +0100)]
[mlir][transform] Make `tile_to_foreach_thread_op` builder to use ArrayAttr
D137413 clarified `scf_foreach_thread` thread mapping nicely. `tile_to_foreach_thread_op` is one of the op that generates `scf_foreach_thread`, however, its builders are still having integer array.
This is bug fix of potential problem.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D137891
Simon Pilgrim [Sat, 12 Nov 2022 18:17:46 +0000 (18:17 +0000)]
[X86] IceLakeModel - conversion instructions don't use Port015
Fixes a lot of throughput mismatches - the more complicated conversion instructions use ICXPort5+ICXPort01, not ICXPort5+ICXPort015 (ICXPort015 is mainly used for basic Logic + blend ops)
Fixing this should allow us to remove a lot of unnecessary scheduler overrides from IceLakeModel
Confirmed by both Agner + uops.info
Kuba Mracek [Sat, 12 Nov 2022 18:16:34 +0000 (10:16 -0800)]
[lsan] Fix stack buffer overwrite in SuspendedThreadsListMac::GetRegistersAndSP
The call to the thread_get_state syscall (that fetches the register values for a thread) on arm64 is mistakenly claiming that the buffer to receive the register state is larger that its actual size on the stack -- the struct on the stack is arm_thread_state64_t, but the MACHINE_THREAD_STATE + MACHINE_THREAD_STATE_COUNT refer to the "unified arm state" struct (which is larger).
Fixes https://github.com/llvm/llvm-project/issues/58503.
Differential Revision: https://reviews.llvm.org/D137292
Louis Dionne [Sat, 12 Nov 2022 18:09:32 +0000 (08:09 -1000)]
[libc++] Make sure that we use the libc++ CI pipeline when no projects have changed
That is necessary for scheduled builds to work.
Louis Dionne [Sat, 12 Nov 2022 17:57:16 +0000 (07:57 -1000)]
[libc++] Remove unused variable in buildkite pipeline generation
Simon Pilgrim [Sat, 12 Nov 2022 17:38:29 +0000 (17:38 +0000)]
[MCA][X86] Add test coverage for VNNI instructions
Simon Pilgrim [Sat, 12 Nov 2022 17:37:09 +0000 (17:37 +0000)]
[MCA][X86] Add missing AVX-GFNI YMM test coverage
Simon Pilgrim [Sat, 12 Nov 2022 17:20:07 +0000 (17:20 +0000)]
[X86] Always classify gf2p8affineqb/gf2p8affineinvqb instructions with SchedWriteVecIMul
There was a mismatch between the AVX512 and SSE/AVX versions
Simon Pilgrim [Sat, 12 Nov 2022 17:02:32 +0000 (17:02 +0000)]
[MCA][X86] Add test coverage for GFNI instructions
Krzysztof Parzyszek [Wed, 28 Sep 2022 14:57:08 +0000 (07:57 -0700)]
[Hexagon] Improve idioms for fixed-point vector multiplication
Make the code more general, restore the ability to generate V6_vmpyhvsrs.
David Green [Sat, 12 Nov 2022 16:41:15 +0000 (16:41 +0000)]
[AArch64] Allow sinking both extract and splat to smull
We currently will sink either a splat or two extracts to a smull/umull.
There can be cases where we have both one operand as an extract and one
as a splat. This alters the areExtractShuffleVectors method to account
for that case.
Differential Revision: https://reviews.llvm.org/D137726
Simon Pilgrim [Sat, 12 Nov 2022 14:29:45 +0000 (14:29 +0000)]
[X86] Replace unnecessary SKL CVTSI2SS/CVTSI2SD overrides with better base class defs
The folded patterns were missing entirely - confirmed by both Agner + uops.info
Simon Pilgrim [Sat, 12 Nov 2022 13:45:16 +0000 (13:45 +0000)]
[MCA][X86][AVX512] Add test coverage for unsigned<->fp conversion instructions
Simon Pilgrim [Sat, 12 Nov 2022 12:39:59 +0000 (12:39 +0000)]
[X86] SkylakeServerModel - conversion instructions don't use Port015
Fixes a lot of throughput mismatches - the more complicated conversion instructions use SKXPort5+SKXPort01, not SKXPort5+SKXPort015 (SKXPort015 is mainly used for basic Logic + blend ops)
Fixing this should allow us to remove a lot of unnecessary scheduler overrides from SkylakeServerModel
Confirmed by both Agner + uops.info
Simon Pilgrim [Sat, 12 Nov 2022 12:15:56 +0000 (12:15 +0000)]
[X86] Replace unnecessary SKL CVTPD2DQ overrides with better base class defs
Also fixes some AVX missing folded instructions
Simon Pilgrim [Sat, 12 Nov 2022 10:37:33 +0000 (10:37 +0000)]
[X86] Tweak Alderlake instregex to match CodeGen-only and public scalar instruction ops
As detailed on #58792 the _Int postfix needs to be optional in the instregex to match both instructions - fixes mismatch warnings on a scheduler model verifier I'm working on
Simon Pilgrim [Sat, 12 Nov 2022 10:23:52 +0000 (10:23 +0000)]
[X86] Replace unnecessary SKL conversion overrides with better base class defs
Split various conversion instructions that use different scheduler pipes for the reg-reg and reg-mem variants (and not an additional Port23 uop for memory folding) - declare the classes separately instead of using the SKLWriteResPair helper
Brad Smith [Sat, 12 Nov 2022 09:54:41 +0000 (04:54 -0500)]
[Support/ELF] - Add OpenBSD PT_OPENBSD_MUTABLE constant.
OpenBSD commit for reference:
https://github.com/openbsd/src/commit/
bd249b5664da50f0178adea78250a7a0d8ea6566
Michał Górny [Sat, 12 Nov 2022 09:34:57 +0000 (10:34 +0100)]
[lldb] [cmake] Fix another typo in third-party/unittest path
wanglei [Sat, 12 Nov 2022 08:35:59 +0000 (16:35 +0800)]
[LoongArch] Implement MCTargetExpr::fixELFSymbolsInTLSFixups hook
Reviewed By: SixWeining, MaskRay
Differential Revision: https://reviews.llvm.org/D137628
Micah Weston [Sat, 12 Nov 2022 08:51:35 +0000 (00:51 -0800)]
[clang-format] Treats &/&& as reference when followed by ',' or ')'
Ran into an issue where function declarations inside function
scopes or uses of sizeof inside a function would treat the && in
'sizeof(Type &&)' as a binary operator.
Attempt to fix this by assuming reference when followed by ',' or
')'. Also adds tests for these.
Also hit an edge case in another test that treated "and" the same
as "&&" since it parses as C++. Changed the "and" to "also" so it
is no longer a keyword.
Fixes #58923.
Differential Revision: https://reviews.llvm.org/D137755
Owen Pan [Sat, 5 Nov 2022 11:09:13 +0000 (04:09 -0700)]
[clang-format] Correctly annotate function names before attributes
Fixes #58827.
Differential Revision: https://reviews.llvm.org/D137486
Craig Topper [Sat, 12 Nov 2022 08:31:31 +0000 (00:31 -0800)]
[RISCV] Rename template parameter. NFC
Craig Topper [Sat, 12 Nov 2022 07:05:34 +0000 (23:05 -0800)]
[RISCV] Use template to reduce some code. NFC
Fangrui Song [Sat, 12 Nov 2022 06:59:51 +0000 (22:59 -0800)]
Add back single quotes when dontcall attribute was split into dontcall-error/dontcall-warn
Single quotes were accidentally dropped in D110364.
Haohai Wen [Sat, 12 Nov 2022 04:30:04 +0000 (12:30 +0800)]
[X86] Reduce unnecessary instregex for AlderlakeP schedule model
Using instregex for simple instruction opcode is much slower than
instrs. This patch replaces them with instrs.
Github issue: 35303
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D137841
Amara Emerson [Sat, 12 Nov 2022 03:54:39 +0000 (19:54 -0800)]
[AArch64][GlobalISel] Select TBZ for icmp sge x, 0.
This results in some nice size improvements on -Os CTMark:
Program size.__text
sdag gisel diff
consumer-typeset/consumer-typeset 414124.00 414052.00 -0.0%
tramp3d-v4/tramp3d-v4 356840.00 356732.00 -0.0%
lencod/lencod 427560.00 427396.00 -0.0%
7zip/7zip-benchmark 568400.00 568172.00 -0.0%
Bullet/bullet 455660.00 455428.00 -0.1%
mafft/pairlocalalign 248236.00 248040.00 -0.1%
sqlite3/sqlite3 284404.00 284176.00 -0.1%
ClamAV/clamscan 381052.00 380604.00 -0.1%
SPASS/SPASS 411932.00 411296.00 -0.2%
kimwitu++/kc 439696.00 438992.00 -0.2%
Geomean difference -0.1%
Peiming Liu [Sat, 12 Nov 2022 01:00:44 +0000 (01:00 +0000)]
[mlir][sparse] fix incorrect coordinates ordering computed by the foreach operation.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137877
Raman Tenneti [Sat, 12 Nov 2022 02:11:06 +0000 (18:11 -0800)]
Removed tabs.
Raman Tenneti [Sat, 12 Nov 2022 02:00:01 +0000 (18:00 -0800)]
[libc] Implement gettimeofday
Implement gettimeofday per
.../onlinepubs/
9699919799/functions/gettimeofday.html.
This call clock_gettime to implement gettimeofday function.
Tested:
Limited unit test: This makes a call and checks that no error was
returned. Used nanosleep for 100 microseconds and verfified it
returns a value that elapses more than 100 microseconds and less
than 300 microseconds.
Co-authored-by: Jeff Bailey <jeffbailey@google.com>
Differential Revision: https://reviews.llvm.org/D137881
Dave Lee [Sat, 12 Nov 2022 00:19:03 +0000 (16:19 -0800)]
[lldb] Rewrite to assertEqual/assertNotEqual (NFC)
Using the more specific assert* methods results in more useful error message.
Matt Arsenault [Fri, 26 Jun 2020 03:57:30 +0000 (23:57 -0400)]
AMDGPU: Fold llvm.amdgcn.sqrt(undef)
Louis Dionne [Thu, 10 Nov 2022 03:00:32 +0000 (17:00 -1000)]
[libc++] Add a libc++ CI pipeline specific to Clang changes
This will ensure that Clang changes get tested against libc++.
Differential Revision: https://reviews.llvm.org/D137759
Matt Arsenault [Mon, 19 Sep 2022 18:04:12 +0000 (14:04 -0400)]
Analysis: Reorder code in isDereferenceableAndAlignedPointer
GEPs should be the most common and basic case, so try that first.
Matt Arsenault [Wed, 2 Nov 2022 21:46:00 +0000 (14:46 -0700)]
WebAssembly: Remove MachineFunction reference from MFI
The MachineFunctionInfo here is a bit awkward because
WasmEHInfo is in the MachineFunction but handled from
the target code. Either everything should move into WebAssembly
or into the MachineFunction for MIR serialization.
Matt Arsenault [Sat, 12 Nov 2022 00:13:40 +0000 (16:13 -0800)]
clang: Fix unnecessary truncation of resource limit values
Ye Luo [Sat, 12 Nov 2022 00:14:33 +0000 (18:14 -0600)]
Disable OMPD tests. Causing CMake issue.
Dave Lee [Fri, 11 Nov 2022 22:32:04 +0000 (14:32 -0800)]
[lldb] Fix SBFileSpec.fullpath for Windows
Fix `fullpath` to not assume a `/` path separator. This was discovered when
D133130 failed on Windows. Use `os.path.join()` to fix the issue.
Reviewed By: mib
Differential Revision: https://reviews.llvm.org/D133366
Michael Jones [Fri, 11 Nov 2022 21:50:01 +0000 (13:50 -0800)]
[libc] move fork into threads folder
Fork, as a thread function, should go in the threads folder.
Additionally, it depends on the thread mutex, and it was causing build
issues for targets where we don't support threads.
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D137867
Lang Hames [Fri, 11 Nov 2022 21:34:29 +0000 (13:34 -0800)]
[ORC-RT][MachO] Unlock JDStatesMutex during push-initializers to avoid deadlock.
During __orc_rt_macho_jit_dlopen the ORC runtime will make a request to the JIT
to push any new initializers. Since this call may add new JD-state to the
runtime (and is expected to in general) we need to unlock the JDStatesMutex
during this operation (and similarly when running initializers and atexits, as
these may call trigger push-initializers recursively).
No testcase yet: I haven't been able to reproduce the deadlock when running
llvm-jitlink in in-process mode, and we don't support out-of-process mode in
regression tests yet.
Lang Hames [Fri, 11 Nov 2022 05:32:31 +0000 (21:32 -0800)]
[ORC] Capture JD by value in MachOPlatform::pushInitializersLoop.
The lambda may run after pushInitializersLoop returns.
Tom Stellard [Fri, 11 Nov 2022 23:17:25 +0000 (15:17 -0800)]
docs: add instructions for stand-alone builds of lld
Reviewed By: kwk, MaskRay
Differential Revision: https://reviews.llvm.org/D124405
Mahesh Ravishankar [Fri, 11 Nov 2022 23:09:08 +0000 (23:09 +0000)]
[mlir][Linalg] Avoid using `tensor.cast` by default while folding `fill` with `pad`.
This is unnecessary if the generated operation type already matches
the type of the replaced value. Also use `OpFoldResult` to reduce the
number of cases the casts are needed.
Reviewed By: springerm, hanchung, antiagainst
Differential Revision: https://reviews.llvm.org/D137479
Alina Sbirlea [Fri, 11 Nov 2022 22:57:10 +0000 (14:57 -0800)]
Revert "[Hexagon] Use default attributes for intrinsics"
This reverts commit
8a8983b279dd5e4dceabe1fadbb8980b6adb88f9.
Uncovers existing regalloc issue in Hexagon backend - blocking for Halide
Hexagon users. Reverting to unblock, to be recommitted when underlying issue is resolved.
Reproducer available shortly.
Matt Arsenault [Sun, 23 Oct 2022 19:29:18 +0000 (12:29 -0700)]
llvm-diff: Add failing testcase for issue 58629
Jordan Rupprecht [Fri, 11 Nov 2022 22:47:57 +0000 (14:47 -0800)]
[NFC] Remove unused var Op
Matt Arsenault [Mon, 24 Oct 2022 17:56:18 +0000 (10:56 -0700)]
llvm-reduce: Minor code cleanups
Matt Arsenault [Mon, 24 Oct 2022 23:19:40 +0000 (16:19 -0700)]
llvm-reduce: Use DenseSet
Dave Lee [Fri, 11 Nov 2022 20:18:37 +0000 (12:18 -0800)]
[lldb] Allow flexible importing of in_call_stack
Allow `in_call_stack` to be imported in either of the following ways:
```
command script import path/to/in_call_stack.py
command script import lldb.utils.in_call_stack
```
rdar://
102249295
Differential Revision: https://reviews.llvm.org/D137860
Mingming Liu [Wed, 9 Nov 2022 06:46:42 +0000 (22:46 -0800)]
[AArch64] Select BFI/BFXIL to ORR with shifted operand when one operand is the left or right shift of another operand
Use right shift [1] as an example
- Before, bfxil is generated (https://godbolt.org/z/EfzWMszPn)
- After, orr with right-shifted operand is generated (added test cases in `CodeGen/AArch64/bitfield-insert.ll`)
[1]
```
define i64 @test_orr_not_bfxil_i64(i64 %0) {
%2 = and i64 %0, 1044480 ; 0xff000
%3 = lshr i64 %2, 12
%4 = or i64 %2, %3
ret i64 %4
}
```
Differential Revision: https://reviews.llvm.org/D137689
Mingming Liu [Wed, 9 Nov 2022 06:28:07 +0000 (22:28 -0800)]
[NFC][AArch64]Precommit test cases to show ORR is better when one operand is a shift of the other operand
In `bfi-not-orr` tests, bfi/bfxil are better since they simplifies away two instructions (extracting bits into destination directly)
In `orr-not-bfi` tests, orr is better since both orr and bfm would simplify away one instruction (the shl node), orr has higher throughput and shorter latency than bfm.
Peiming Liu [Fri, 11 Nov 2022 18:51:25 +0000 (18:51 +0000)]
[mlir][sparse] fix crash when calling getTuple on non-sparse tensors.
This enables full sparse convolution codegen in D137298
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D137853
Matt Arsenault [Thu, 20 Oct 2022 21:19:59 +0000 (14:19 -0700)]
llvm-reduce: Report number of new chunks
Mengxuan Cai [Fri, 11 Nov 2022 17:42:45 +0000 (12:42 -0500)]
[LoopFuse] Ensure inner loops are in loop simplified form under new PM
LoopInfo doesn't give all loops in a loop nest, it gives top level loops
only. While isLoopSimplifyForm() only checkes for the outter most loop of a
loop nest. As a result, inner loops that are not in simplied form can
not be simplified with the original code.
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D137672
Sanjay Patel [Fri, 11 Nov 2022 20:26:54 +0000 (15:26 -0500)]
[InstCombine] allow more folds more multi-use selects
The 'and' case showed up in a recent bug report and prevented
more follow-on transforms from happening.
We could handle more patterns (for example, the select arms
simplified, but not to constant values), but this seems
like a safe, conservative enhancement. The backend can
convert select-of-constants to math/logic in many cases
if it is profitable.
There is a lot of overlapping logic for these kinds of patterns
(see SimplifySelectsFeedingBinaryOp() and FoldOpIntoSelect()),
so there may be some opportunity to improve efficiency.
There are also optimization gaps/inconsistency because we do
not call this code for all bin-opcodes (see TODO for ashr test).
Sanjay Patel [Fri, 11 Nov 2022 16:17:07 +0000 (11:17 -0500)]
[InstCombine] add tests for binop with select operand; NFC
Jakub Kuderski [Fri, 11 Nov 2022 20:13:48 +0000 (15:13 -0500)]
[mlir][arith] Add `arith.cmpi` support to WIE
This inludes both LIT tests over IR and runtime checks.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D137846
Daniel Rodríguez Troitiño [Fri, 11 Nov 2022 19:56:46 +0000 (11:56 -0800)]
[objcopy] Fix order of Mach-O LINKEDIT pieces during layout
The exports trie and the chained fixups where in the opposite order, and
function starts happenned before them, instead of after them.
Restore the correct order and rewrite the code to make it easier to move
around in the future if needed by reusing the `Offset` variable and
keeping both the `StartOf...` and the size of each piece together.
This was found out while trying to use the system strip in a binary
already stripped by LLVM and receiving errors around chained fixups when
we enabled those in the linker.
Reviewed By: alexander-shaposhnikov
Differential Revision: https://reviews.llvm.org/D133974
Krzysztof Parzyszek [Tue, 8 Nov 2022 22:57:21 +0000 (14:57 -0800)]
[Hexagon] Place aligned loads closer to users
Vector alignment code was grouping all aligned loads together. In some
cases the groups could become quite large causing a lot of spill to be
generated. This will place the loads closer to where they are used,
reducing the register pressure.