ci/freedreno: Disable flaky a530 for now.

This morning saw at least 3 pipelines fail from a530 not responding and
not coming back after we tried to power cycle, and airlied was having some
similar trouble yesterday.  Until I can figure out what's going wrong
(python script failing to set up serial after retry?  relays worn out?
Power supply failing?), just disable the boards.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13123>

anv/blorp: Force compute blorp on compute-only queues

Reworks:
 * Set BLORP_BATCH_USE_COMPUTE in anv_blorp_batch_init (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

anv/blorp: Add anv_blorp_batch_init, anv_blorp_batch_finish

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

anv/blorp: Select pipeline based on BLORP_BATCH_USE_COMPUTE

Reworks:
 * Let blorp_clear handle DEBUG_BLOCS
 * Old subject was: "Use compute blorp for vkCmdFillBuffer with
   INTEL_DEBUG=blocs"
 * Old subject was: "anv/blorp: Support params.cs_prog_data being set"

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

anv/blorp: Make sure blorp type is supported by the queue

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

anv: Prevent starting a render pass on compute queues

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

anv: Store anv_queue_family type in cmd-pool

v2 (Jason Ekstrand):
 - Use an anv_queue_family pointer

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Support some image/buffer blit operations using compute

Reworks:
 * Use BLORP_BATCH_USE_COMPUTE flag rather than compute param to
   blorp_copy (s-b Jason)
 * Squash "intel/blorp: Set shader_pipeline for compute"
 * Squash "intel/blorp: Add blorp_copy_supports_compute function"
 * Squash "intel: Support compute for image/buffer copy if INTEL_DEBUG=blocs
           is set"
 * Squash "intel/blorp: Support compute for some blit operations"
 * Use nir_image_store (s-b Jason)
 * Use nir_push_if (s-b Jason)
 * Require gfx12 for ccs in blorp_copy_supports_compute (s-b Jason)
 * Add nir_pop_if (s-b Ken)
 * Fix aux_usage check on gfx12 blorp_copy_supports_compute (s-b Ken)
 * Use blorp_set_cs_dims (s-b Jason)
 * Use dim=2d with array=true for nir_image_store (s-b Jason, Francisco)
 * Restructure gen checks in blorp_copy_supports_compute (s-b Ken)
 * Use nir_load_global_invocation_id (s-b Jason)
 * Fix inefficient calculation of store_pos (s-b Jason)
 * Use bounds_if being NULL/non-NULL for nir_pop_if (s-b Jason)
 * discard => bounds (s-b Ken)
 * Re-add ISL_AUX_USAGE_CCS_E in *_supports_compute (s-b Sagar)
 * Skip duplicated in_bounds calculation (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp/blit: Rename wm_prog_key and prog_key to key

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Support compute for slow clears

Reworks:
 * Use BLORP_BATCH_USE_COMPUTE flag rather than compute param to
   blorp_clear (s-b Jason)
 * Use nir_load_global_invocation_id (s-b Jason)
 * Use nir_push_if (s-b Jason)
 * Use nir_image_store (s-b Jason)
 * Require gfx12 for ccs in blorp_clear_supports_compute (s-b Jason)
 * Add nir_pop_if (s-b Ken)
 * Fix aux_usage check on gfx12 blorp_clear_supports_compute (s-b Ken)
 * Use blorp_set_cs_dims (s-b Jason)
 * Simplify rgb-as-red calculation (s-b Jason)
 * Use dim=2d with array=true for nir_image_store (s-b Jason, Francisco)
 * discard => bounds (s-b Ken)
 * Re-add ISL_AUX_USAGE_CCS_E in *_supports_compute (s-b Sagar)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Convert blorp_clear color_write_disable to a bitmask

Reworks:
 * Various cleanups adding BITFIELD_* (s-b Jason)
 * Add /* color_write_disable */ comment (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

blorp/clear: Simplify rbg-as-red channel packing

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

blorp: Set view usage to ISL_SURF_USAGE_STORAGE_BIT for compute

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Use blorp_check_in_bounds for discards

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add blorp_check_in_bounds()

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Change discard terminology to bounds

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add blorp_get_cs_local_y, blorp_set_cs_dims

Based the blorp_params, blorp_get_cs_local_y returns a recommended
local_y size for a compute shader.

blorp_set_cs_dims sets the compute program dims based on a given
local_y size.

Reworks:
 * Add blorp_set_cs_dims (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/gfx7: Change GPGPU Mode to bool

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Emit compute program based on BLORP_BATCH_USE_COMPUTE

Reworks:
 * Don't pack params, just memcpy param struct (s-b Jason)
 * Old subject: "intel/blorp: Emit compute program if
   params.cs_prog_data is set"
 * Various cleanups of push-const size/alignment (s-b Jason)
 * Fix subslice count by moving to devinfo (s-b Ken)
 * Simplify cw.InterfaceDescriptor code (s-b Ken)
 * Drop some comments from i965 (s-b Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

anv,iris,genxml: Use NumberOfBarriers on XeHP

Ref: bspec 55400
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

blorp: Add blorp_alloc_general_state

Reworks:
 * Add crocus

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Split out surface setup from state emission

Render will use blorp_setup_binding_table and blorp_emit_btp, but
compute will only use blorp_setup_binding_table.

Rework:
 * Use blorp_setup_binding_table, blorp_emit_btp (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Split out ps specific sampler state into a separate function

The compute path will use blorp_emit_sampler_state, whereas the render
path will use blorp_emit_sampler_state_ps.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add blorp_compile_cs

Reworks:
 * Don't pack params (s-b Jason)
 * Drop nir_remove_dead_variables (s-b Jason)
 * Fix comment s/render target/destination image/ (s-b Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add subgroup_id input for compute programs

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/compiler: Use INTEL_DEBUG=blorp to dump blorp compute shaders

Make INTEL_DEBUG=blorp dump the blorp compute shaders instead using
the general INTEL_DEBUG=cs which is now reserved for actual compute
programs.

Ref: 05933fb0f7e ("intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add brw_blorp_init_cs_prog_key

Reworks:
 * Split out blorp_init_base_prog_key to share with fs/cs key init (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add shader_pipeline to brw_blorp_base_key

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Add compute support to BLORP_CREATE_NIR_INPUT

Reworks:
 * Set driver_location (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

intel/blorp: Move most of BLORP_CREATE_NIR_INPUT into a function

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>

frontends/va: Fix test_va_api VAAPIDisplayAttribs tests

Set max_display_attribs to 0 instead of 1 to match
va[Query,Get,Set]DisplayAttributes implementations [1].

If max_display_attribs is greater than 0 libva-utils tests check
vaQueryDisplayAttributes() accordingly [2].

[1] https://gitlab.freedesktop.org/mesa/mesa/-/blob/2de348cdb01e45/src/gallium/frontends/va/display.c#L32
[2] https://github.com/intel/libva-utils/blob/master/test/test_va_api_display_attribs.cpp#L90

Signed-off-by: Ed Baker <edward.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12941>

virgl/drm: explicit context initialization

If the host supports explicit context initialization, try it.
If no capabilitiies associated with virgl are present, return
an error.

Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Tested-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7712>

virgl/drm: query for context init ioctl and supported capset ids

Just add the params to the existing lists.

Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Tested-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7712>

drm-uapi: virtgpu_drm.h: context init feature

This change allows creating contexts of depending on set of
context parameters.  The meaning of each of the parameters
is listed below:

1) VIRTGPU_CONTEXT_PARAM_CAPSET_ID

This determines the type of a context based on the capability set
ID.  For example, the current capsets:

VIRTIO_GPU_CAPSET_VIRGL
VIRTIO_GPU_CAPSET_VIRGL2

define a Gallium, TGSI based "virgl" context.  We only need 1 capset
ID per context type, though virgl has two due a bug that has since
been fixed.

The use case is the "gfxstream" rendering library and "venus"
renderer.

gfxstream doesn't do Gallium/TGSI translation and mostly relies on
auto-generated API streaming.  Certain users prefer gfxstream over
virgl for GLES on GLES emulation.  {gfxstream vk}/{venus} are also
required for Vulkan emulation.

The goal is for guest userspace to choose the optimal context type
depending on the situation/hardware.

2) VIRTGPU_CONTEXT_PARAM_NUM_RINGS

This tells the number of independent command rings that the context
will use.  This value may be zero and is inferred to be zero if
VIRTGPU_CONTEXT_PARAM_NUM_RINGS is not passed in.  This is backwards
compatibility for virgl, which has one big giant command ring for all
commands.

The maxiumum number of rings is 32.  In practice, multi-queue or
multi-ring submission is used for powerful dGPUs and virtio-gpu
may not be the best option in that case (see PCI passthrough or
rendernode forwarding).

3) VIRTGPU_CONTEXT_PARAM_POLL_RING_IDX_MASK

This is a mask of ring indices for which the DRM fd is pollable.
For example, if VIRTGPU_CONTEXT_PARAM_NUM_RINGS is 2, then the mask
may be:

[ring idx]  |  [1 << ring_idx] | final mask
-------------------------------------------
    0              1                1
    1              2                3

The "Sommelier" guest Wayland proxy uses this to poll for events
from the host compositor.

Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Tested-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7712>

radv: plug leaks in radv_device_init_accel_struct_build_state

Fixes: 0dad88b4694 ("radv: Implement device-side BVH building.")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13110>

panvk/ci: Enable blend tests

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

panvk: Lower blend operations when needed

The gallium driver makes use of blend shaders, but panvk takes a
slightly different approach. Vulkan drivers are passed the blend
operation at pipeline creation time, which means they know it when
compiling the fragment shader and can lower the blend operation
directly in the fragment shader itself. Doing that simplifies the
pipeline creation since we don't have to deal with blend shaders
anymore.

This might come at a cost for translation layers like Zink though,
since it requires re-compiling the fragment shader every time the
blend operation changes, which we do anyway, since we don't have
a pipeline cache yet. Let's keep things simple for now and revise
things if/when we end up having performance issues.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

panvk: Fill the blend constants sysval

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

pan/blend: Allow passing blend constants through a sysval

This is needed to allow lowering blend operations in fragment shaders
when the blend operation uses dynamic blend constants.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

nir/lower_blend: Shrink blended result if needed

Make sure the new and old sources have the same number of components,
otherwise the NIR validation pass complains.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

nir/lower_blend: Make sure we're not passed scaled formats

SCALED formats are interpreted as floats, but not in the usual [0, 1]
or [-1, 1] range, meaning that the blend lowering logic can't directly
apply to those. Assert that the format being passed is not a scaled
format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

nir/lower_blend: Don't lower RTs whose format is set to NONE

The caller doesn't necessarily want to lower blend operations on all
render targets since some of them might be supported natively (panvk
will be in that case). Let's just skip RTs that have a format set to
PIPE_FORMAT_NONE to allow that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

nir/lower_blend: Pad src to a 4-component vector

nir_ssa_for_src() is not supposed to pad the src vector if
dst->num_components > src->num_components. Let's pad things explicitly
with nir_pad_vector().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

nir: Make sure src->num_components < dst->num_components in nir_ssa_for_src()

The NIR validation complains if the swizzle accesses a component that's
not present in the source.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>

panfrost: Add ASTC 3D texture format entries

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>

panfrost: Encode 3D ASTC dimensions

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>

panfrost: Use ASTC 2D enums

Rather than manipulating the bits to do the mapping, use a dead simple
switch() with the enum definition.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>

panfrost: Assert ASTC/AFBC are not used on v4

These are not introduced until v5. The required enums do not exist on
v4. Assert this is so.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>

panfrost: Add ASTC stretch factor enums

ASTC textures all use a common ASTC format, with the ASTC block
dimension configured with auxiliary bits at the bottom of the payload
pointer. Add the corresponding enum for ASTC 2D and 3D.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12814>

drirc: Set vs_position_always_precise for Assault Android Cactus

A couple of tesselation evaluation shaders lack some precise marks
on its outputs which can lead to different results after optimizations.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5376
Fixes: 09705747d72 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13027>

driconf, glsl: Add a vs_position_always_precise option

This is basically the same workaround as in 9b577f2a88 (driconf, glsl: Add a
vs_position_always_invariant option) commit but for tesselation evaluation
shaders. Some applications do not mark outputs as precise in tesselation
evaluation shaders which can lead to different results in case some
optimizations were applied.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Fixes: 09705747d72 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13027>

panfrost: Move genxml related files to a subdir

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>

panfrost: Split command stream descriptor definitions per-gen

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>

panfrost: Add a common genxml file so we can share a few definitions

Start with the enums that were manually redefined in
pan_{texture,format}.h and the blend equation descriptors.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>

radv: fix selecting the hash when RADV_FORCE_VRS is enabled

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>

radv: fix adjusting the frag coord when RADV_FORCE_VRS is enabled

force_vrs was always RADV_FORCE_VRS_NONE at that point and the
hw workaround was never applied.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>

radv: remove the LLVM stat about the number of private VGPRs

This doesn't seem really useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12999>

aco/ra: don't rewrite affinities for phi operands after register assignment

The effect of doing so is random and not meaningful.

Totals from 52 (0.03% of 150170) affected shaders: (GFX10.3)
CodeSize: 538768 -> 538784 (+0.00%); split: -0.04%, +0.04%
Instrs: 100661 -> 100707 (+0.05%); split: -0.01%, +0.06%
Latency: 1205950 -> 1205768 (-0.02%); split: -0.07%, +0.05%
InvThroughput: 200106 -> 200040 (-0.03%); split: -0.31%, +0.28%
Copies: 5717 -> 5754 (+0.65%); split: -0.17%, +0.82%
Branches: 3153 -> 3162 (+0.29%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: create nested affinities for loop header phis

Totals from 875 (0.58% of 150170) affected shaders: (GFX10.3)
CodeSize: 6084528 -> 6066628 (-0.29%); split: -0.32%, +0.02%
Instrs: 1136497 -> 1133565 (-0.26%); split: -0.28%, +0.02%
Latency: 23355051 -> 22952592 (-1.72%); split: -1.83%, +0.10%
InvThroughput: 13028151 -> 12859628 (-1.29%); split: -1.38%, +0.09%
Copies: 85673 -> 82790 (-3.37%); split: -3.62%, +0.26%
Branches: 25049 -> 25098 (+0.20%); split: -0.08%, +0.28%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: create affinities between nested phis

Totals from 17143 (11.42% of 150170) affected shaders: (GFX10.3)
VGPRs: 1138112 -> 1138440 (+0.03%); split: -0.00%, +0.03%
CodeSize: 131235532 -> 131147080 (-0.07%); split: -0.14%, +0.07%
Instrs: 24848044 -> 24775419 (-0.29%); split: -0.32%, +0.02%
Latency: 599031816 -> 596005601 (-0.51%); split: -0.52%, +0.01%
InvThroughput: 152059329 -> 151054105 (-0.66%); split: -0.66%, +0.00%
VClause: 410951 -> 410958 (+0.00%); split: -0.01%, +0.01%
Copies: 1696885 -> 1621908 (-4.42%); split: -4.64%, +0.22%
Branches: 846710 -> 851052 (+0.51%); split: -0.29%, +0.80%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: don't set affinities for ssa-repair phis

These have no effect anymore.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: for phis try to find an operand-matching register earlier

Totals from 3557 (2.37% of 150170) affected shaders: (GFX10.3)
VGPRs: 257976 -> 257984 (+0.00%)
CodeSize: 34296232 -> 34270552 (-0.07%); split: -0.09%, +0.01%
Instrs: 6512289 -> 6506900 (-0.08%); split: -0.10%, +0.01%
Latency: 136376181 -> 136262553 (-0.08%); split: -0.10%, +0.02%
InvThroughput: 33042816 -> 32992849 (-0.15%); split: -0.18%, +0.03%
VClause: 104687 -> 104686 (-0.00%)
SClause: 238657 -> 238663 (+0.00%); split: -0.00%, +0.00%
Copies: 477690 -> 471058 (-1.39%); split: -1.52%, +0.13%
Branches: 223058 -> 224326 (+0.57%); split: -0.02%, +0.59%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: try more aggressive to assign phi defs the same register

Totals from 4158 (2.77% of 150170) affected shaders: (GFX10.3)
VGPRs: 312008 -> 312000 (-0.00%)
CodeSize: 42902064 -> 42892200 (-0.02%); split: -0.06%, +0.04%
Instrs: 8086443 -> 8084532 (-0.02%); split: -0.07%, +0.05%
Latency: 138551153 -> 138215222 (-0.24%); split: -0.28%, +0.03%
InvThroughput: 39676773 -> 39570850 (-0.27%); split: -0.29%, +0.02%
SClause: 306299 -> 306284 (-0.00%); split: -0.01%, +0.00%
Copies: 552481 -> 553353 (+0.16%); split: -0.75%, +0.91%
Branches: 284381 -> 282409 (-0.69%); split: -0.74%, +0.04%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: split register assignment for phis into separate function

No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: remove some redundant code

No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: refactor affinities into assignment struct

This lets us get rid of an unordered_map<>.

No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

aco/ra: fix intersects()

The previous implementation failed when a contained b.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>

radv: fix missing features for BDA

Only the KHR one is filled by the common code.

Fixes: ec2007d47ed ("radv: Use the shared now-in-core feature/prop extension helper functions.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13035>

compiler/clc: grab opencl-c.h from the system path by default

By default we use the header installed opencl-c.h header. But in the
case Mesa is compiled for microsoft clon12 we keep the injected file.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>

compiler/clc: Clean ups

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>

Move a bunch of the CLC stuff from src/microsoft to common code

The D3D12-specific stuff isn't useful to have in common code but all the
stuff to invoke clang really should be common.

v2: Rebase (Lionel)

v3: Define a new clc_libclc_new_dxil() entrypoint to create a clc
    context with DXIL nir_options (Jesse)

v4: Fixup meson build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>

meson: extract libversion checks from clc & clover

The src/microsoft/clc/meson.build was assuming to be run only on
Windows. That's about to change.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>

microsoft/clc: fix compiler warning on uninitiailzed variable use

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>

microsoft/clc: drop MSVC specific function

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>

virgl: Flush context before waiting on fences

The logic behind this change is intuitive: if we are waiting for
something, we should probably flush all pending rendering so that it
starts executing in the meantime. This prevents the GPU from sitting
idle for long periods of time while we are also blocked in the app.

With the gun3d trace:
Before: 79 fps After: 215 fps

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13096>

util: fix sign comparison

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13074>

st/texture: Fall back to single-slice uploads in st_CompressedTexSubImage

Currently, if we ever fail to create a re-interpreted uncompressed view
of the resource, we fall back to a SW path.  On some Intel hardware,
this happens whenever LOD > 0.  Instead, we should fall back to
attempting to upload one slice at a time and only fall back to SW as a
last resort.

v2 [by Ken]: Fix buf_offset calculation and loop over layers.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11737>

st/texture: Dedent surface setup in CompressedTexSubImage

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11737>

loader/dri3: fix swap out of order when changing swap interval

This fixes SPECVIEWPERF13 creo test case hang:
  1. Client: send present pixmap request (serial=1) when swap_interval==1
     and increase send_sbc=1
  2. Server: pend the request before vblank arrives
  3. Client: set swap_interval=0 (so set XCB_PRESENT_OPTION_ASYNC),
     send another present pixmap request (serial=2), increase send_sbc=2
  4. Server: handle the async request immediately and send complete event
     (serial=2)
  5. Client: handle the event and set recv_sbc=event->serial=2
  6. Server: vblank arrives so handle pending request and send complete
     event (serial=1)
  7. Client: handle the event and set recv_sbc=event->serial=1
  8. Client: someone call loader_dri3_swapbuffer_barrier() and waiting
     on recv_sbc==send_sbc, but no one will set recv_sbc=2 again

So basically it's caused by swap happens out of order. This commit
fixes the problem by waiting on the pending sync swaps all done when
switching to async mode, so move 6&7 before 3.

Attach the xtrace when problem happens:

  005:<:003e: 72: Present-Request(148,1): Pixmap window=0x03000002 pixmap=0x0300000b serial=1 valid=0x00000000 update=0x00000000 x_off=0 y_off=0 target_crtc=0x00000000 wait_fence=0x00000000 idle_fence=0x0300000c options=0 target_msc=4294967296 divisor=0 remainder=0 notifies=;
  ...
  005:<:0041: 72: Present-Request(148,1): Pixmap window=0x03000002 pixmap=0x03000011 serial=2 valid=0x00000000 update=0x00000000 x_off=0 y_off=0 target_crtc=0x00000000 wait_fence=0x00000000 idle_fence=0x03000012 options=Async target_msc=0 divisor=0 remainder=0 notifies=;
  005:>:0041: Event Generic(35) Present(148) IdleNotify(2) event=0x03000006 window=0x03000002 serial=2 pixmap=0x03000011 idle_fence=0x03000012
  005:>:0041: Event Generic(35) Present(148) CompleteNotify(1) kind=Pixmap(0x00) mode=Copy(0x00) event=0x03000006 window=0x03000002 serial=2 ust=7505462213117739011 msc=3565046193979392
  005:>:0041: Event Generic(35) Present(148) IdleNotify(2) event=0x03000006 window=0x03000002 serial=1 pixmap=0x0300000b idle_fence=0x0300000c
  005:>:0041: Event Generic(35) Present(148) CompleteNotify(1) kind=Pixmap(0x00) mode=Copy(0x00) event=0x03000006 window=0x03000002 serial=1 ust=7505533793042694147 msc=3565050488946688

Cc: mesa-stable
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13019>

venus: keep layouts of descriptor sets alive

We might reorder vkCmdBindDescriptorSets after
vkDestroyDescriptorSetLayout due to batching, which is likely invalid.
Keep the layouts alive with the sets to defer
vkDestroyDescriptorSetLayout.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>

venus: add vn_refcount to vn_descriptor_set_layout

The reference count does not go beyond 1 yet.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>

venus: add a helper to destroy vn_descriptor_set

Add vn_descriptor_set_destroy.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>

venus: convert bo and shmem to use vn_refcount

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>

venus: add vn_refcount

Memory ordering is hard.  Add vn_refcount to take care of the details.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>

v3dv: Use VK_DEFINE_*HANDLE_CASTS instead of rolling our own

The core ones have some nifty stuff like asserts that it's a valid
vk_object_base and has the right type.  We don't have real type safety
with Vulkan handles but this is as close as we can get.  The core ones
also track when we've started handing out handles for logging purposes
which we want.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13101>

vulkan/shader_module: Fix the lifetime of temporary shader modules

The vk_shader_module_handle_from_nir() macro was constructing a
temporary vk_shader_module and passing it through
vk_shader_module_to_handle().  Since this is a function and not a macro,
it means that the lifetime of the temporary vk_shader_module will end
once the to_handle() function is called.  Technically, this is a
use-after-free.  I really don't know why no one has been bitten by this
yet....

Fixes: a41e98ddcae0 "vk/util: add a util macro for initializing stack..."
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13101>

isaspec: De-duplicate bitset encoding

bitset encoding tends to have a lot of duplication, for ex. many
instructions with the same encoding modulo the fixed pattern.  Now that
encode_bitset is split out into it's own template, so that we can
capture the result, use a hash table to de-duplicate the bitset encoding
into "snippet" functions so that bitset cases with identical encoding
can re-use the same generated code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>

isaspec: Split encode_bitset() into it's own template

In the next patch, we are going to want to be able to capture the result
of rendering the template as a py variable, which I don't think you can
do otherwise with a <%def>.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>

isaspec: Fix comment

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>

isaspec: Remove unused leftovers

These were never used, leftovers from an earlier iteration of isaspec
which used an RPN based thing for expressions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>

docs: update calendar and link releases notes for 21.2.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13109>

docs" Add SHA256 sum for mesa 21.2.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13109>

docs: add release notes for 21.2.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13109>

venus: copy VkPhysicalDeviceImageDrmFormatModifierInfoEXT

We should not drop VkPhysicalDeviceImageDrmFormatModifierInfoEXT when it
is provided.

Fixes dEQP-VK.drm_format_modifiers.export_import.*.

Fixes: efa185ed5cd ("venus: rework external memory capability queries")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13094>

gallivm: use pmulhrsw to make aos sampling more accurate.

This uses pmulhrsw avx2 and ssse3 variants. It fixes the
precision of texture filtering calculations.

However it does leave these paths inaccurate on platforms
that don't support it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13075>

radv: workaround incorrect image format with World War Z

The image format in a FSR-related shader is incorrect.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5407
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13084>

intel/fs: Emit URB fences when we have LSC

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>

intel/fs: Add the URB fence message

When they re-arranged all the dataport stuff and added the LSC, doing
URB fencing through the dataport no longer makes sense.  Instead, there
is now a fence message on the URB shared function.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>

intel/fs: Ignore SLM fences if shared is unused

Found this nugget while looking at the ACO driver.  It seems sensible to
avoid SLM fences if there is no SLM.  This also makes the check depend
on SLM usage rather than just shader stage which will be useful if we
ever implement task/mesh because task shaders also have SLM.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>

intel/fs: Rework fence handling in brw_fs_nir.cpp

Start off making everything look like LSC where we have three types of
fences: TGM, UGM, and SLM.  Then, emit the actual code in a generation-
aware way.  There are three HW generation cases we care about:
XeHP+ (LSC), ICL-TGL, and IVB-SKL.  Even though it looks like there's a
lot to deduplicate, it only increases the number of ubld.emit() calls
from 5 to 7 and entirely gets rid of the SFID juggling and other
weirdness we've introduced along the way to make those cases "general".
While we're here, also clean up the code for stalling after fences and
clearly document every case where we insert a stall.

There are only three known functional changes from this commit:

 1. We now avoid the render cache fence on IVB if we don't need image
    barriers.

 2. On ICL+, we no longer unconditionally stall on barriers.  We still
    stall if we have more than one to help tie them together but
    independent barriers are independent.  Barrier instructions will
    still operate in write-commit mode and still be scheduling barriers
    but won't necessarily stall.

 3. We now assert-fail for URB fences on LSC platforms.  We'll be adding
    in the new URB fence message for those platforms in a follow-on
    commit.

It is a big enough refactor, however, that other minor changes may be
present.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>