agx: Validate predecessor information

Including the new loop header? flag.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Add loop header? flag

This is useful for deciding whether we need to fix up phis in RA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Recollect stored vectors at their use

This is Timur's cheesy solution to split-hell.shader_test. Seems to work ok
here.

Before: 94 inst, 588 bytes, 165 halfregs, 1 threads, 0 loops, 0:0 spills:fills
After: 63 inst, 454 bytes, 129 halfregs, 1 threads, 0 loops, 0:0 spills:fills

On Android GLES3.1 shader-db, a few shaders are helped a lot:

   total instructions in shared programs: 1781706 -> 1781473 (-0.01%)
   instructions in affected programs: 4284 -> 4051 (-5.44%)
   helped: 16
   HURT: 2
   Instructions are helped.

   total bytes in shared programs: 12197854 -> 12196640 (<.01%)
   bytes in affected programs: 29526 -> 28312 (-4.11%)
   helped: 20
   HURT: 2
   Bytes are helped.

   total halfregs in shared programs: 489007 -> 488755 (-0.05%)
   halfregs in affected programs: 945 -> 693 (-26.67%)
   helped: 7
   HURT: 0
   Halfregs are helped.

   total threads in shared programs: 18873216 -> 18875008 (<.01%)
   threads in affected programs: 5376 -> 7168 (33.33%)
   helped: 7
   HURT: 0
   Threads are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Extract coordinate register size calculation

It will be used for image writes too, not just reads.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

asahi: Pass through surface sample count

This makes PIPE_CAP_SURFACE_SAMPLE_COUNT do something, namely, explode
with lots of fireworks. We'll have to figure out what's wrong, but at
least now we aren't just not trying at all. Should not break anything as
long as PIPE_CAP_SURFACE_SAMPLE_COUNT is not flipped on.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

asahi: Disable PIPE_CAP_SURFACE_SAMPLE_COUNT

This never worked, disable it.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

asahi: Revert "Advertise ARB_texture_barrier"

This reverts commit 9e67d3f23780a818b9fc764105f39c6d595c6530.

We do not, in fact, implement texture barriers. Texture barriers are
supposed to allow non-overlapping rendering feedback loops. We cannot
support that at non-tile boundaries when texture compression is enabled
without some kind of downgrade path or other special handling.

Fixes Emacs corruption on X/Glamor.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Fix discards

Switch our frontends from generating sample_mask_agx to discard_agx, and
switching from legalizing sample_mask_agx to lowering discard_agx to
sample_mask_agx. This is a much easier problem and is done here in a way that is
simple (and inefficient) but obviously correct.

This should fix corruption in Darwinia.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Update explanation of sample_mask behaviour

We discovered today that these (probably) trigger depth/stencil testing, which
has significant implications for the correct/performant use.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

nir: Add discard_agx intrinsic

sample_mask_agx corresponds directly to the hardware's 2-source instruction, but
it's hard to use correctly and even harder to legalize after the fact, since
it's responsible for not only discard but also late depth/stencil testing. For
our various high-level lowering passes, it's easier to use a one-source discard
(where we don't have to worry about sample masks), which the compiler will
internally lower to the two-source instruction. Introduce such an instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

radv: adjust alignment of the preprocess buffer with DGC

The preprocess buffer is the buffer used to generate the cmdbuf. It
was aligned to 256 bytes but the correct alignment is actually
ac_gpu_info::ib_alignment.

Otherwise, if a DGC IB is executed like a IB1, this hits an assertion
in radv_amdgpu_cs_submit() because the alignment is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23764>

radv: only dirty the active push constant stages with DGC

It's unnecessary to dirty all stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23761>

radv: only dirty the index type when necessary with DGC

This should only be needed for non-indexed draws and it's already
dirty if the DGC binds an index buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23761>

radv/amdgpu: dump all cs with RADV_DEBUG=noibs

It was only dumping the oldest.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23646>

radv/amdgpu: fix dumping cs with RADV_DEBUG=noibs

The ib_buffer is NULL now.

Fixes: 50e6b16855d ("radv/amdgpu: Use fallback submit for queues that can't use IBs.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23646>

pvr: Correctly read dynamic state setup during blend constant setup

Somewhat counterintuitively, dynamic_state.set contains the bits that
have been loaded from static state, i.e. those that are _not_ dynamic.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23590>

radeonsi: disable H264HIGH10 profile

Issue: H.264 high 10 profile is currently not supported, but is shown as
supported in vainfo.

Reason: Kernel reported capabilities for video encoder/decode doesn't
consider the actual profile (only using reduced profile).

Solution: Use kernel reported capabilities only for basic H.264/HEVC
profiles. Other profiles (e.g. 10 bits) should be checked based on HW.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9242

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23824>

radv: reserve more space in CS for SQTT

Otherwise, it can hit an assertion.

Fixes: 7893040f807 ("radv: Add stricter space checks.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23826>

aco: Drop NIR parallel copy handling

Backends never see these instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23831>

aco: Remove unneeded stage related info fields.

Cleanup of various fields with redundant information.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

aco: Use aco_shader_info::hw_stage instead of guessing.

With this change, ACO is going to rely on the caller to set
the HW stage and will no longer guess it from the input shaders.

This will help enable compiling merged shaders separately,
but that will need further changes in instruction selection.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

radv: Set aco_shader_info::hw_stage

ACO will rely on this field instead of guessing
the stage internally.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

radeonsi: Set aco_shader_info::hw_stage

ACO will rely on this field instead of guessing
the stage internally.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

aco: Add hw_stage field to aco_shader_info.

Unused in this commit, but this is going to replace the shader
stage selection inside ACO after the drivers set it correctly.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

aco: Use ac_hw_stage instead of aco-specific HWStage.

The new ac_hw_stage is going to be used by drivers as well.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

ac: Add ac_hw_stage enum.

This is going to be shared between RADV, RadeonSI and ACO.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

treewide: spelling fixes

Debian's lintian tool flagged some spelling issues:
assumtion -> assumption
unkown -> unknown
memeber -> member
sucess -> success
perfomance -> performance

Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23618>

anv: fix utrace batch allocation

The introduction of a workaround adding lots of MI_NOOPs broke our
computation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b9aa66d5d0 ("anv: disable preemption for 3DPRIMITIVE during streamout")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23792>

freedreno/decode: Correctly handle chip_id

gpu_id is not decodable from chip_id in general case,
so we should use chip_id to search for fd_dev_info and get
GPU generation from that.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

freedreno,ir3: Don't call fd_dev_64b more than necessary

fd_dev_64b calls fd_dev_gen which after the last commit calls
fd_dev_info that may scan through all hw definitions.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

freedreno: Decouple GPU gen from gpu_id/chip_id

gpu_id is obsolete, chip_id doesn't encode the GPU generation.
Thus we have to manually specify the GPU gen instead of inferring it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

freedreno/perfcntrs: Link with libfreedreno_common

Header from freedreno/common is used without linking with its
implementation. It worked before because all called functions
were header only, which would change soon.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

ci: Upref virglrenderer

Update expectation too.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23768>

virgl/ci: Drop duplicate runs

CTS GL 3.2 includes all the tests of previous versions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23768>

vulkan: Migrate shader module hash to BLAKE3.

Shaders are the largest thing we hash now, so they benefit from a faster
hash.

Change the field name from `sha1` to `hash` to avoid tying the definition
to a particular algorithm. This doubles down as a precaution against
callers still assuming a 20-byte hash (in which case the compilation will
error out).

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22571>

util/blake3: Add blake3_hash typedef.

This is more ergonomic than unsigned char hash[BLAKE3_OUT_LEN].

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22571>

Revert "egl: return correct error for EGL_KHR_image_pixmap"

This reverts commit 5db031bf3ea3e37983f3ab17f2b550e1949d95a9.

It crashes X after logging in on Ubuntu 20.04.

Fixes: 5db031bf3ea3e3 - egl: return correct error for EGL_KHR_image_pixmap

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23740>

r600/sfn: Don't clear clear group flag on vec4 that comes from TEX or FETCH

If we consider clearing the group flag of a vec4 register that is used as
source for some instruction we have to take into account that the parent
of the register element may also be part of a group in the parent instruction.
In this case we must not clear the group flag.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9118

Fixes:  f3415cb26a (r600/sfn: copy propagate register load chains)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23813>

anv/video: fix to set U/V offset correctly.

Fixes: 98c58a16ef1a ("anv: add initial video decode support for h264.")

Closes: mesa/mesa#9227

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23819>

glsl: call nir_opt_find_array_copies() when linking

shader-db results IRIS (BDW):

total instructions in shared programs: 17883388 -> 17859658 (-0.13%)
instructions in affected programs: 48100 -> 24370 (-49.33%)
helped: 6
HURT: 0
helped stats (abs) min: 1450 max: 7028 x̄: 3955.00 x̃: 3387
helped stats (rel) min: 40.31% max: 51.92% x̄: 47.07% x̃: 48.96%
95% mean confidence interval for instructions value: -6613.28 -1296.72
95% mean confidence interval for instructions %-change: -52.73% -41.40%
Instructions are helped.

total cycles in shared programs: 866961809 -> 863521521 (-0.40%)
cycles in affected programs: 9179396 -> 5739108 (-37.48%)
helped: 6
HURT: 0
helped stats (abs) min: 252584 max: 972430 x̄: 573381.33 x̃: 495130
helped stats (rel) min: 21.80% max: 48.65% x̄: 35.01% x̃: 34.58%
95% mean confidence interval for cycles value: -917157.00 -229605.67
95% mean confidence interval for cycles %-change: -47.61% -22.40%
Cycles are helped.

total spills in shared programs: 20417 -> 15521 (-23.98%)
spills in affected programs: 6966 -> 2070 (-70.28%)
helped: 6
HURT: 0

total fills in shared programs: 25151 -> 21005 (-16.48%)
fills in affected programs: 4374 -> 228 (-94.79%)
helped: 6
HURT: 0

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9055
Fixes: d75a36a9eeb1 ("glsl: remove do_copy_propagation_elements() optimisation pass")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23737>

nir/load_libclc: run some opt passes for everybody

Cuts down serialized size from 2850288 to 1377780 bytes.

Reduces clinfo with Rusticl time by 40% for debug builds.

(Old data, but the point stands)

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15996>

rusticl/device: create helper context before loading libclc

Some drivers (llvmpipe) postpone some screen initialization until the
first context is created.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15996>

venus: Fix detection of push descriptor set

- Fix null deref. VkPipelineLayoutCreateInfo::pSetLayouts is allowed to
  contain VK_NULL_HANDLE.
- The loop 'break' was misplaced.

Fixes crash in
dEQP-VK.pipeline.pipeline_library.graphics_library.fast.0_00_11_11 after
VK_EXT_graphics_pipeline_library is enabled in a later patch.

Fixes: 91966f2eff1 ("venus: extend lifetime of push descriptor set layout")
Signed-off-by: Lina Versace <linyaa@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23810>

nir/opt_if: Use block_ends_in_jump

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23782>

nir: Remove integer and 64-bit modifiers

Now that Intel and R600 both do their own modifier propagation, the only
backends that still lower modifiers in NIR are:

* nir-to-tgsi
* lima
* etnaviv
* a2xx

The latter 3 backends do not support integers, and certainly do not support
fp64. So they don't use these.

TGSI in theory supports integer negate modifiers but NTT doesn't use them, so
they're unused there too.

Since they're unused, we remove NIR support for integer and 64-bit modifiers,
leaving only 16/32-bit float modifiers. This will reduce the scope needed for a
replacement to NIR modifiers, being pursued in !23089.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23782>

venus: Advertise 1.3 in ICD file

It was still advertising 1.2.

Signed-off-by: Lina Versace <linyaa@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23808>

venus: suballocate feedback slot with feedback buffer alignment

Venus sync feedback design relies on concurrent host device resource
access. To avoid device flush overwriting host writes, we must
suballocate the slots with a minimum size of the buffer alignment.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23633>

docs: update calendar for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

docs/relnotes: add sha256sum for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

docs: add release notes for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

anv: align buffers to a cache line

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9217
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23794>

r300: add partial CMP support on R5xx

VE_COND_MUX_GTE4 is a nice match for the TGSI CMP opcode, however
there is a big limitation due to the general shortcoming of the
vertex shader engine that any instruction can read only two different
temporary registers. So we still have to lower in some cases.

Shader-db RV530:
total instructions in shared programs: 130872 -> 130333 (-0.41%)
instructions in affected programs: 29854 -> 29315 (-1.81%)
helped: 294
HURT: 83
total temps in shared programs: 16747 -> 16775 (0.17%)
temps in affected programs: 407 -> 435 (6.88%)
helped: 10
HURT: 38

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23691>

radv: pre-init surface info

this is costly to do at render time, so avoid it when possible

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23770>

ci/etnaviv: update ci expectation

I have been running ci stress tests during the last few days
and nights and this is what I needed to get a pass rate > 80%.
There are still many flakes but I think this is a good starting
point to make better use of the ci.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23797>

Revert "amd/ci: temporarily disable some manual jobs that take a long time to run"

This reverts commit 4031ed5c8a0bbda910f22aec5ee3263b8137936a.

Signed-off-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23798>

rusticl: stop linking with libgalliumvl

it's not needed.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23778>

rusticl: specify which symbols to export

Drops release binary size from 31MB to 29MB

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23778>

rusticl: add ld_args_gc_sections

This drops release file size from 33MB to 31MB on my system.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23778>

meson: Guard the glsl tests that only working when OpenGL ES2 is enabled

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

mapi: Fixes non-constant-expression cannot be narrowed from type 'unsigned long' to 'unsigned int' in initializer list with clang

error is:
../src/mapi/glapi/tests/check_table.cpp:563:19: error: non-constant-expression cannot be narrowed from type 'unsigned long' to 'unsigned int' in initializer list [-Wc++11-narrowing]
   { "glNewList", _O(NewList) },

This is just a test and only with clang, and can be disabled by compiler option, so there is no need to back ported

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

meson: Use consistence disabled/enabled comment for shared-glapi option

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

mapi: Fixes check_table.cpp for DrawArraysInstancedARB and DrawElementsInstancedARB

The compile error when compiled with "-Dglx=xlib -D shared-glapi=disabled":
check_table.cpp:1133:37: error: ‘struct _glapi_table’ has no member named ‘DrawArraysInstancedARB’; did you mean ‘DrawArraysInstanced’?
 1133 |    { "glDrawArraysInstancedARB", _O(DrawArraysInstancedARB) },

Fixes: 5679ef99b82 ("glapi: remove EXT and ARB suffixes from Draw functions")

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

rusticl: experimental support for cl_khr_fp16

Hidden behind `RUSTICL_ENABLE=fp16` for now as the OpenCL CTS doesn't have
enough fp16 tests at the moment. There has been a lot of work on it though,
so hopefully we can enable and verify it soon.

Additionally libclc also misses a bunch of fp16 functionality, so most of
the tests would also just crash.

However this flag is useful for development as it already wires up most of
the code needed.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23788>

rusticl/device: rename doubles to fp64 and long to int64

They are obviously the better names.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23788>

ci/panfrost: switch panfrost-g52-piglit-gles2 from X to XWayland

Runtime reduced approx. by 3 minutes (~ 11 to 8 minutes).

 - Add spec@ext_image_dma_buf_import@ext_image_dma_buf_import-transcode-nv12-as-r8-gr88 crash
 - drop useless `.piglit-test` extend

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23785>

zink/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

radeonsi/get: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

r600/pipe: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

iris/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

crocus/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

sofpipe/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

llvmpipe/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

gallium: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

radeonsi: clean up #includes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: declare compiler[] and nir_options as pointers to reduce #includes

so that we don't have to include the structure definitions.
(ac_llvm_compiler includes LLVM, and nir_options includes NIR)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: clean up query functions, make them static, remove forward decls

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for compute by buffering reg writes

This is the compute portion of the work. It uses a separate buffer
for compute SH registers in si_context.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for gfx by buffering reg writes

Instead of writing SH registers into the command buffer, push them into
an array in si_context. Before a draw, take all buffered register writes
and create a single SET_SH_REG_PAIRS_PACKED packet for them.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: reorder compute code to prepare for packed SET_SH_REG packets

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: enable register shadowing by default

required by SET_SH_REG_PAIRS_PACKED*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: fix GLCTS with register shadowing by keeping the CS preamble

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: remove uses_reg_shadowing parameter from si_init_gfx_preamble_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: remove radeon_winsys::cs_set_preamble

It only does radeon_emit_array and it's not possible to do anything better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: use si_pm4_create_sized for the shadowing preamble

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: don't do BREAK_BATCH for context regs with only 1 context per batch

because it has no effect

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: keep pipeline statistics disabled when they are not used

so that we don't always disable/enable pipeline stats around blits
when there are no pipeline stat queries

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: determine si_pm4_state::reg_va_low_idx automatically

The existing code doesn't work with the packed SET packets, so si_pm4_state
needs to find reg_va_low_idx after the whole packet is built.

Remove si_pm4_set_reg_va and do the same thing for SET_SH_REG.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: use SET_*_REG_PAIRS_PACKED packets for pm4 states

It can generate all PACKED packets, but only SET_CONTEXT_REG_PAIRS_PACKED
is generated because register shadowing is required by
SET_SH_REG_PAIRS_PACKED*.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: eliminate redundant TCS user data and RSRC2 register changes

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: move the only tcs_out_lds_offsets field to vs_state_bits

This removes 1 user data SGPR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: replace tcs_out_lds_layout with nearly identical tes_offchip_addr

tcs_out_lds_layout is basically renamed to tes_offchip_addr in TCS, using
the same variable as TES and also using the same bit layout. The only
difference in the bit layout was that TCS had to mask out the low bits,
which this also removes.

The enums are renamed to *_SGPR_TCS_OFFCHIP_ADDR so as not to conflict
with *_SGPR_TES_OFFCHIP_ADDR, which are in different user data SGPRs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: move TCS.gl_PatchVerticesIn into the tcs_offchip_layout SGPR

we'll be able to remove 1 TCS user data SGPR thanks to this

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

zink/ci: remove 3 tests from the fails list

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

amd/ci: temporarily disable some manual jobs that take a long time to run

We are trying to re-enable the valve CI... but doing so runs all the
jobs, including the manual ones.

Since some can take over an hour to run, let's disable them, and
re-enable them in another MR by reverting this commit.

Sorry for the noise!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

Revert "ci: mark the valve farm as down"

Fixed by rebooting the gateway. A post-mortem analysis will be
performed to figure out what happened!

This reverts commit 2089fc8188635ed0ee72e2ddc009e7a775210bb7.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

nir_opt_algebraic: don't use i32csel without native integer support

Otherwise nir_lower_int_to_float (or specifically nir_gather_ssa_types)
will fail to recognize we already have float constants and converts them
again.

Example from spec/glsl-1.10/execution/vs-loop-array-index-unroll.shader_test
with r300 driver (after enabling has_fused_comp_and_csel).

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x3e800000, 0x3f800000) = (0.000000, 0.250000, 1.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x3f000000, 0x3f800000) = (0.000000, 0.500000, 1.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x3f400000, 0x3f800000) = (0.000000, 0.750000, 1.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x3f800000) = (0.000000, 1.000000)
        vec1 32 ssa_6 = load_const (0x3f800000 = 1.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec4  1 ssa_9 = ilt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_15 = i32csel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_15.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

and after nir_lower_int_to_float

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x4e7a0000, 0x4e7e0000) = (0.000000, 1048576000.000000, 1065353216.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x4e7c0000, 0x4e7e0000) = (0.000000, 1056964608.000000, 1065353216.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x4e7d0000, 0x4e7e0000) = (0.000000, 1061158912.000000, 1065353216.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x4e7e0000) = (0.000000, 1065353216.000000)
        vec1 32 ssa_6 = load_const (0x4e7e0000 = 1065353216.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x3f800000, 0x40000000, 0x40400000) = (0.000000, 1.000000, 2.000000, 3.000000)
        vec4  1 ssa_9 = flt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_13 = fcsel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_13.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23704>

docs/ci: fix command to disable/re-enable farms

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23780>

r600/sfn: Add source mod propagation also to fp64 ops

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>

r600/sfn: Implement fsat for 64 bit ops

Because a plain mov with the fsat modifier doesn't do a proper 64 bit fsat
we either have to propagate the op as modifier to the instruction that
creates the value, or we add a fake op that applies the fsat op, i.e. we
implement the mov as an add_64 with zero as the second value.

Fixes:  0ff3c4bef21e6768a53610337c39d1e306b3869e
    r600/sfn: drop use of nir source mods

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>

anv: update conformanceVersion

The Vulkan CTS started generating the list of valid versions the driver
can report as conformant against based on the active branches, and the
1.3.0 branch we were reporting up to now is no longer valid.

Fixes dEQP-VK.api.driver_properties.conformance_version

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23784>