net: phy: add Motorcomm YT8531S phy id.

We added patch for motorcomm.c to support YT8531S. This patch has
been tested on AM335x platform which has one YT8531S interface
card and passed all test cases.
The tested cases indluding: YT8531S UTP function with support of
10M/100M/1000M; YT8531S Fiber function with support of 100M/1000M;
and YT8531S Combo function that supports auto detection of media type.

Since most functions of YT8531S are similar to YT8521 and we reuse some
codes for YT8521 in the patch file.

Signed-off-by: Frank <Frank.Sae@motor-comm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: Ic52d4469045c2bfbf97250e137004729fc6dea46

net: phy: fix yt8521 duplicated argument to & or |

cocci warnings: (new ones prefixed by >>)
>> drivers/net/phy/motorcomm.c:1122:8-35: duplicated argument to & or |
  drivers/net/phy/motorcomm.c:1126:8-35: duplicated argument to & or |
  drivers/net/phy/motorcomm.c:1130:8-34: duplicated argument to & or |
  drivers/net/phy/motorcomm.c:1134:8-34: duplicated argument to & or |

 The second YT8521_RC1R_GE_TX_DELAY_xx should be YT8521_RC1R_FE_TX_DELAY_xx.

Fixes: 70479a40954c ("net: phy: Add driver for Motorcomm yt8521 gigabit ethernet phy")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Frank <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I3f15389f5b7c13d23c068b1f5c178dc9462d05d1

net: phy: Add driver for Motorcomm yt8521 gigabit ethernet phy

Add a driver for the motorcomm yt8521 gigabit ethernet phy. We have verified
 the driver on StarFive VisionFive development board, which is developed by
 Shanghai StarFive Technology Co., Ltd.. On the board, yt8521 gigabit ethernet
 phy works in utp mode, RGMII interface, supports 1000M/100M/10M speeds, and
 wol(magic package).

Signed-off-by: Frank <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I98c7dd937da59afce8a5a79fa78c6cca8dc47096

RISCV: configs: enable FUSE_FS configuration

Enable CONFIG_FUSE_FS configs and other missed configs.

Change-Id: If6c234ad9b945bd0e9b634cd03fafe681a15dfe1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

RISCV: configs: Enanble some configs from module to static

Enable some configs from module to static.
Current module partitions is using to 32MB, so it needs to decrease
module size under 32MB.

Change-Id: I9925f0019540b984e4d400b1fbc054ee8b05e960
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

config: Enable FTRACE

Required by IoT-headless preset.

Change-Id: I779f566b1e7bd74a7db168c909e1ebdb7287caee
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>

packaging: Add version to modules directory

Prevents conflict with `filesystem` package.

Change-Id: I5281cf8f5349d82bdcaed9b66fdc0cb6896af96b
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>

config: Enable NBD module

Useful for development with networked SD card emulation.

Change-Id: Ie02b2bdd81b44d874978497cb9dded874a9482a3
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>

media: starfive: add "WITH Linux-syscall-note" to SPDX tag of uapi headers

UAPI headers licensed under GPL are supposed to have exception
"WITH Linux-syscall-note" so that they can be included into non-GPL
user space application code.

Change-Id: I129c7bf343e3da61f8d49a023b5d16699cb18796
Origin: upstream, https://github.com/starfive-tech/linux/pull/94
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>

RISCV: configs: enable USB/ETH configurations

Enable USB/ETH configuration relevant to JH7110.

Change-Id: I14b9e28cb96b38765997373375f87bdb71ca00f7
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

build: add the separated device tree file

Add the separated device tree file according to VisionFive2 board
revision.

Change-Id: I35fa7e81199f363e0cda53fd9ecac5943743a3ab
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

build: Add local build script for VisionFive2

Add local build script for VisionFive2.

Change-Id: I0ca80fd1e383b9ce62797944fba1755e315fa9c7
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

packaging: Add linux-visionfive2 spec file

Add linux-visionfive2 spec vile to build with gbs.
This is for only visionfive2 board.

Change-Id: Icc8feec48b9d77c27b4ce8f2d9468ca882d1fca1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

riscv: fix riscv64 unrecognized opcode build error

Considering older gcc version, "imafd" has to be changed
to "g", in order for asm to handle "zicsr" and "zifencei"
extensions.

Support for the mentioned extensions has been added
in GCC 11.1, hence this commit may be removed
after GCC update.

The lack of this causes following errors:
Error: unrecognized opcode `csrr a5,0xc01'
Error: unrecognized opcode `csrr a2,0xc01'

Change-Id: I0768a7b1255c828c4fc319f74f2783bc7e1581bf
Signed-off-by: Marek Szulc <m.szulc3@samsung.com>
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>

RISCV: configs: Add tizen_vf2_defconfig file

Add tizen_vf2_defconfig file for VisionFive2 boardi.
This defconfig is an initial version to use Tizen on VisionFive2.

Change-Id: Ie675e71129f698d294f637f7545be323466537de
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

RISC-V: Add arch functions to support hibernation/suspend-to-disk

Low level Arch functions were created to support hibernation.
swsusp_arch_suspend() relies code from __cpu_suspend_enter() to write
cpu state onto the stack, then calling swsusp_save() to save the memory
image.

Arch specific hibernation header is implemented and is utilized by the
arch_hibernation_header_restore() and arch_hibernation_header_save()
functions. The arch specific hibernation header consists of satp, hartid,
and the cpu_resume address. The kernel built version is also need to be
saved into the hibernation image header to making sure only the same
kernel is restore when resume.

swsusp_arch_resume() creates a temporary page table that covering only
the linear map. It copies the restore code to a 'safe' page, then start
to restore the memory image. Once completed, it restores the original
kernel's page table. It then calls into __hibernate_cpu_resume()
to restore the CPU context. Finally, it follows the normal hibernation
path back to the hibernation core.

To enable hibernation/suspend to disk into RISCV, the below config
need to be enabled:
- CONFIG_ARCH_HIBERNATION_HEADER
- CONFIG_ARCH_HIBERNATION_POSSIBLE

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

RISC-V: mm: Enable huge page support to kernel_page_present() function

Currently kernel_page_present() function doesn't support huge page
detection causes the function to mistakenly return false to the
hibernation core.

Add huge page detection to the function to solve the problem.

Fixes: 9e953cda5cdf ("riscv: Introduce huge page support for 32/64bit kernel")
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

RISC-V: Factor out common code of __cpu_resume_enter()

The cpu_resume() function is very similar for the suspend to disk and
suspend to ram cases. Factor out the common code into suspend_restore_csrs
macro and suspend_restore_regs macro.

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

RISC-V: Change suspend_save_csrs and suspend_restore_csrs to public function

Currently suspend_save_csrs() and suspend_restore_csrs() functions are
statically defined in the suspend.c. Change the function's attribute
to public so that the functions can be used by hibernation as well.

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

dts: usb: add StarFive JH7110 USB dts configuration.

USB Glue layer and Cadence USB subnode configuration,
also includes USB and PCIe phy dts configuration.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

usb: cdns3: add StarFive JH7110 USB driver.

There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child of this USB wrapper module device.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

dt-binding: Add JH7110 USB wrapper layer doc.

The dt-binding doc of Cadence USBSS-DRD controller wrapper
layer.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Peter Chen <peter.chen@kernel.org>

phy: starfive: add JH7110 PCIE 2.0 and USB 2.0 PHY driver.

Add Starfive JH7110 SoC PCIe 2.0 and USB 2.0 PHY driver support.
PCIe 2.0 PHY can used as USB 3.0 PHY

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

dt-bindings: phy: Add StarFive JH7110 USB/PCIe document

Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
PCIe 2.0 phy can use as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

media: starfive: Add Starfive Camera Subsystem driver

Add the driver for Starfive Camera Subsystem found on
Starfive JH7110 SoC. It is used for handing image sensor
data.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>

MAINTAINERS: Add Starfive Camera Subsystem driver

Add an entry for Starfive Camera Subsystem driver.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>

media: cadence: Add support for external dphy and JH7110 SoC

Add support for external MIPI D-PHY and Starfive JH7110 SoC which
has the cadence csi2 receiver.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>

media: admin-guide: Add starfive_camss.rst for Starfive Camera Subsystem

Add the file 'starfive_camss.rst' that documents the Starfive Camera
Subsystem driver which is used for handing image sensor data.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>

media: dt-bindings: cadence-csi2rx: Convert to DT schema

Convert DT bindings document for Cadence MIPI-CSI2 RX controller
to DT schema format and add new properties.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>

media: dt-bindings: Add bindings for JH7110 Camera Subsystem

Add the bindings documentation for Starfive JH7110 Camera Subsystem
which is used for handing image sensor data.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>

riscv: dts: starfive: Add dphy rx node

Add dphy rx node for the StarFive JH7110 SoC. It is used to transfer CSI
camera data.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>

phy: starfive: Add mipi dphy rx support

Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
transfer CSI camera data.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>

dt-bindings: phy: Add starfive,jh7110-dphy-rx

StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>

crypto: starfive - Add hash and HMAC support

Adding hash/HMAC support for SHA-2 and SM3 to StarFive cryptographic
module.

Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>

riscv: dts: starfive: Add crypto and DMA node for VisionFive 2

Add StarFive cryptographic module and dedicated DMA controller node to
VisionFive 2 SoCs.

Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

crypto: starfive - Add crypto engine support

Adding device probe and DMA init for StarFive cryptographic module.

Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>

dt-bindings: crypto: Add StarFive crypto module

Add documentation to describe StarFive cryptographic engine.

Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>

riscv: dts: starfive: Add TRNG node for VisionFive 2

Adding StarFive TRNG controller node to VisionFive 2 board.

Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>

riscv: dts: starfive: add dma controller node

Add the dma controller node for the Starfive JH7110 SoC.

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>

dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA

Add DMA reset operation in device probe and use different configuration
on CH_CFG registers according to match data. Update all uses of
of_device_is_compatible with of_device_get_match_data.

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>

dt-bindings: dma: snps,dw-axi-dmac: constrain the items of resets for JH7110 dma

The DMA controller needs two reset items to work properly on JH7110 SoC,
so there is need to constrain the items' value to 2, other platforms
have 1 reset item at most.

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>

riscv: dts: starfive: visionfive-2: Add thermal-zones

Add thermal-zones for StarFive VisionFive 2 board.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

riscv: dts: starfive: jh7110: Add temperature sensor node

Add temperature sensor support for StarFive JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

hwmon: (sfctemp) Add StarFive JH71x0 temperature sensor

Add driver for the StarFive JH71x0 temperature sensor. You
can enable/disable it and read temperature in milli Celcius
through sysfs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

dt-bindings: hwmon: Add starfive,jh71x0-temp

Add bindings for the temperature sensor on the StarFive JH7100 and
JH7110 SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>

riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy

v1.3B:
  v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
  inverse configurations.
  The tx_clk of v1.3B uses an external clock and needs to be
  switched to an external clock source.

v1.2A:
  v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
  configurations.
  v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
  switch rx and rx to external clock sources.

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

riscv: dts: starfive: jh7110: Add ethernet device nodes

Add JH7110 ethernet device node to support gmac driver for the JH7110
RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

net: stmmac: starfive_dmac: Add phy interface settings

dwmac supports multiple modess. When working under rmii and rgmii,
you need to set different phy interfaces.

According to the dwmac document, when working in rmii, it needs to be
set to 0x4, and rgmii needs to be set to 0x1.

The phy interface needs to be set in syscon, the format is as follows:
starfive,syscon: <&syscon, offset, shift>

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

net: stmmac: Add glue layer for StarFive JH7110 SoC

This adds StarFive dwmac driver support on the StarFive JH7110 SoC.

Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

dt-bindings: net: Add support StarFive dwmac

Add documentation to describe StarFive dwmac driver(GMAC).

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

dt-bindings: net: snps,dwmac: Add 'ahb' reset/reset-name

According to:
stmmac_platform.c: stmmac_probe_config_dt
stmmac_main.c: stmmac_dvr_probe

dwmac controller may require one (stmmaceth) or two (stmmaceth+ahb)
reset signals, and the maxItems of resets/reset-names is going to be 2.

The gmac of Starfive Jh7110 SOC must have two resets.
it uses snps,dwmac-5.20 IP.

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

net: stmmac: platform: Add snps,dwmac-5.20 IP compatible string

Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid
to define some platform data in the glue layer.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

dt-bindings: net: snps,dwmac: Add dwmac-5.20 version

Add dwmac-5.20 IP version to snps.dwmac.yaml

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

riscv: dts: starfive: Add PWM node

Adding StarFive PWM controller node to VisionFive 2 SoC.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>

pwm: starfive: Add PWM driver support

Add Pulse Width Modulation driver support for StarFive
JH7110 soc.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>

dt-bindings: PWM: Add StarFive PWM module

Add documentation to describe StarFive Pulse Width Modulation
controller driver.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

riscv: dts: starfive: jh7110: Add qspi controller node

Add the quad spi controller node for the Starfive JH7110 SoC.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>

spi: cadence-quadspi: Add support for StarFive JH7110 QSPI

Add QSPI reset operation in device probe and add RISCV support to
QUAD SPI Kconfig.

Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230302105221.197421-3-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>

dt-bindings: qspi: cdns,qspi-nor: constrain minItems/maxItems of resets

The QSPI controller needs three reset items to work properly on JH7110 SoC,
so there is need to change the maxItems's value to 3 and add minItems
whose value is equal to 2. Other platforms do not have this constraint.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230302105221.197421-2-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>

riscv: dts: starfive: Add mmc node

Adds the mmc node for the StarFive JH7110 SoC.
Set mmco node to emmc and set mmc1 node to sd.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>

riscv: dts: jh7110: starfive: Add timer node

Add the timer node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

clocksource: Add StarFive timer driver

Add timer driver for the StarFive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: timer: Add timer for StarFive JH7110 SoC

Add bindings for the timer on the JH7110 RISC-V SoC
by StarFive Technology Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

riscv: dts: starfive: jh7110: Add watchdog node

Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

riscv: dts: starfive: jh7100: Add watchdog node

Add watchdog node for the StarFive JH7100 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

drivers: watchdog: Add StarFive Watchdog driver

Add watchdog driver for the StarFive JH7100 and JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: watchdog: Add watchdog for StarFive JH7100 and JH7110

Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC.
And Use JH7100 as first StarFive SoC with watchdog.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

clk: starfive: jh7110-sys: Modify PLL clocks source

Modify PLL clocks source to be got from dts instead of
the fixed factor clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

Add PLL clock inputs from PLL clock generator.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

dt-bindings: soc: starfive: syscon: Add optional patternProperties

Add optional compatible and patternProperties.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

clk: starfive: Add StarFive JH7110 PLL clock driver

Add driver for the StarFive JH7110 PLL clock controller.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: clock: Add StarFive JH7110 PLL clock generator

Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes

Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
System-Top-Group, Image-Signal-Process and Video-Output
clock and reset drivers for the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks

Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

clk: starfive: Add StarFive JH7110 Video-Output clock driver

Add driver for the StarFive JH7110 Video-Output clock controller.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

reset: starfive: jh7110: Add StarFive Video-Output reset support

Add auxiliary_device_id to support StarFive JH7110 Video-Output resets
of which the auxiliary device name is "clk_starfive_jh71x0.reset-vout".

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver

Add driver for the StarFive JH7110 Image-Signal-Process clock controller.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support

Add auxiliary_device_id to support StarFive JH7110 Image-Signal-Process
resets of which the auxiliary device name is
"clk_starfive_jh71x0.reset-isp".

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: starfive: Add StarFive JH7110 System-Top-Group clock driver

Add driver for the StarFive JH7110 System-Top-Group clock controller.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

reset: starfive: jh7110: Add StarFive System-Top-Group reset support

Add auxiliary_device_id to support StarFive JH7110 System-Top-Group resets
of which the auxiliary device name is "clk_starfive_jh71x0.reset-stg".

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

riscv: dts: starfive: Add syscon node

Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

dt-bindings: soc: starfive: Add StarFive syscon doc

Add documentation to describe StarFive System Controller Registers.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: add pmu controller node

Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs
to be used by other modules such as VPU, ISP, etc.

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>

riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree

Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

riscv: dts: starfive: Add StarFive JH7110 pin function definitions

Add pin function definitions for StarFive JH7110 SoC.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

riscv: dts: starfive: Add initial StarFive JH7110 device tree

Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

dt-bindings: riscv: Add SiFive S7 compatible

Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

dt-bindings: interrupt-controller: Add StarFive JH7110 plic

Add compatible string for StarFive JH7110 plic.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

dt-bindings: timer: Add StarFive JH7110 clint

Add compatible string for the StarFive JH7110 clint.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

reset: starfive: Add StarFive JH7110 reset driver

Add auxiliary driver to support StarFive JH7110 system
and always-on resets.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

clk: starfive: Add StarFive JH7110 always-on clock driver

Add driver for the StarFive JH7110 always-on clock controller
and register an auxiliary device for always-on reset controller
which is named as "reset-aon".

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

clk: starfive: Add StarFive JH7110 system clock driver

Add driver for the StarFive JH7110 system clock controller and
register an auxiliary device for system reset controller which
is named as "reset-sys".

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator

Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

reset: starfive: jh71x0: Use 32bit I/O on 32bit registers

We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.

There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.

Switch to 32bit I/O in preparation for supporting these resets too.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

reset: starfive: Rename "jh7100" to "jh71x0" for the common code

For the common code will be shared with the StarFive JH7110 SoC.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>