shaohui xie [Tue, 15 Nov 2016 06:36:47 +0000 (14:36 +0800)]
net: fman: fix 2.5G SGMII settings
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
oliver@schinagl.nl [Tue, 8 Nov 2016 16:38:59 +0000 (17:38 +0100)]
net: phy: realtek: Only force master mode on rtl8211b/c
Commit
525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
oliver@schinagl.nl [Tue, 8 Nov 2016 16:38:58 +0000 (17:38 +0100)]
net: phy: realtek: make define more consistent
All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
oliver@schinagl.nl [Tue, 8 Nov 2016 16:38:57 +0000 (17:38 +0100)]
net: phy: realtek: Use the BIT() macro
The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Mon, 14 Nov 2016 14:08:42 +0000 (15:08 +0100)]
net: phy: micrel: Fix error handling
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Tue, 6 Dec 2016 13:07:20 +0000 (08:07 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
Stefan Roese [Mon, 18 Jul 2016 10:51:39 +0000 (12:51 +0200)]
usb: xhci-pci: Add DM support
This patch adds DM support to the xHCI PCI driver. Enabling its use
e.g. in x86 platforms.
Status: On the congatec BayTrail SoM, xHCI still does not work
correctly with this patch. Some internal timeouts lead to resets (BUG).
Additional work is needed here. I'm posting this version as WIP so that
other developers interested in this support might use it as a start.
I might get back to it in a few weeks as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagan Teki [Fri, 25 Nov 2016 17:47:28 +0000 (23:17 +0530)]
MAINTAINERS: Fix ALTERA SOCFPGA Files
Replace arch/arm/cpu/armv7/socfpga/ path with
arch/arm/mach-socfpga/ and removed board file path
since board/altera has different boards with relevant
board maintainers.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Dinh Nguyen [Tue, 29 Nov 2016 15:03:13 +0000 (09:03 -0600)]
MAINTAINERS: socfpga: update email address for Dinh Nguyen
With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Bill Randle [Sat, 19 Nov 2016 04:23:33 +0000 (20:23 -0800)]
qts-filter.sh: strip DOS line endings and handle continuation lines
Some Altera Quartus generated files have long lines that are split with a '\' at
the end of the line. It also wOn Windows, rites files in DOS format, which can
confuse some of the processing scripts in this file. This patch solves both issues.
Signed-off-by: Bill Randle <bill.randle@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 16 Nov 2016 16:20:23 +0000 (17:20 +0100)]
ARM: socfpga: Add boot0 hook to prevent SPL corruption
Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.
The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:
ffff0040 <data_abort>:
ffff0040:
ebfffffe bl
ffff0040 <data_abort>
ffff0044 <reset>:
ffff0044:
ea000012 b
ffff0094 <save_boot_params>
ffff0048 <save_boot_params_ret>:
ffff0048:
e10f0000 mrs r0, CPSR
ffff004c:
e200101f and r1, r0, #31
ffff0050:
e331001a teq r1, #26
Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.
Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Anatolij Gustschin [Mon, 14 Nov 2016 15:07:10 +0000 (16:07 +0100)]
socfpga: add support for Terasic DE1-SoC board
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
Tom Rini [Mon, 5 Dec 2016 23:36:23 +0000 (18:36 -0500)]
Prepare v2017.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 5 Dec 2016 22:00:23 +0000 (17:00 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Yuan Yao [Thu, 1 Dec 2016 02:13:52 +0000 (10:13 +0800)]
armv8: QSPI: Add AHB bus 16MB+ size support
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
jerry.huang@nxp.com [Thu, 1 Dec 2016 03:44:25 +0000 (11:44 +0800)]
fsl/usb: enable the errata-a005697 for ls1012a
Enable the errata-a005697 for ls1012a
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yuan Yao [Wed, 30 Nov 2016 03:26:20 +0000 (11:26 +0800)]
ls1021a: QSPI: update the node for QSPI support
Add the name for register space and memory space.
<0x1550000 0x10000 > is the QSPI register space.
<0x40000000 0x4000000> is the QSPI memory space.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Priyanka Jain [Tue, 29 Nov 2016 11:15:05 +0000 (16:45 +0530)]
armv8: ls2080a: Add serdes1 protocol 0x3b support
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Mon, 21 Nov 2016 03:36:48 +0000 (11:36 +0800)]
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Mon, 21 Nov 2016 03:36:47 +0000 (11:36 +0800)]
fsl/ddr: Fix compiling warning
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Stefan Roese [Thu, 1 Dec 2016 12:52:08 +0000 (13:52 +0100)]
travis-ci: Build mvebu boards (arm & aarch64) in separate job
Its easier to watch the output of the build process when the platforms
specific boards are grouped in a separate job. This patch adds a job
for all mvebu boards (arm and aarch64).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Bartosz Golaszewski [Thu, 1 Dec 2016 11:07:43 +0000 (12:07 +0100)]
davinci: omapl138_lcdk: increase PLL0 frequency
The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Yegor Yefremov [Thu, 1 Dec 2016 11:52:18 +0000 (12:52 +0100)]
arm: baltos: enable booting from USB
First of all U-Boot would search for a USB mass storage device
with either uEnv.txt or kernel-fit.itb and boot.
If USB mass storage device is not available or doesn't provide
these files then MMC will be tried.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Yegor Yefremov [Thu, 1 Dec 2016 11:52:17 +0000 (12:52 +0100)]
arm: baltos: active mPCIe slot
Baltos devices provide a mPCIe slot, whose power is turned off by
default. This patch activates mPCIe slot in U-Boot, so that for example
GSM modem can be already available in user space.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Yegor Yefremov [Thu, 1 Dec 2016 11:52:16 +0000 (12:52 +0100)]
arm: baltos: remove TI board leftover
Remove unneeded pinmux configurations and TI EEPROM struct.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Jean-Jacques Hiblot [Thu, 1 Dec 2016 09:37:03 +0000 (10:37 +0100)]
ARM: DRA7: AMxx: Make sure that the SPL always reads the configuration EEPROM
The bootrom may corrupt the area of SRAM used to store the ti_common_eeprom
structure. This patch makes sure that it's always read after a reset, even
if a valid MAGIC number is found in the SRAM.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Michal Simek [Thu, 1 Dec 2016 10:09:01 +0000 (11:09 +0100)]
dm: spl: mmc: Fix EXT SPL support
The patch
"dm: spl: mmc: Support CONFIG_BLK in SPL MMC"
(sha1:
87bce4e5c0b55452d70830928b2d7b98fa24d4e3)
converted FAT part of spl_mmc_do_fs_boot() but forget to update also EXT
part by 's/&mmc->block_dev/mmc_get_blk_desc(mmc)/'.
This patch is fixing compilation error when CONFIG_SPL_EXT_SUPPORT
is enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 5 Dec 2016 16:02:01 +0000 (11:02 -0500)]
Merge git://www.denx.de/git/u-boot-i2c
Stefan Roese [Fri, 18 Nov 2016 16:21:51 +0000 (17:21 +0100)]
sata: sata_mv: Fix misaligned cache warnings
This patch fixes the warnings about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [
7facb400,
7facb460]
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Fri, 11 Nov 2016 07:18:44 +0000 (08:18 +0100)]
arm64: mvebu: Restrict memory size to a usable maximum
Not all memory is mapped in the MMU. So we need to restrict the memory
size so that U-Boot does not try to access it. Also, the internal
registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB
are mapped for system memory. This is what we pass to the U-Boot
subsystem here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Thu, 27 Oct 2016 11:36:45 +0000 (13:36 +0200)]
arm64: mvebu: Add PCI support to DB-88F8040 board
This patch adds PCI support to the Marvell Armada-8K devel board.
Additionally the Intel E1000 ethernet driver is enabled so that
network support is available on this board, even without the
internal network interfaces being supported (yet).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Thu, 27 Oct 2016 11:34:03 +0000 (13:34 +0200)]
arm64: mvebu: Add regions for PCI spaces to the memory map
To use the PCIe driver, its controller memory and the PCIe regions need
to get mapped in the MMU. Otherwise these areas can't be accessed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Shadi Ammouri [Thu, 27 Oct 2016 11:29:41 +0000 (13:29 +0200)]
pci: mvebu: Add PCIe driver for Armada-8K
This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.
The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.
Tested on the Marvell DB-88F8040 Armada-8K eval board.
Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:16:25 +0000 (18:16 +0200)]
drivers/phy: marvell: Add support for the slave CP COMPHY device
With the support for the Armada 8k, a 2nd COMPHY controller now needs
to get supported from the CP110 slave controller. This patch adds support
for this 2nd contoller in the COMPHY driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:12:40 +0000 (18:12 +0200)]
arm64: mvebu: Init COMPHY from the slave-CP on the A8k
The Armada8k implements 2 CPs (communication processors) and the 2nd
CP also is equipped with a COMPHY controller. This patch now loops
over all enabled MISC devices (CP110) enabled in the DT to initialize
all CPs.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:11:44 +0000 (18:11 +0200)]
arm64: mvebu: armada-8040-db.dts: Add I2C and SPI aliases
Add I2C and SPI aliases to enable usage in U-Boot. Otherwise U-Boot will
not be able to use the SPI NOR chip for environment storage and use
"i2c dev 0" to select this I2C bus.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 15:43:25 +0000 (17:43 +0200)]
arm64: mvebu: armada-8040-db.dts: Add COMPHY configuration
This patch adds the COMPHY device tree configuration to the DT file for
the Marvell DB-88F8040 devel board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 15:41:12 +0000 (17:41 +0200)]
arm64: mvebu: armada-cp110-slave.dtsi: Add COMPHY / UTMI device tree nodes
This patch adds the COMPHY and UTMI device tree nodes to the cp110-slave
dtsi file for the Armada 8K.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 15:35:55 +0000 (17:35 +0200)]
arm64: mvebu: armada-cp110-dtsi: Rename comphy DT node names
Since the cp110 slave also has comphy DT nodes, the names need to be
renamed to avoid a name clash. Lets use the common naming scheme:
"cpm_xxx" for master and "cps_xxx" for slave.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 09:47:51 +0000 (11:47 +0200)]
arm64: mvebu: Add support for the DB-88F8040 Armada 8k devel board
This patch adds the necessary files to support the Marvell Armada 8k
devel board. Most board specfic files are shared with the Armada 7k
boards under the name "armada-8k*". So only minimal changes are
necessary to add this basic board support (except the DT files of
course).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:14:29 +0000 (18:14 +0200)]
arm64: mvebu: Add slave CP area to the memory map
To enable access to the slave CP its memory needs to be added to the
MMU memory map.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 10:41:45 +0000 (12:41 +0200)]
arm64: mvebu: armada-8k: Only configure xHCI power on DB-88F7040 board
This patch uses of_machine_is_compatible() to detect the board at runtime
and only configured the I2C IO expander for the xHCI power / reset on
the DB-88F7040 board. As this code will be used by other Armada-7k/8k
ports, its necessary to use this runtime detection here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 08:10:32 +0000 (10:10 +0200)]
arm64: mvebu: Add Armada-80x0 dts/dtsi files
Add the latest version of the DT files from the Linux kernel.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 08:56:19 +0000 (10:56 +0200)]
arm64: mvebu: Rename db-88f7040 files to armada-8k
This moves some of the Armada DB-88F7040 board specific files to a more
generic name: armada-8k. This is in preparation for the Armada-8k
support which will be added soon. And since both platforms share
most devices, lets also share most source files to not duplicate
the code here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Simon Glass [Wed, 23 Nov 2016 13:34:45 +0000 (06:34 -0700)]
dm: Add timeline and guide for porting I2C drivers
Add a README with a brief guide to porting i2c drivers over to use driver
model.
Add a timeline also. All I2C drivers should be converted by the end
of June 2017.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:34:44 +0000 (06:34 -0700)]
dm: i2c: Add a note to I2C drivers which need conversion
Maintainers need to be notified more directly of the need to convert these
drivers. Add a note to the top each affected file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:34:43 +0000 (06:34 -0700)]
samsung: i2c: Split the high-speed I2C code into a new driver
Now that driver model is used for I2C on all boards, we can split the
high-speed code into its own driver. There is virtually no common code,
and this significantly reduces confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:34:42 +0000 (06:34 -0700)]
samsung: i2c: Drop old code from I2C driver
Now that all boards use DM_I2C we can drop the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:34:41 +0000 (06:34 -0700)]
arm: samsung: Convert s5p_goni and smdkc100 to DM_I2C
These are the last two samsung boards that don't use DM_I2C. Move them
over, leaving #ifdefs to allow the maintainer to complete this work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:34:40 +0000 (06:34 -0700)]
arm: exynos: i2c: Convert exynos boards to use DM_I2C
Three boards are still not converting to use DM_I2C. They are also using
the old PMIC framework. Rather than removing them, add #ifdefs to allow
them to continue to build. This will give the maintainers a little more
time to decide whether to convert them or not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Tom Rini [Sun, 4 Dec 2016 18:55:15 +0000 (13:55 -0500)]
Merge git://git.denx.de/u-boot-mpc85xx
Vignesh R [Tue, 22 Nov 2016 09:12:56 +0000 (14:42 +0530)]
defconfig: am43xx_evm: Enable DM_SPI and DM_SPI_FLASH
Commit
4c4e3b37750f3("ARM: AM43xx: Enable FIT") accidentally disabled
DM_SPI and DM_SPI_FLASH. Add back DM_SPI and DM_SPI_FLASH to
am43xx_evm_defconfig in order to make use of DM framework for QSPI.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Andrew F. Davis [Mon, 21 Nov 2016 20:37:09 +0000 (14:37 -0600)]
common: image: Remove FIT header update from image post-processing
After an image is selected out of a FIT blob for further processing we
run an optional, platform specific, post-processing function on this
component. This post-processing may modify the position and size of the
image, so after post-processing we update the location and size for this
image in the FIT header. This can cause problems as the position of
subsequent components in the FIT blob are only referenced by relative
position to the end of the last component. When we resize or move a
component the following components position will be calculated
incorrectly. To fix this, we do not update the FIT header but instead
only update our local understanding of the image data. This also allows
us to re-run post-processing steps if needed.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Tested-by: Carlos Hernandez <ceh@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:16 +0000 (00:50 +0000)]
usb: gadget: remove unused shortname variable
The shortname variable isn't referenced anywhere in the code, so just
remove it.
Pointed out by a GCC 6.2 default warning option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:12 +0000 (00:50 +0000)]
davinci: da8xxevm: fix indentation
Apparently the indentation is wrong in this case, as the second message
should be printed indepdently of the if statement.
Fix this indentation to avoid both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:11 +0000 (00:50 +0000)]
usb: eth: r8152_fw: fix indentation
Apparently the indentation is wrong here, fix this to avoid compiler
warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:10 +0000 (00:50 +0000)]
marvell: comphy_a3700: fix bitmask
Obviously the mask for the rx and tx select field cannot be right,
as it would overlap in one and exceed the 32-bit register in the other
case. From looking at the neighbouring bits it looks like the mask
should be really 4 bits wide instead of 8.
Pointed out by a GCC 6.2 (default) warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Andre Przywara [Wed, 16 Nov 2016 00:50:09 +0000 (00:50 +0000)]
net: rtl8169: remove unneeded definition
The rtl8169_intr_mask variable isn't used anywhere in the code, so
just remove it to avoid a GCC 6.2 compiler warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:07 +0000 (00:50 +0000)]
net: e1000: fix indentation
Apparently the indentation is off here, for the IGB model just want to
bail out early.
Fix this to avoid both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:06 +0000 (00:50 +0000)]
mtd: cfi_flash: fix indentation
The indentation is misleading here and suggests that the write command
will be only executed in the else clause.
It seems like this is not intended, so fix the indentation to avoid
both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:01:32 +0000 (06:01 -0700)]
serial: Drop the s3c24x0 serial driver
This is not used by any boards. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: David Müller <d.mueller@elsoft.ch>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Simon Glass [Wed, 23 Nov 2016 13:01:31 +0000 (06:01 -0700)]
arm: Remove VCMA9 board
This board has not been converted to DM_SERIAL by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: David Müller <d.mueller@elsoft.ch>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Simon Glass [Wed, 23 Nov 2016 13:01:30 +0000 (06:01 -0700)]
arm: Remove smdk2410 board
This board has not been converted to DM_SERIAL by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: David Müller <d.mueller@elsoft.ch>
Simon Glass [Wed, 23 Nov 2016 13:01:29 +0000 (06:01 -0700)]
serial: Update docs to indicate mcfuart supports DM_SERIAL
This driver was converted so we should remove it from the list.
Signed-off-by: Simon Glass <sjg@chromium.org>
Niko Mauno [Wed, 23 Nov 2016 12:52:32 +0000 (14:52 +0200)]
post: cosmetic: fix typo
Change 'date' to 'data'.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Walt Feasel [Wed, 23 Nov 2016 06:26:14 +0000 (01:26 -0500)]
Cosmetic api: api_storage.c Spelling correction
Make spelling correction for 'from'
Signed-off-by: Walt Feasel <waltfeasel@gmail.com>
Walt Feasel [Wed, 23 Nov 2016 06:26:13 +0000 (01:26 -0500)]
Cosmetic api: api_storage.c Comment style
Make comment style modifications
Signed-off-by: Walt Feasel <waltfeasel@gmail.com>
Walt Feasel [Wed, 23 Nov 2016 06:26:12 +0000 (01:26 -0500)]
Cosmetic api: api_storage.c Line over 80 char
Make checkpatch style modification for
WARNING: line over 80 characters
Signed-off-by: Walt Feasel <waltfeasel@gmail.com>
Walt Feasel [Wed, 23 Nov 2016 06:26:11 +0000 (01:26 -0500)]
Cosmetic api: api_storage.c Blank line after {
Make checkpatch style modification for
CHECK: Blank lines aren't necessary after
an open brace '{'
Signed-off-by: Walt Feasel <waltfeasel@gmail.com>
Walt Feasel [Wed, 23 Nov 2016 06:26:10 +0000 (01:26 -0500)]
Cosmetic api: api_storage.c Align parenthesis
Make checkpatch style modification for
CHECK: Alignment should match open parenthesis
Signed-off-by: Walt Feasel <waltfeasel@gmail.com>
Lokesh Vutla [Fri, 25 Nov 2016 05:44:26 +0000 (11:14 +0530)]
ti_armv7_common: env: Increase IO buffer size
There are certain environment variables whose length is greater than
the defined IO buffer size. So, increase the IO buffer size to print the
entire variables.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Schuyler Patton [Fri, 25 Nov 2016 05:44:25 +0000 (11:14 +0530)]
ARM: dts: AM571x-IDK Initial Support
Add initial DTS support for AM571-IDK evm.
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Steve Kipisz [Fri, 25 Nov 2016 05:44:24 +0000 (11:14 +0530)]
board: ti: am57xx: Add support for the am571x idk
The AM571x Industrial Development Kit (IDK) is a board based on TI's
AM571x SoC which has a single core 1.5GHz Cortex-A15processor. This
board is a development platform for the Industrial Market with:
- 1GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The PRU/ICSS will be supported by 3rd party software for EtherCat,
Profibus, and other Industrial protocols.
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5718
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Fri, 25 Nov 2016 05:44:23 +0000 (11:14 +0530)]
board: ti: am572x-idk: Update pinmux using latest PMT
Update the board pinmux for AM572x-IDK board using latest PMT[1] and the
board files named am572x_idk_v1p3b_sr2p0 that were autogenerated on
20th October, 2016 by "Steve Kipisz <s-kipisz2@ti.com>" and
"Tom Johnson <thjohnson@ti.com>".
[1] https://dev.ti.com/pinmux/app.html#/default/
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Fri, 25 Nov 2016 05:44:22 +0000 (11:14 +0530)]
board: ti: am572x: Add pinmux for X15/GPEVM SR2.0 using latest PMT
Update the board pinmux for AM572x-IDK board using latest PMT[1] and the
board files named am572x_gp_evm_A3a_sr2p0 that were autogenerated on
19th October, 2016 by "Ahmad Rashed<a-rashed@ti.com>".
[1] https://dev.ti.com/pinmux/app.html#/default/
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Fri, 25 Nov 2016 05:44:21 +0000 (11:14 +0530)]
board: ti: am57xx: Update SR1.1 RGMII0 iodelay timings for x15/GPEVM
Update the timing for RGMII0 interface based on
PCT_DRA75x_DRA74x_SR1.1_v1.3.10 version (Jan 2016). This update
is for SR1.1
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Fri, 25 Nov 2016 05:44:20 +0000 (11:14 +0530)]
board: ti: am57xx: Add support for detection of X15 revb1
BeagleBoard-X15 Rev B1 with SR1.1 platform have incompatible changes for HDMI
GPIO requiring new dtb support. This implies we have to properly identify
the platform now as well. Hence provide a different board name for the
Rev B1 variants.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Fri, 25 Nov 2016 05:44:19 +0000 (11:14 +0530)]
board: ti: am57xx: Add support for detection of reva3 variations for GPEVM
AM57xx evm Rev A3 with SR2.0 platform have incompatible changes for HDMI
GPIO requiring new dtb support. This implies we have to properly identify
the platform now as well. Hence provide a different board name for the
Rev A3 variations.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Fri, 25 Nov 2016 05:44:18 +0000 (11:14 +0530)]
ARM: dts: am57xx: sync DT with latest Linux
Sync all am57xx based dts files with latest Linux
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Keerthy [Wed, 23 Nov 2016 07:55:34 +0000 (13:25 +0530)]
configs: dra7xx: Enable lp873x options
DRA71-evm uses LP873x regulator. Enable lp873x PMIC config options.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:33 +0000 (13:25 +0530)]
configs: dra7xx: Enable pmic/regulator options
Enable pmic/regulator config options.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:32 +0000 (13:25 +0530)]
configs: dra7xx: hs: Enable DM_ETH
Enable DM_ETH for hs boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 23 Nov 2016 07:55:31 +0000 (13:25 +0530)]
configs: ti_omap5_common: Select dtb name for dra71x
Select dtb name for dra71x-evm.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:30 +0000 (13:25 +0530)]
ARM: dts: dra71x-evm: Add DT support
Add DT support for dra71-evm and built it as part of FIT image.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:29 +0000 (13:25 +0530)]
ARM: dts: dra7xx: sync DT with latest Linux
Sync all dra7xx based dts files with latest Linux
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:28 +0000 (13:25 +0530)]
ARM: OMAP4+: Add support for getting pbias info from board
Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based
boards to enable mmc regulator. This is not true always like in case of
DRA71x-evm. So get this information based on the board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Delete omap4_vmmc_pbias_config from omap_hsmmc.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
Keerthy [Wed, 23 Nov 2016 07:55:27 +0000 (13:25 +0530)]
board: ti: dra71x-evm: Add PMIC support
Add the pmic_data for LP873x PMIC which is used to power
up dra71x-evm.
Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
the efuse registers only to use OPP_NOM irrespective of any
CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined.
[1] http://www.ti.com/product/DRA718/technicaldocuments
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 23 Nov 2016 07:55:26 +0000 (13:25 +0530)]
board: ti: dra72: Introduce optimization for rgmii timing for rev C
Rev C version of EVM does require IODelay to be configured for RGMII
pins in MANUAL_1 configuration. Update the same based on PG2.0 initial
simulation values.
Data based on PCT_DRA72x_SR2.0_SR1.0_v1.3.0.7
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:25 +0000 (13:25 +0530)]
board: ti: dra71x-evm: Add mux settings
Add mux and iodelay settings for dra71x-evm.
Data generated using PCT_DRA71x_SR2.0_v1.0.0.0 version (June 2016).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:55:24 +0000 (13:25 +0530)]
board: ti: dra71x-evm: Add epprom support
The dra71x-evm is a board based on TI's DRA718 processor targeting BOM-optimized
entry infotainment systems such as display audio and is a software compatible
derivative of the highly successful DRA74 and DRA72 processor families.
More information can be found here[1].
Add epprom detection for dra71-evm.
[1] http://www.ti.com/product/dra718
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 23 Nov 2016 07:24:41 +0000 (12:54 +0530)]
ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP
This patch adds support to update the device-tree blob to adjust the
DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
the default being OPP_NOM. The voltage settings are done in u-boot,
but the actual clock configuration itself is done in kernel because
of the following reasons:
1. SoC definition constraints us to NOT to do dynamic voltage
scaling ever after the initial avs0 setting in bootloader
- so the voltage must be set in bootloader.
2. The voltage level must be set even if the IP blocks like
GPU/DSP are unused.
3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
and similar DPLL clock configuration code has been cleaned up in
v2014.10 u-boot release. See commit,
02c41535b6a4 ("ARM: OMAP4/5:
Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
The non-essential DPLLs are configured within the kernel during
the clock init step when parsing the device tree and creating
the clock devices. This approach meets both the u-boot and kernel
needs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 23 Nov 2016 07:24:40 +0000 (12:54 +0530)]
ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.
The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.
The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:24:39 +0000 (12:54 +0530)]
ARM: OMAP4+: Add support for dynamically selecting OPPs
It can be expected that different paper spins of a SoC can have
different definitions for OPP and can have their own constraints
on the boot up OPP for each voltage rail. In order to have this
flexibility, add support for dynamically selecting the OPP voltage
based on the board to handle any such exceptions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 4 Dec 2016 18:54:19 +0000 (13:54 -0500)]
omap4_sdp4430: Disable SPL_OS_BOOT
We are tight on space on this board so drop SPL_OS_BOOT
Signed-off-by: Tom Rini <trini@konsulko.com>
York Sun [Thu, 1 Dec 2016 22:10:47 +0000 (14:10 -0800)]
powerpc: mpc86xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option
Use Kconfig instead of defining this macro in header file.
Signed-off-by: York Sun <york.sun@nxp.com>
Tom Rini [Sun, 4 Dec 2016 00:43:51 +0000 (19:43 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-dm
Yann E. MORIN [Sun, 13 Nov 2016 20:59:52 +0000 (21:59 +0100)]
cmd: move CMD_PXE to Kconfig
Currently, CMD_PXE is forcibly enabled in config_distro_defaults.h, so
that general purpose distributions can rely on it being defined. This
header is included, under conditions or not, by various archs or
famillies of archs / SoCs.
However, it is very possible that boards based on those SoCs will not
have a physical ethernet connector at all, even if the have a MAC; for
example, the Nanopi Neo AIR (sunxi H3) does not. It is also possible
that network booting is absolutely not necessary for a device.
However, it is not possible to disable the PXE command, as it is
forcibly enabled and is non-configurable.
But it turns out we already have a config option to build a distro-ready
image, in the name of DISTRO_DEFAULTS.
Move CMD_PXE out of the hard-coded config_distro_defaults.h into a
Kconfig option, that gets selected by DISTRO_DEFAULTS when it is set.
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Joe Hershberger <joe.hershberger@ni.com>
[trini: Make it select MENU, run moveconfig.py]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 29 Nov 2016 14:14:57 +0000 (09:14 -0500)]
Enable DISTRO_DEFAULT on platforms that missed it before
A number of platforms had been using the distro default feature before
it was moved to Kconfig but did not enable the new Kconfig option when
it was enabled. This caused a regression in terms of features and this
introduces breakage when more things move to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 29 Nov 2016 14:14:56 +0000 (09:14 -0500)]
cmd: Convert CMD_BOOTMENU
Also convert MENU while we're in here.
Signed-off-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Tue, 29 Nov 2016 22:33:26 +0000 (16:33 -0600)]
board: ti: am57xx: add FIT image TEE processing
Populate the corresponding TEE image processing call to be
performed during FIT loadable processing.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>