Guilherme Gallo [Mon, 15 Aug 2022 20:07:21 +0000 (17:07 -0300)]
ci/bin: Remove whitespace from token files
There was a security problem with some `gitlab_gql.py` scenarios because
of `\r` and `\n` in the token file, which interrupted the requests for
Gitlab endpoints.
Stripping the token file after reading the file content solves the
problem.
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>
Guilherme Gallo [Mon, 15 Aug 2022 19:18:53 +0000 (16:18 -0300)]
ci/bin: Fix requirements.txt
Add missing aiohttp and PyYAML packages
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>
Alyssa Rosenzweig [Sun, 25 Sep 2022 00:57:31 +0000 (20:57 -0400)]
agx: Reserve live-in regs at the start of block
...Rather than reserving the union of the registers live-out of the
predecessors. This avoids reserving registers that are killed along a
control flow edge (where the predecessor has another successor that does
use the register).
glmark2 subset of shaderdb:
total instructions in shared programs: 6442 -> 6440 (-0.03%)
instructions in affected programs: 42 -> 40 (-4.76%)
helped: 1
HURT: 0
total bytes in shared programs: 42186 -> 42174 (-0.03%)
bytes in affected programs: 270 -> 258 (-4.44%)
helped: 1
HURT: 0
total halfregs in shared programs: 1769 -> 1757 (-0.68%)
halfregs in affected programs: 75 -> 63 (-16.00%)
helped: 3
HURT: 0
helped stats (abs) min: 4.0 max: 4.0 x̄: 4.00 x̃: 4
helped stats (rel) min: 16.00% max: 16.00% x̄: 16.00% x̃: 16.00%
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Sat, 24 Sep 2022 23:13:00 +0000 (19:13 -0400)]
agx: Pass in max regs as a paramter to RA
This will allow us to restrict max regs later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Sat, 24 Sep 2022 04:15:55 +0000 (00:15 -0400)]
agx: Introduce ra_ctx data structure
We have more parameters to pass, this will get unwieldly otherwise.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Sat, 24 Sep 2022 04:04:21 +0000 (00:04 -0400)]
agx: Write to r0l with a "nesting" instruction
This avoids modeling the r0l register explicitly in the IR, which would
complicate RA for little benefit at this stage. Do the simplest thing
that could possibly work in SSA.
glmark2 subset.
total instructions in shared programs: 6442 -> 6442 (0.00%)
instructions in affected programs: 701 -> 701 (0.00%)
helped: 4
HURT: 5
helped stats (abs) min: 1.0 max: 3.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 1.46% max: 7.69% x̄: 4.03% x̃: 3.48%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.60 x̃: 1
HURT stats (rel) min: 0.81% max: 7.41% x̄: 2.67% x̃: 1.14%
95% mean confidence interval for instructions value: -1.58 1.58
95% mean confidence interval for instructions %-change: -3.70% 3.08%
Inconclusive result (value mean confidence interval includes 0).
total bytes in shared programs: 42196 -> 42186 (-0.02%)
bytes in affected programs: 7768 -> 7758 (-0.13%)
helped: 8
HURT: 5
helped stats (abs) min: 2.0 max: 18.0 x̄: 7.25 x̃: 4
helped stats (rel) min: 0.13% max: 7.26% x̄: 2.02% x̃: 0.97%
HURT stats (abs) min: 6.0 max: 18.0 x̄: 9.60 x̃: 6
HURT stats (rel) min: 0.82% max: 6.32% x̄: 2.37% x̃: 1.02%
95% mean confidence interval for bytes value: -7.02 5.48
95% mean confidence interval for bytes %-change: -2.30% 1.63%
Inconclusive result (value mean confidence interval includes 0).
total halfregs in shared programs: 1926 -> 1769 (-8.15%)
halfregs in affected programs: 1395 -> 1238 (-11.25%)
helped: 71
HURT: 0
helped stats (abs) min: 1.0 max: 10.0 x̄: 2.21 x̃: 2
helped stats (rel) min: 1.92% max: 52.63% x̄: 15.33% x̃: 11.76%
95% mean confidence interval for halfregs value: -2.69 -1.73
95% mean confidence interval for halfregs %-change: -17.98% -12.68%
Halfregs are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 21:27:43 +0000 (17:27 -0400)]
agx: Preload vertex/instance ID only at start
This means we don't reserve the registers, which improves RA
considerably. Using a special preload psuedo-op instead of a regular
move allows us to constrain semantics and gaurantee coalescing.
shader-db on glmark2 subset:
total instructions in shared programs: 6448 -> 6442 (-0.09%)
instructions in affected programs: 230 -> 224 (-2.61%)
helped: 4
HURT: 0
total bytes in shared programs: 42232 -> 42196 (-0.09%)
bytes in affected programs: 1530 -> 1494 (-2.35%)
helped: 4
HURT: 0
total halfregs in shared programs: 2291 -> 1926 (-15.93%)
halfregs in affected programs: 2185 -> 1820 (-16.70%)
helped: 75
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Sat, 24 Sep 2022 03:15:10 +0000 (23:15 -0400)]
agx: Print agx_dim appropriately
Easier to read, and gets us closer to proper disasm in Mesa.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 20:40:39 +0000 (16:40 -0400)]
agx: Print instructions as "dest = src"
This makes the dataflow easier to read, especially with splits and
collects (which take variable numbers of sources/destinations).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 20:35:31 +0000 (16:35 -0400)]
agx: Emit trap at pack-time, not during isel
This makes the shaderdb stats make more sense.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 02:35:46 +0000 (22:35 -0400)]
agx: Rename "combine" to "collect"
For consistency with ir3 and bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 02:35:44 +0000 (22:35 -0400)]
agx: Dynamically size split instruction
This is more flexible.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 02:35:43 +0000 (22:35 -0400)]
agx: Switch to dynamic allocation of srcs/dests
So we can handle parallel copies later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 02:35:41 +0000 (22:35 -0400)]
agx: Improve printing of immediate sources
For floats, decode the float. Regardless, the size speciifer is
redundant.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 02:35:39 +0000 (22:35 -0400)]
agx: Don't prefix pseudo-ops
It's not really buying us anything and it clutters the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Fri, 23 Sep 2022 02:35:36 +0000 (22:35 -0400)]
agx: Emit smaller combines for nir_op_vec2/3
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Thu, 22 Sep 2022 03:43:48 +0000 (23:43 -0400)]
agx: Set PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
Avoids spilling in t-rex.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig [Thu, 22 Sep 2022 03:23:14 +0000 (23:23 -0400)]
agx: Add iterators for phi/non-phi instructions
We know that phi nodes are always at the start (this is asserted in
agx_validate and a fundamental invariant of SSA form). That means we can
cheaply iterate all n phi nodes forward (or n non-phi nodes backwards)
in O(n) time. We already open code this idiom in a few places, use
common iterators instead so we don't need to justify in random places.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Mike Blumenkrantz [Thu, 13 Oct 2022 20:35:22 +0000 (16:35 -0400)]
zink: disable fbfetch when flushing clears
this ensures there's no weird perf happening, avoids using renderpass
instead of dynamic rendering, and avoids hitting an assert from broken
framebuffer construction
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
Mike Blumenkrantz [Thu, 13 Oct 2022 20:29:27 +0000 (16:29 -0400)]
zink: unset rp_changed after initializing renderpass attachments
if fbfetch is setup here, it will flag rp_changed
this is already inside renderpass setup, however, so just unset it
to avoid erroneously trigering the assert
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
Mike Blumenkrantz [Wed, 12 Oct 2022 17:42:58 +0000 (13:42 -0400)]
zink: clamp line_stipple_factor to 1 if stipple is disabled
0 is technically an illegal value even though it won't be read in this case
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
Mike Blumenkrantz [Thu, 13 Oct 2022 17:51:43 +0000 (13:51 -0400)]
zink: don't add other usage bits for transient images
this is illegal
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
Mike Blumenkrantz [Thu, 13 Oct 2022 11:58:10 +0000 (07:58 -0400)]
zink: check core feature for pipeline cache control
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
Emma Anholt [Wed, 12 Oct 2022 22:25:41 +0000 (15:25 -0700)]
zink: Fix dummy CB path decision for VK_EXT_cwe presence.
We have to do the dummy workaround when we *don't* have the ext. This was
apparently a mis-sedding.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19057>
Karol Herbst [Sun, 2 Oct 2022 11:54:24 +0000 (13:54 +0200)]
rusticl/mem: propper CL_MEM_ALLOC_HOST_PTR support
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Karol Herbst [Sun, 25 Sep 2022 17:12:34 +0000 (19:12 +0200)]
lp: claim being UMA
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Karol Herbst [Fri, 23 Sep 2022 18:15:16 +0000 (20:15 +0200)]
rusticl/mem: rewrite the (un)mapping code
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Karol Herbst [Fri, 23 Sep 2022 17:46:14 +0000 (19:46 +0200)]
rusticl: add helper ctx wrapper for coherent and direct mapping
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Karol Herbst [Fri, 23 Sep 2022 17:58:24 +0000 (19:58 +0200)]
rusticl: rework resource mappings a little
The _async variants will be removed later.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Karol Herbst [Fri, 23 Sep 2022 17:44:37 +0000 (19:44 +0200)]
rusticl/mesa: add bx() method to PipeTransfer
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Karol Herbst [Thu, 22 Sep 2022 13:05:14 +0000 (15:05 +0200)]
rusticl: add support for coherent resources
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
Timothy Arceri [Thu, 13 Oct 2022 03:17:37 +0000 (14:17 +1100)]
glthread: fix matrix stack depth tracking
Dont bump the depth if the application attempts to overflow or
underflow the stack.
Fixes:
6febe2b880e7 ("glthread: track all matrix stack depths")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19059>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:17:17 +0000 (21:17 -0400)]
asahi: Remove no-direct-packing
It's weird.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:16:35 +0000 (21:16 -0400)]
asahi: Use a header more like Intel's GenXML
We're trying to converge on a common schema.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:13:11 +0000 (21:13 -0400)]
asahi,panfrost: Remove exact attribute
Not used, although in the future it might be...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:10:24 +0000 (21:10 -0400)]
panfrost,asahi: Remove unused function
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:07:18 +0000 (21:07 -0400)]
panfrost,asahi: Remove unused prepare macro
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:04:11 +0000 (21:04 -0400)]
asahi/genxml: Defeature uint/float
Unused, relic from panfrost and not in upstream genxml.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Sat, 1 Oct 2022 01:03:02 +0000 (21:03 -0400)]
asahi: Eliminate "Pixel Format" type from GenXML
This is leaky and hurts compatibility with upstream GenXML. Just use the
actual hardware fields.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
Alyssa Rosenzweig [Mon, 19 Sep 2022 01:37:07 +0000 (21:37 -0400)]
nir/lower_system_values: Fix cs_local_index_to_id with variable workgroups
In that case we need to use the sysval. That sysval can be optimized anyway in
the nonvariable case. Fixes test_basic.get_linear_ids on panfrost.
Fixes:
998d84fca56 ("nir/lower_system_values: Support lowering more intrinsics")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18662>
Kenneth Graunke [Thu, 4 Aug 2022 09:06:52 +0000 (02:06 -0700)]
intel/compiler: Vectorize gl_TessLevelInner/Outer[] writes [v2]
Setting the NIR options takes care of iris thanks to the common st/mesa
linking code, and updating brw_nir_link_shaders should handle anv.
The main effort here is updating remap_tess_levels, which needs to
handle vector stores, writemasking, and swizzling. Unfortunately,
we also need to continue handling the existing single-component
access because it's used for TES inputs, which we don't vectorize.
We could try to vectorize TES inputs too, but they're all pushed
anyway, so it wouldn't buy us much other than deleting this code.
Also, we do have opt_combine_stores, but not one for loads.
One limitation of using nir_vectorize_tess_levels is that it works
on variables, and so isn't able to combine outer/inner writes that
happen to live in the same vec4 slot (for triangle domains). That
said, it's still better than before.
For writes, we allow the intrinsics to supply up to the full size
of the variable (vec4 for outer, vec2 for inner) even if the domain
only requires a subset of those components (i.e. triangles needs 3).
shader-db results on Icelake:
total instructions in shared programs:
19600314 ->
19597528 (-0.01%)
instructions in affected programs: 65338 -> 62552 (-4.26%)
helped: 271 / HURT: 0
helped stats (abs) min: 6 max: 24 x̄: 10.28 x̃: 12
helped stats (rel) min: 1.30% max: 18.18% x̄: 5.80% x̃: 7.59%
95% mean confidence interval for instructions value: -10.71 -9.85
95% mean confidence interval for instructions %-change: -6.17% -5.43%
Instructions are helped.
total cycles in shared programs:
851842332 ->
851808165 (<.01%)
cycles in affected programs: 618577 -> 584410 (-5.52%)
helped: 271 / HURT: 0
helped stats (abs) min: 64 max: 540 x̄: 126.08 x̃: 111
helped stats (rel) min: 2.57% max: 37.97% x̄: 6.12% x̃: 5.06%
95% mean confidence interval for cycles value: -135.35 -116.80
95% mean confidence interval for cycles %-change: -6.67% -5.57%
Cycles are helped.
total sends in shared programs: 1025238 -> 1024308 (-0.09%)
sends in affected programs: 6454 -> 5524 (-14.41%)
helped: 271 / HURT: 0
helped stats (abs) min: 2 max: 8 x̄: 3.43 x̃: 4
helped stats (rel) min: 5.71% max: 25.00% x̄: 14.98% x̃: 17.39%
95% mean confidence interval for sends value: -3.57 -3.29
95% mean confidence interval for sends %-change: -15.42% -14.54%
Sends are helped.
According to Felix DeGrood, this results in a 10% improvement in
the draw call time for certain draw calls from Strange Brigade.
v2: Fix assertions about number of components and add more of them.
Combine the quads and triangles handling as it's nearly identical.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19061>
semjon00 [Tue, 4 Oct 2022 08:29:16 +0000 (11:29 +0300)]
hasvk: force inline more pipe flush functions
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
semjon00 [Tue, 4 Oct 2022 08:27:56 +0000 (11:27 +0300)]
hasvk: combine flushes in Draw/DrawIndexed/DrawIndirectByteCountEXT
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
semjon00 [Tue, 4 Oct 2022 07:59:50 +0000 (10:59 +0300)]
hasvk: don't export gfx state flushing helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
semjon00 [Tue, 4 Oct 2022 07:31:32 +0000 (10:31 +0300)]
hasvk: don't export flush_compute_state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
Yonggang Luo [Mon, 5 Sep 2022 17:02:29 +0000 (01:02 +0800)]
util: Implement atomic operations consistently across compilers and testing for it
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18795>
Yonggang Luo [Sat, 3 Sep 2022 09:32:28 +0000 (17:32 +0800)]
util: Remove the include of windows.h when compiling with MSVC
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7345
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18795>
Karol Herbst [Wed, 12 Oct 2022 21:43:22 +0000 (23:43 +0200)]
rusticl/kernel: preserve fp16 denorms to fix vload/vstore_half
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19041>
Yiwei Zhang [Thu, 6 Oct 2022 22:43:09 +0000 (22:43 +0000)]
venus: avoid accessing local var in VN_ADD_EXT_TO_PNEXT_OF
This boring refactor:
- makes it consistent for extension name alias
- shortens the line a bit to not further regress line width
- applies macro when possible to be consistent
- removes some redundant empty lines
v2: rebase
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18993>
Mike Blumenkrantz [Mon, 26 Sep 2022 13:38:44 +0000 (09:38 -0400)]
lavapipe: store compiler options to physical device
this minimizes noise in gallium trace
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18867>
Mike Blumenkrantz [Wed, 12 Oct 2022 21:35:03 +0000 (17:35 -0400)]
zink: prevent ballooning of view object memory
if a resource is in use every frame and never goes idle, it becomes
impossible to execute pruning, as there is no tracking for when views
are no longer in use
to avoid eventually ooming in this scenario, add some data to zink_resource_object
which can effectively "queue" pruning of these views if ballooning is
detected at a time when the views are guaranteed to be safe to delete
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19056>
Mike Blumenkrantz [Wed, 12 Oct 2022 19:03:55 +0000 (15:03 -0400)]
zink: delete view objects when unsetting resource usage in batch reset
if the resource has no usage, it's guaranteed to be idle, which means view
objects can be pruned to avoid memory ballooning
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19056>
Mike Blumenkrantz [Wed, 12 Oct 2022 14:48:14 +0000 (10:48 -0400)]
zink: rework/improve descriptor pool overflow handling on batch reset
the existing model for descriptor pools works thusly:
* allocate pool
* when possible, reuse existing pool from overflow array
* when pool is full, append to overflow array
* on batch reset, cycle the overflow arrays to enable reuse
the problem with this is it uses two separate arrays for overflow, and these arrays
are cycled but never consolidated, leading to wasted memory allocations for whichever
array is not currently being recycled
to resolve this, make the following changes to batch resets:
* set the recycle index to whichever overflow array is smaller
* copy the elements from the smaller array to the larger array (consolidate)
* set the number of elements in the smaller array to 0
this leads to always appending to an empty array while the array containing all the
"free" pools is always the one that's available for recycled use
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19053>
Mike Blumenkrantz [Wed, 12 Oct 2022 15:51:14 +0000 (11:51 -0400)]
zink: fix pool overflow handling on batch reset
this mechanism worked off the previous iteration of descriptor updating,
in which pools were stored in a set to the batch state and could be iterated
normally
now, however, they're stored as a sparse array, and so the dynarray util for getting
the number of elements cannot be used
instead, use the calculated size for the array like every other accessor for
the pools to ensure correct indexing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19053>
Mike Blumenkrantz [Wed, 12 Oct 2022 14:45:07 +0000 (10:45 -0400)]
zink: handle oom better during descriptor updating
in the case where a new descriptor pool cannot be allocated naturally:
* iterate free batch states and try to free up memory
* iterate in-use batch states and try to free up memory
* ???
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19053>
Mike Blumenkrantz [Wed, 12 Oct 2022 14:44:44 +0000 (10:44 -0400)]
zink: move descriptor function up in file
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19053>
Chad Versace [Wed, 12 Oct 2022 04:09:19 +0000 (21:09 -0700)]
venus: Enable Vulkan 1.3
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19046>
Chad Versace [Wed, 12 Oct 2022 02:01:13 +0000 (19:01 -0700)]
venus: Enable VK_KHR_synchronization2
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19046>
Chad Versace [Wed, 12 Oct 2022 03:27:11 +0000 (20:27 -0700)]
venus: Refactor vn_command_buffer_builder temp storage
Easy refactor. Change the storage type from `VkImageMemoryBarrier *` to
`void *`. Prepares for VK_KHR_synchronization2.
The patch series is cleaner with this refactor. I promise.
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19046>
Chad Versace [Wed, 12 Oct 2022 02:00:46 +0000 (19:00 -0700)]
venus: Add vn_queue_wait_idle_before_present()
Trivial refactor.
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19046>
Chad Versace [Wed, 12 Oct 2022 01:58:19 +0000 (18:58 -0700)]
venus: Change signature of vn_get_fence_feedback_cmd
Trivial refactor.
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19046>
Chad Versace [Wed, 12 Oct 2022 02:05:25 +0000 (19:05 -0700)]
venus/queue: Rename some local vars
Reduces noise in following patches.
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19046>
Simon Zeni [Wed, 28 Sep 2022 10:25:11 +0000 (06:25 -0400)]
meson: remove unused EGL_NO_X11 definition
Last EGL header update changed the logic for the Xlib header inclusion. Now
the caller has to specify USE_X11 if they want the Xlib definitions.
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18848>
Simon Zeni [Wed, 28 Sep 2022 10:23:01 +0000 (06:23 -0400)]
EGL: sync headers with Khronos
Since [1], EGL removed the inclusion of the Xlib headers by default.
The logic is now reversed, and the call has to define USE_X11 to include the
Xlib headers instead of EGL_NO_X11_HEADERS to prevent the inclusion.
[1]: https://github.com/KhronosGroup/EGL-Registry/pull/130/commits/
3670d645f4a26a0a9e87e7f3a8608e7cc1d53b5b
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18848>
Simon Zeni [Fri, 30 Sep 2022 10:11:07 +0000 (06:11 -0400)]
egl: set API symbols public
With the latest header update from Khronos, KHRONOS_APICALL (which is then
defined as EGLAPI) is empty, preventing the API symbols to be visible.
This commit adds `PUBLIC` to all the symbols from the EGL API that needs to be
visible.
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18848>
Simon Zeni [Wed, 28 Sep 2022 10:15:26 +0000 (06:15 -0400)]
egl: fix Xlib include in egldisplay.h
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18848>
Brian Paul [Tue, 11 Oct 2022 17:51:57 +0000 (11:51 -0600)]
draw: fix base vertex bug
Move the assignment of draw->start_index into the num_draws loop
in draw_pt_arrays() so that it's updated for each primitive we're
drawing. Previously, it was only set once to the 0th primitive's
start index.
This fixes incorrect gl_BaseVertex values when using
vkCmdDrawMultiEXT() with more than one VkMultiDrawInfoEXT item.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19039>
Brian Paul [Mon, 10 Oct 2022 20:13:10 +0000 (14:13 -0600)]
draw: fix vertex id offset bug
The vertex_id_offset value needs to be used both for the elt and
linear cases. As it was, if a long primitive was split, the vertex id
seen in the VS was also getting to reset to zero for each batch of the
split prim's vertices.
This fixes at least five VMware test cases (dx11-dxsdk-FluidCS11,
dx11-amd-TressFX-v1.0, dx10-win7-dxsdk-samples-nbodygravity,
dx10-win7-dxsdk-samples-gpuboids, dx10-wide-points).
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19039>
Dylan Baker [Wed, 12 Oct 2022 17:18:38 +0000 (10:18 -0700)]
intel/genxml: use Path.replace instead of unlink and rename
Suggested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Mon, 3 Oct 2022 17:32:37 +0000 (10:32 -0700)]
intel/genxml: use a main() function
So we have less stuff in the global namespace
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Mon, 3 Oct 2022 17:31:58 +0000 (10:31 -0700)]
intel/genxml: split the processing code up
Instead of crewating output or validating in the process code, just
process, then let main handle the rest
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Mon, 3 Oct 2022 17:45:47 +0000 (10:45 -0700)]
intel/genxml: reprocess xml with elementree output
This makes two relatively small changes, first it addes the encoding to
the xml delcaration, and switches the quote style. Second, it changes
the final newline. These seemed minor enough to not warrent patches to
make the old wrter do the same thing as the new writer.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Mon, 3 Oct 2022 17:22:20 +0000 (10:22 -0700)]
intel/genxml: use ElementTree.write and .indent
This removes a bunch of hand-written code, and allows for fewer corner
cases. The resulting code has some minor differences (no empty newlines
and the encoding is declared in the xml declaration)
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Tue, 4 Oct 2022 17:14:21 +0000 (10:14 -0700)]
intel/genxml: re-process with extra whitespace removed
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Mon, 3 Oct 2022 17:38:02 +0000 (10:38 -0700)]
intel/genxml: remove newlines between xml islands
When we move to using etree to print this it won't have them, so this
minimizes the diff further.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Tue, 4 Oct 2022 17:13:47 +0000 (10:13 -0700)]
intel/genxml: re-process with space before `/>`
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Dylan Baker [Mon, 3 Oct 2022 17:49:09 +0000 (10:49 -0700)]
intel/genxml: write a space before the '/>` closing tag
ElementTree.write will do this, and we want to minimize the diff when we
switch from our own writer to the builtin one.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
Ruijing Dong [Thu, 6 Oct 2022 20:45:58 +0000 (16:45 -0400)]
radeonsi/vcn: enable multi-slice encoding
- enable h264 multiple slice encoding
- enable hevc multiple slice encoding
- enable hevc block size config options.
- enable amp, strong_intra_smmothing,
constrained_intra_pred and deblocking filter
disable config options for hevc encoding.
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18992>
Ruijing Dong [Thu, 6 Oct 2022 20:37:47 +0000 (16:37 -0400)]
radeonsi/vcn: enable dbk in avc encoding
enable deblocking filter in avc encoder.
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18992>
Ruijing Dong [Thu, 6 Oct 2022 20:33:36 +0000 (16:33 -0400)]
frontends/va: add h264 dbk enc parameters
Obtain va h264 dbk enc parameters.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18992>
Ruijing Dong [Thu, 6 Oct 2022 20:26:56 +0000 (16:26 -0400)]
gallium/pipe/video: add data struct for dbk in avc encoding.
add dbk data structure for preparing enabling
avc deblocking filter.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18992>
Bas Nieuwenhuizen [Fri, 8 Oct 2021 00:11:19 +0000 (02:11 +0200)]
radv: Rework modification detection of the meta cache.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19047>
Bas Nieuwenhuizen [Thu, 7 Oct 2021 22:39:17 +0000 (00:39 +0200)]
radv: Use a VkPipelineCache handle for meta shaders.
Prep work for using the common vk caches.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19047>
Bas Nieuwenhuizen [Fri, 8 Oct 2021 00:03:06 +0000 (02:03 +0200)]
radv: Constify entry_size.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19047>
Samuel Pitoiset [Tue, 11 Oct 2022 09:06:05 +0000 (11:06 +0200)]
radv: use SHA1_DIGEST_LENGTH in the pipeline cache
Instead of a magic value.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19047>
Samuel Pitoiset [Tue, 11 Oct 2022 10:27:20 +0000 (12:27 +0200)]
radv: move the disk cache to the vk_physical_device struct
To be able to use it from the common pipeline cache implementation.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19047>
Konstantin Seurer [Sun, 9 Oct 2022 12:46:31 +0000 (14:46 +0200)]
radv: Remove create_accel_build_shader
Unused since every kernel is written in GLSL now.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19006>
Mike Blumenkrantz [Wed, 12 Oct 2022 01:53:49 +0000 (21:53 -0400)]
zink: handle global and scratch vars
also delete cs pushconst since that was for clover and I don't care anymore
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19044>
Mike Blumenkrantz [Wed, 12 Oct 2022 01:55:16 +0000 (21:55 -0400)]
zink: add some bda handling
will be useful in the near future
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19044>
Mike Blumenkrantz [Tue, 11 Oct 2022 20:24:51 +0000 (16:24 -0400)]
zink: add a safety assert in descriptor updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19038>
Mike Blumenkrantz [Tue, 11 Oct 2022 20:34:27 +0000 (16:34 -0400)]
zink: move descriptor layout/pool stuff to screen object
this already has locks for async gfx precompiles, but compute shaders
can be compiled on one context and bound on another, which means
all the descriptor stuff they allocate has to be portable:
specifically the pool key ids MUST match across contexts
this is trivially achieved by making pool keys into screen objects
fixes #7434
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19038>
Dylan Baker [Tue, 11 Oct 2022 20:49:07 +0000 (13:49 -0700)]
docs: update calendar and link releases notes for 22.2.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19040>
Dylan Baker [Tue, 11 Oct 2022 19:09:25 +0000 (12:09 -0700)]
docs: Add sha256 sum for 22.2.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19040>
Dylan Baker [Tue, 11 Oct 2022 18:53:31 +0000 (11:53 -0700)]
docs: add release notes for 22.2.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19040>
SoroushIMG [Fri, 30 Sep 2022 15:08:27 +0000 (16:08 +0100)]
zink: fix isNan mismatch between NIR and SPIR-V
SPIR-V and Vulkan allow implementations to optimize
float ops assuming inputs are not NaN unless SignedZeroInfNanPreserve
execution mode is enabled.
This means isnan which is turned to nir_op_fneu(a,a) and then emitted
as SpvOpFUnordNotEqual could potentially be optimised to a const 0.
isnan is special in this approach and therefore recognise this pattern,
and emit SpvOpIsNan instead of enabling SignedZeroInfNanPreserve which
will hurt performace of some vulkan drivers.
Fixes dEQP-GL45-ES31.functional.shaders.builtin_functions.common.isnan.*
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18910>
SoroushIMG [Thu, 1 Sep 2022 18:40:16 +0000 (19:40 +0100)]
zink: stop enabling minmax filtering when not supported
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18910>
SoroushIMG [Tue, 19 Jul 2022 12:25:02 +0000 (13:25 +0100)]
zink: fix invalid Offset set for variables which do not need an offset
Offset decoration in spirv is unsigned and it does not have a notion of an invalid offset.
Unlike NIR which set -1 for invlaid offset. This translates to invalid spirv being produced.
Instead, just don't emit an Offset decoration.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18910>
Konstantin Seurer [Mon, 10 Oct 2022 14:07:08 +0000 (16:07 +0200)]
radv/rra: Calculate bvh size requirements recursively
Gets rid of the assumption, that every internal node has the same size.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19017>
Konstantin Seurer [Sun, 9 Oct 2022 20:00:17 +0000 (22:00 +0200)]
radv/rra: Handle box16 nodes
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19017>
Konstantin Seurer [Sun, 9 Oct 2022 16:30:42 +0000 (18:30 +0200)]
radv: Use half floats for box16 coords
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19017>