agx: Defeature fsub

All has_fsub does is fuse fsubs (they're unfused otherwise), no point doing that
if we're going to just going to lower.

shader-db is mostly noise.

total instructions in shared programs: 1487217 -> 1487035 (-0.01%)
instructions in affected programs: 22658 -> 22476 (-0.80%)
helped: 85
HURT: 2
helped stats (abs) min: 1.0 max: 12.0 x̄: 2.19 x̃: 1
helped stats (rel) min: 0.38% max: 2.46% x̄: 0.87% x̃: 0.65%
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.58% max: 1.08% x̄: 0.83% x̃: 0.83%
95% mean confidence interval for instructions value: -2.51 -1.67
95% mean confidence interval for instructions %-change: -0.97% -0.70%
Instructions are helped.

total bytes in shared programs: 10189996 -> 10189288 (<.01%)
bytes in affected programs: 158132 -> 157424 (-0.45%)
helped: 85
HURT: 2
helped stats (abs) min: 4.0 max: 48.0 x̄: 8.75 x̃: 4
helped stats (rel) min: 0.22% max: 1.44% x̄: 0.51% x̃: 0.38%
HURT stats (abs)   min: 6.0 max: 30.0 x̄: 18.00 x̃: 18
HURT stats (rel)   min: 0.90% max: 0.91% x̄: 0.91% x̃: 0.91%
95% mean confidence interval for bytes value: -9.98 -6.30
95% mean confidence interval for bytes %-change: -0.56% -0.39%
Bytes are helped.

total halfregs in shared programs: 462536 -> 462556 (<.01%)
halfregs in affected programs: 131 -> 151 (15.27%)
helped: 1
HURT: 4
helped stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 28.57% max: 28.57% x̄: 28.57% x̃: 28.57%
HURT stats (abs)   min: 4.0 max: 8.0 x̄: 5.50 x̃: 5
HURT stats (rel)   min: 12.77% max: 36.36% x̄: 25.01% x̃: 25.45%
95% mean confidence interval for halfregs value: -0.65 8.65
95% mean confidence interval for halfregs %-change: -18.64% 47.23%
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Use u_default_get_sample_position

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

agx: Remove bogus assert

I->mask isn't even valid for iter instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Compress more texture targets

They should already work, we just need it enabled. The comment here claimed
(incorrectly) that there is no hardware support for linear 2D arrays. In fact,
there is support, it's just not advertised in the public Metal API. With some
awful tricks, I managed to reverse-engineer the hardware interface and hooked it
up, so we can take advantage of it now.

In fact, we can stop checking the target explicitly at all. The only case where
we can't compress is 1D/buffer textures, which are necessarily less than 16
height so will be dropped in the next check.

When I originally wrote this cuhange, dolphin's MeltyMoltenGalaxy trace with
specialized shaders at 4K was helped from 28fps to 43fps, which is massive :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Use 2D array staging resources for cube/3D

Staging resources need to be linear for efficient CPU side mapping. This is a
problem for access to 3D and cube textures, since we don't have linear 3D
textures or linear cube textures. But we do have linear 2D array textures, which
can be reshaped to the same effect. So use a 2D array staging resource even for
3D textures and cube maps.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Explicitly ban MSAA, compression with linear

These get asserted later. It doesn't really matter but this makes our queries
more accurate. This came up when experimenting a debug option that forces linear
textures to be used as much as possible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

agx: Handle linear 2D array textureSize()

We handle linear 2D arrays internally for blit shaders, so we need textureSize
to work for these. That requires some special casing, because there's a line
stride where the layer count would otherwise be. But it's not too bad.

Fixes
dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray_*
when forcing linear textures.

Since we clamp array access to the maximum layer, we need textureSize() to work
for even the most basic array texturing. So this should fix blits from linear 2D
arrays as well, which finally unlocks support for compressed arrays/cubes/3D
textures.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

agx/lower_zs_emit: Fix progress returning

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

agx: Fix abs/neg propagation into fcmpsel

The first two sources are floats, the latter two sources and destination (and
hence the opcode) are not. Reflect that when packing and optimizing. Noticed
while debugging a silly dEQP test.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

agx: Handle splits of uniforms

This is straightforward, and can happen with certain u2u16 patterns.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Track write to separate stencil

From the commit message of 94f7c011d6e ("v3d: Track write reference to the
separate stencil buffer."), anholt says:

   Otherwise, a blit from separate stencil may fail to flush the job that
   initialized it, or new drawing could fail to flush a blit reading from
   stencil.

Fixes
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Identify XML for barycentric coordinates

Reading them from a fragment shader, not interpolating at custom ones.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Don't use depth/stencil staging blits

Our staging resources need to be LINEAR, however we don't support LINEAR with
DEPTH_STENCIL. The APIs don't actually require this, we just need to make sure
we don't generate internal staging blits to linear depth/stencil resources. For
uploading to compressed depth/stencil textures, we could use a depth/stencil
staging (since we can read from linear depth/stencil). However, for downloading
from compressed depth/stencil, we can't use a depth/stencil staging (since we
can't write linear depth/stencil). So, to handle both cases in a unified way,
just use colour blits for depth/stencil resources, using a compatible colour
format. This wouldn't be ok for an application to do itself, but within the
driver we know that it's safe, since there's no difference in memory between
depth/stencil and colour on AGX. In particular, Z16 is compressed exactly the
same as R16, Z8 as R8, and so on.

Fixes depth/stencil compression.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Minify width/height in create_surface

Otherwise framebuffer->width ends up being wrong with u_blitter, this is what
other drivers do. If we needed to render to depth/stencil with u_blitter, this
would cause us trouble.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Fix disk cache disable with AGX_MESA_DEBUG

We go to initialize the disk cache before we've compiled any shaders so
agx_compiler_debug is 0 at this point. Don't try to read it, instead go through
sa safe getter that will do the right thing.

Fixes: 5e9538c12e0 ("agx: isolate compiler debug flags")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Fix batch writer tracking for null batches

When an empty batch is submitted, nothing happens. However, this batch
may have taken over writer status for some BOs which still have a
pending submitted batch that hasn't finished yet. If we drop writer
status at this point, two bad things happen:

- We spuriously clear bo->writer_syncobj, which breaks syncing on
  post-facto BO exports
- We break agx_sync_writer(), since we no longer know about the old
  writer to properly block on it.

To fix this (hopefully rare) case, take advantage of bo->writer_syncobj
to find the currently submitted writer batch again, and revert the
writer to it. If this turns out to be common and a performance issue
iterating through submitted batches for each written BO, we could
implement it with two writer batch arrays instead, one for active
writers and one for submitted writers... but hopefully that isn't
necessary.

This splits the cleanup path in agx_batch_cleanup() depending on whether
the cleanup is for a reset or proper completion. Since this is only used
within agx_batch.c, drop the public prototype while we're at it.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Add batch state debugging

I've had to reimplement this more than once, let's just make a flag for
it.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Free low VA BOs correctly

These need the shader_base added to them. Fixes GEM_BIND errors after
usc_head provides VA without the VM_SHADER_START offset from returned
low VA.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Fix typo in debug/error message helper macro

The typo is in the !__GLIBC__ case and was observed while building on
Alpine.

Fixes: 0a132b06406d ("asahi: Add a helper macro for debug/error messages")
Reported-by: mps
Tested-by: mps
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Enable 2xMSAA (for deqp)

This also just works, let's enable it (still gated on deqp).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Broadcast Z for all components on texture fetch

Gallium expects this.

Related commit: 6cac9c748e

Co-authored-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

asahi: Identify ZS resolve bits (tentative)

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22891>

nir/lower_fp16_casts: Fix SSA dominance

Fixes: 01dfd65 ("nir: port fp16 casting code from dxil")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22804>

ci: uprev kernel to 6.3.1 with fixed patch for Adreno SMMU

Going from release candidate to stable kernel hopefully also improve
overall stability.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22873>

freedreno/a6xx+: Use template to handle a6xx vs a7xx differences

This doesn't enable support for a7xx yet, but uses the new register pack
builders for registers that differ between a7xx and a6xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22837>

freedreno/a6xx: Rework set_bin_size()

The open-coded flag param for "all the other bits" won't work once we
have register variants in play.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22837>

r600/sfn: fix cube to array lowering for LOD

Makes piglits related to texturequerylod and samplercubearray pass.

Fixes: 79ca456b4837 ("r600/sfn: rewrite NIR backend")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22883>

r600/sfn: Ass support for image_samples

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8971

Fixes: 79ca456b4837 ("r600/sfn: rewrite NIR backend")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22883>

docs/tgsi: use \ll and \gg for left and right shift

This renders a bit cleaner.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: fixup latex for TEX and TEX2

We need to excape the underscores for shadow_ref, as well as escape
non-math symbols.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: do not use math-block for non-latex

This block isn't valid latex, so let's just use a pseudocode-block like
we do elsewhere here.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: use math-notations for conditionals

These are math-blocks, which is supposed to use math-notation for
conditionals. So let's change it to math notation.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: wrap overly long lines

While we're at it, use some alignment so the equations still reads
reasonably.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: fixup bad latex

It's better to split these two equations in two than to try to write
extra text that needs lots of escaping. This fixes the LaTeX rendering
to be somewhat readable.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: fix bad latex

We need empty spaces here, otherwise LaTeX thinks it's one equation, and
puts it all back onto one line.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

docs/tgsi: fix up indent

There's a mixture of indent styles here, with either two or three
spaces. We have standardized on three spaces for .rst-files in the
editorconfig, so let's apply that.

While we're at it, make sure math-blocks are indented into their
opcode-block. While the result might look the same most of the time,
this matters when we have textual explaination following math-blocks,
like we have in a few caess. If we don't indent the math there, we
end up with having to unindent the text following the math-block for it
not to count as a part of the math block, which looks very confusing
when reading the source code.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21893>

dzn: fix pointer type mismatch

    ../src/microsoft/vulkan/dzn_image.c: In function ‘dzn_GetImageMemoryRequirements2’:
    ../src/microsoft/vulkan/dzn_image.c:918:91: error: passing argument 6 of ‘dzn_ID3D12Device12_GetResourceAllocationInfo3’ from incompatible pointer type [-Werror=incompatible-pointer-types]
      918 |                                                            &image->castable_format_count, &image->castable_formats,
          |                                                                                           ^~~~~~~~~~~~~~~~~~~~~~~~
          |                                                                                           |
          |                                                                                           DXGI_FORMAT **
    In file included from ../src/microsoft/vulkan/dzn_private.h:67,
                     from ../src/microsoft/vulkan/dzn_image.c:24:
    ../src/microsoft/vulkan/dzn_abi_helper.h:64:107: note: expected ‘const DXGI_FORMAT * const*’ but argument is of type ‘DXGI_FORMAT **’
       64 |                                               const UINT *num_castable_formats, const DXGI_FORMAT *const *castable_formats,
          |                                                                                 ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~
    cc1: some warnings being treated as errors
    ninja: build stopped: subcommand failed.

Fixes: 71dbb3120a9d0fb0de32 ("dzn: Use GetResourceAllocationInfo3 for castable formats")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22877>

ci/turnip: Drop the IUB bug fallout flakes.

They haven't been seen since my fix landed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>

ci/turnip: Drop an xfail from the full run for a recent fix.

Fixes: 2cbc24b9da01 ("turnip: fix buffer markers using wrong addresses")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>

ci/radv: Disable flaky heaven d3d9 trace.

10 flakes this month, starting with the noted job.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>

ci/radeonsi: Mark glx-make-current as flaky.

It no longer 100% crashes, but instead sometimes fails.

Fixes: 91b06ea8b254 ("Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>

intel/tools: decode ACTHD printed by newer kernels

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22874>

radeonsi/vcn: fix decoding bs buffer alignement issue.

reason:
  in some cases, bs buffer size could cause assertion,
  and some bitstreams of certain resolutions could
  not be decoded.

solution:
  to align the bs buffer to 128.

fixes: 4f1646d73fa8bac82ff2195f06a5f6011853f647

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22844>

zink: add ZINK_DEBUG=optimal_keys

it's otherwise very annoying to figure out why this may or may not be
available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>

zink: disable EXT_shader_object if !optimal_keys

this has the same requirements as GPL and then some

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>

zink: break out optimal key handling into separate function

this is growing to be much larger than the original conditional

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>

zink: move EXT_shader_object check to another place

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>

anv: increase instruction heap to 2Gb

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8917
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>

anv: make internal address space allocation more dynamic

We're about to manipulate these pools and dealing with the fix address
ranges is painful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>

anv: link anv_bo to its VMA heap

We want to add more heaps in the future and so not having to do
address checks to find out in what heap to release a BO is convinient.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>

anv: avoid hardcoding instruction VA constant in shaders

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>

anv: remove 48bit address space checks

All the supported platforms should have 36+ bits of virtual address
space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>

isl: fix layout for comparing surf and view properties

These asserts were checking isl_format_layout against itself, change
to compare surface format layout against view format layout.

Fixes: 628bfaf1c6f ("intel/isl: Add some sanity checks for compressed surfaces")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22790>

intel/fs: fix scheduling of HALT instructions

With the following test :

dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.no_out_of_bounds_load

There is a :

shader_start:
   ...                                 <- no control flow
   g0 = some_alu
   g1 = fbl
   g2 = broadcast g3, g1
   g4 = get_buffer_size g2
   ...                                 <- no control flow
   halt                                <- on some lanes
   g5 = send <surface>, g4

eliminate_find_live_channel will remove the fbl/broadcast because it
assumes lane0 is active at get_buffer_size :

shader_start:
   ...                                 <- no control flow
   g0 = some_alu
   g4 = get_buffer_size g0
   ...                                 <- no control flow
   halt                                <- on some lanes
   g5 = send <surface>, g4

But then the instruction scheduler will move the get_buffer_size after
the halt :

shader_start:
   ...                                 <- no control flow
   halt                                <- on some lanes
   g0 = some_alu
   g4 = get_buffer_size g0
   g5 = send <surface>, g4

get_buffer_size pulls the surface index from lane0 in g0 which could
have been turned off by the halt and we end up accessing an invalid
surface handle.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20765>

amd: Cleanup old GS intrinsics code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

ac/nir/ngg: Use sendmsg in NGG lowering.

There is no need to use alloc_vertices_and_primitives anymore,
because it will be compiled to sendmsg anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

ac/nir: Emit legacy GS DONE signal in NIR.

Legacy GS needs to emit a DONE signal at the end. Do this in NIR
instead of in the backends.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

ac/nir: Use sendmsg in legacy GS lowering.

Remove the GS intrinsics completely and emit the sendmsg here
instead of in the backend. This is done to simplify backend code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

ac/llvm: Clarify arguments of ac_build_sendmsg.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

amd: Move sendmsg defines to ac_shader_util.

Will be used by ac/nir legacy and NGG lowerings.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

amd: Add and implement gs_wave_id sysval.

Contains a global wave ID of legacy GS waves.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

amd: Add and implement sendmsg_amd intrinsic.

This intrinsic is going to be used for simplifying GS code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

aco: Disallow constant propagation on SOPP and fixed operands.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

aco/ra: create M0-affinities for s_sendmsg

v2 by Timur Kristóf:
Do not add the affinity for instructions that can't write m0
reliably, such as readlane-like instructions on GFX8.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>

intel/compiler: UNDEF SubgroupInvocation's register

This value takes a few instructions to create, involving expanding
V-immediates, adding 8 for SIMD16, and so on.  We can mark it UNDEF
so that it's clear that although these are partial writes, we are
actually defining the entire value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>

intel/compiler: UNDEF comparisons with smaller than 32-bit

Comparisons which produce 32-bit boolean results (0 or 0xFFFFFFFF)
but operate on 16-bit types would first generate a CMP instruction
with W or HF types, before expanding it out.  This CMP is a partial
write, which leads us to think the register may contain some prior
contents still.  When placed in a loop, this causes its live range
to extend beyond its real life time.

Mark the register with UNDEF first so that we know that no prior
contents exist and need to be preserved.

This affects:
flt32, fge32, feq32, fneu32, ilt32, ult32, ige32, uge32, ieq32, ine32

On one of Cyberpunk 2077's most complex compute shaders, this reduces
the maximum live registers from 696 to 537 (22.8%).  Together with the
next patch, Cyberpunk's spills and fills are cut by 10.23% and 9.19%,
respectively.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>

vulkan: Document vk_physical_device::supported_features

While we're here, move it to after supported extensions to stay
consistent with the vk_physical_device_init parameters.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Constantine Shablya <constantine.shablya@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22845>

zink: take location_frac into account in pv emulation

The pv mode emulation code was not taking into account the location_frac
of variables, they where beeing stored in a 1D array leading to
collisions.

Fixes: 5a4083349f3 ("zink: add provoking vertex mode lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22856>

nir: switch to a normal sampler for ARB program with not depth textures

It is undefined behavior when an ARB assembly or shadow2d GLSL func
uses SHADOW2D target with a texture in not depth format.
In this case AMD and NVIDIA automatically replaces SHADOW sampler
with a normal sampler and some games like Penumbra Overture which abuses
this UB works fine but breaks with mesa.

Replace the shadow sampler with a normal one here by recompiling
the ARB program variant

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>

drirc: add allow_sampled_tex_copy option

From OpenGL spec 8.6
"An INVALID_OPERATION error is generated if the object bound to
READ_FRAMEBUFFER_BINDING is framebuffer complete and its effective
value of SAMPLE_BUFFERS (see section 9.2.3.1) is one"

But some games might do this

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>

Uprev Piglit to 79a084c56b6dd79f7c3a97b57a72963121ebb1e6

https://gitlab.freedesktop.org/mesa/piglit/-/compare/355ad6bcb2cb3d9e030b7c6eef2b076b0dfb4d63...79a084c56b6dd79f7c3a97b57a72963121ebb1e6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22548>

pvr: Move heap initialisation out of pvr_winsys_helper.

This code will not be used by the new KMD, so it is being moved out of
this shared code area.

Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22826>

panvk: clear dangling pointers

Fixes:
```
[829/1646] Compiling C object src/panfrost/vulkan/libpanvk_v6.a.p/panvk_vX_meta_clear.c.o
In function 'panvk_meta_clear_zs_img',
    inlined from 'panvk_v6_CmdClearDepthStencilImage' at ../src/panfrost/vulkan/panvk_vX_meta_clear.c:457:7:
../src/panfrost/vulkan/panvk_vX_meta_clear.c:415:26: warning: storing the address of local variable 'view' in '((struct pan_fb_info *)((char *)commandBuffer + 144))[23].zs.view.zs' [-Wdangling-pointer=]
  415 |       fbinfo->zs.view.zs = &view;
      |       ~~~~~~~~~~~~~~~~~~~^~~~~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c: In function 'panvk_v6_CmdClearDepthStencilImage':
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'view' declared here
  393 |    struct pan_image_view view = {
      |                          ^~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'commandBuffer' declared here
[844/1646] Compiling C object src/panfrost/vulkan/libpanvk_v7.a.p/panvk_vX_meta_clear.c.o
In function 'panvk_meta_clear_zs_img',
    inlined from 'panvk_v7_CmdClearDepthStencilImage' at ../src/panfrost/vulkan/panvk_vX_meta_clear.c:457:7:
../src/panfrost/vulkan/panvk_vX_meta_clear.c:415:26: warning: storing the address of local variable 'view' in '((struct pan_fb_info *)((char *)commandBuffer + 144))[23].zs.view.zs' [-Wdangling-pointer=]
  415 |       fbinfo->zs.view.zs = &view;
      |       ~~~~~~~~~~~~~~~~~~~^~~~~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c: In function 'panvk_v7_CmdClearDepthStencilImage':
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'view' declared here
  393 |    struct pan_image_view view = {
      |                          ^~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'commandBuffer' declared here
```

Cc: mesa-stable
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22829>

anv: implement VK_KHR_ray_tracing_position_fetch

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>

intel/nir/rt: wire position fetch intrinsic

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>

intel/nir/rt: use a single load for instance leaf loading

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>

spirv/nir: wire ray interection triangle position fetch

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>

spirv: update to latest headers

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>

vulkan: bump headers to 1.3.249

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>

pvr: Reduce free list initial size when multiple devices are created

Will hopefully reduce the memory load when running dEQP.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22330>

pvr: Use vk_device's enabled features struct

Avoids duplicating the struct in pvr_device and fixes uninitialized
accesses when ppEnabledFeatures was NULL.

Noticed when running valgrind over dEQP.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22331>

pvr: Don't ralloc build context from compiler

rogue_compiler is allocated for each VkPhysicalDevice which means it can
be used from multiple threads when compiling. Allocating the build context
from this will lead to race conditions as ralloc is not thread safe.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22332>

panvk: port panvk_logi to vk_logi

Signed-off-by: Hui Ni <shuizhuyuanluo@126.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22772>

pvr: Adjust clear's region clip words

Co-Authored-By: : Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>

pvr: Fix incorrect PBE packmode for S8_UINT

Fixes:
dEQP-VK.pipeline.monolithic.stencil.format.d24_unorm_s8_uint.states
  .fail_keep.pass_keep.dfail_keep.comp_always

Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>

pvr: Don't advertise S8_UINT support

S8_UINT is not a requirement for Vulkan 1.0.

Revert "pvr: Add initial support for VK_FORMAT_S8_UINT".

This reverts commit 220356e0831bc870a189cf8d116a8b0ff6e1e500.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>

pvr: fix sync waiting while using pvrsrvkm

pvrsrvkm type sync objects can have a pending state where,
the fence is unsignaled but does not have a valid sync file
due to not yet being submitted to kernel.

The wait function therefore needs to handle these types of syncs
through a spin loop.

This was seen as crashes in dEQP-VK.synchronization.timeline_semaphore.*

Signed-off-by: SoroushIMG <soroush.kashani@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>

docs: fixup About Mesa3D.org link

This link is supposed to point to www.mesa3d.org, not docs.mesa3d.org.
Let's fix it up!

Fixes: 7da0482636a ("docs: add custom html theme")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22825>

llvmpipe: fixup refactor copypasta

I accidentally set this state based on the wrong state when refactoring,
whoops!

Fixes: a1846e39269 ("llvmpipe: merge all rasterizer-bind functions")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22832>

mesa/main: drop use_legacy_math_rules

Seems the only thing that really needs this is fpow(0, 0), which should
return NaN, but then gets multiplied with zero. Let's fix that by doing
a bcsel instead of fmul to select the result here. While we're at it,
get rid of the fabs for stop, which isn't needed.

This fixes a piglits failure for most (if not all?) drivers that doesn't
support legacy math rules.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22789>

r600: remove unused code

With the cleanup in 337dc7d76604e646f1a85615ab2d9d238427bf46 this code
became unused.

Fixes: 337dc7d76604 ("r600: remove TGSI code path")
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22743>

nir/lower_io_to_vector: initialize base

Prevent GCC warning:
```
[230/1401] Compiling C object src/compiler/nir/libnir.a.p/nir_lower_io_to_vector.c.o
In function 'get_flat_type',
    inlined from 'create_new_io_vars' at ../src/compiler/nir/nir_lower_io_to_vector.c:300:10:
../src/compiler/nir/nir_lower_io_to_vector.c:208:14: warning: 'base' may be used uninitialized [-Wmaybe-uninitialized]
  208 |       return glsl_array_type(glsl_vector_type(base, 4), slots, 0);
      |              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/compiler/nir/nir_lower_io_to_vector.c: In function 'create_new_io_vars':
../src/compiler/nir/nir_lower_io_to_vector.c:163:24: note: 'base' was declared here
  163 |    enum glsl_base_type base;
      |                        ^~~~
```

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8957

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22840>

dzn: Delete queue-level event waits

These are unneeded. Events can't be used to indefinitely stall work
like you can with a semaphore or timeline semaphore. The signals
still need to happen so that execution will modify the state that
can be polled from the CPU though.

Fixes dEQP-VK.synchronization.basic.event.single_submit_multi_command_buffer

Fixes: 04fa6c71 ("dzn: Batch command lists together")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22842>

dzn: Support separate depth/stencil resolves via blits

In theory, ResolveSubresourceRegion should be able to resolve just
the depth or just the stencil. In practice, WARP had bugs, which
means that was never tested, so just do it via blits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22836>

dzn: Support all available depth/stencil resolve modes

Fixes dEQP-VK.imageless_framebuffer.depth_stencil_resolve and
dEQP-VK.renderpass2.depth_stencil_resolve.misc.properties

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22836>

dzn: Augment blit resolve to support min/max/sample-zero modes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22836>

vulkan: write beta extensions into generator scripts.

Updated by: Hyunjun Ko <zzoon@igalia.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21806>

vulkan/cmd_queue: handle beta extensions.

Since this was moved to vulkan_core.h, we have to add the beta header
ourselves when required.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21806>

nir: add/update comments for gl_access_qualifier

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22769>

nir: rename ACCESS_STREAM_CACHE_POLICY -> ACCESS_NON_TEMPORAL and document

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22769>