platform/upstream/llvm.git
16 months ago[libc++] Refactor the selection of string's ABI in __config
Louis Dionne [Mon, 19 Jun 2023 16:58:51 +0000 (12:58 -0400)]
[libc++] Refactor the selection of string's ABI in __config

This doesn't change the selection, but it expands the conditions to
add comments and make it clearer what's happening. It also removes a
-Wundef instance when we checked __ARM_ARCH_7K__ >= 2 without checking
that it is defined in the first place.

Differential Revision: https://reviews.llvm.org/D153413

16 months ago[ARM] Repair check lines in sub-cmp-peephole.ll test. NFC
David Green [Wed, 21 Jun 2023 21:47:30 +0000 (22:47 +0100)]
[ARM] Repair check lines in sub-cmp-peephole.ll test. NFC

Commit ec77747fbdca901e0fded58f940dae62e0f6b726 regenerated the check lines
without being very careful about which lines were updated. This attempts to fix
them to make sure the V7 and V8 lines are emitted as needed.

16 months agoRevert "Revert "[LLD][ELF] Cortex-M Security Extensions (CMSE) Support""
Amilendra Kodithuwakku [Wed, 21 Jun 2023 20:40:41 +0000 (21:40 +0100)]
Revert "Revert "[LLD][ELF] Cortex-M Security Extensions (CMSE) Support""

This reverts commit a685ddf1d104b3ce9d53cf420521f5aaff429630.

This relands Arm CMSE support (D139092) and fixes the GCC build bot errors.

16 months ago[mlir][openacc] Update host_data data operands list name
Razvan Lupusoru [Wed, 21 Jun 2023 21:24:24 +0000 (14:24 -0700)]
[mlir][openacc] Update host_data data operands list name

For all other compute and data constructs, the data operands list
is named `dataClauseOperands`. Update `acc.host_data` to be
consistent with this naming.

Reviewed By: clementval

Differential Revision: https://reviews.llvm.org/D153425

16 months ago[mlir][sparse] rewrite arith::SelectOp to semiring operations to sparsify it.
Peiming Liu [Wed, 21 Jun 2023 04:16:40 +0000 (04:16 +0000)]
[mlir][sparse] rewrite arith::SelectOp to semiring operations to sparsify it.

Reviewed By: aartbik, K-Wu

Differential Revision: https://reviews.llvm.org/D153397

16 months ago[DFSAN] Add support for strncat
Tomasz Kuchta [Wed, 21 Jun 2023 21:18:05 +0000 (21:18 +0000)]
[DFSAN] Add support for strncat

This patch adds a support for the libc strncat() function in DFSAN

Reviewed by: browneee

Differential Revision: https://reviews.llvm.org/D152196

16 months ago[flang][openacc] Use acc.private and acc.firstprivate when lowering clauses
Valentin Clement [Wed, 21 Jun 2023 21:19:20 +0000 (14:19 -0700)]
[flang][openacc] Use acc.private and acc.firstprivate when lowering clauses

Lower private and firstprivate operands through their corresponding
data entry operation to support array section.

Depends on D152972

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D152974

16 months ago[mlir][openacc] Add acc.firstprivate operation as data entry operation
Valentin Clement [Wed, 21 Jun 2023 21:18:08 +0000 (14:18 -0700)]
[mlir][openacc] Add acc.firstprivate operation as data entry operation

acc.firstprivate operation will be used as data entry operation
for the firstprivate operands.

Depends on D152970

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D152972

16 months ago[mlir][openacc] Add acc.private operation as data entry operation
Valentin Clement [Wed, 21 Jun 2023 21:16:57 +0000 (14:16 -0700)]
[mlir][openacc] Add acc.private operation as data entry operation

acc.private operation will be used as data entry operation
for the private operands.

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D152970

16 months ago[lldb/test] Disable TestStackCoreScriptedProcess.py
Med Ismail Bennani [Wed, 21 Jun 2023 21:05:55 +0000 (14:05 -0700)]
[lldb/test] Disable TestStackCoreScriptedProcess.py

This patch disables TestStackCoreScriptedProcess.py since it times out
non deterministicly.

Signed-off-by: Med Ismail Bennani <ismail@bennani.ma>
16 months ago[test] Add test for null_pointer_is_valid and Inliner instsimplify interaction
Arthur Eubanks [Wed, 21 Jun 2023 15:31:42 +0000 (08:31 -0700)]
[test] Add test for null_pointer_is_valid and Inliner instsimplify interaction

As requested in D151254

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153435

16 months ago[NFC][sanitizer] Pass user region into OnMapSecondary
Vitaly Buka [Wed, 21 Jun 2023 20:50:42 +0000 (13:50 -0700)]
[NFC][sanitizer] Pass user region into OnMapSecondary

16 months ago[NFC][sanitizer] Add OnMapSecondary callback
Vitaly Buka [Wed, 21 Jun 2023 20:30:44 +0000 (13:30 -0700)]
[NFC][sanitizer] Add OnMapSecondary callback

Now it implemented as OnMap everywhere, but in follow up patches
we can optimize Asan handler.

16 months ago[PhaseOrdering] Add test showing mis-compile caused by 17fdaccccf.
Florian Hahn [Wed, 21 Jun 2023 20:15:13 +0000 (21:15 +0100)]
[PhaseOrdering] Add test showing mis-compile caused by 17fdaccccf.

The test shows a mis-compile where @test gets incorrectly simplified to
unreachable. The test case is reduced from a ThinLTO build of Clang,
with only the relevant pass sequence included.

16 months ago[NFC][sanitizer] Remove MapUnmapCallback from sanitizer_flat_map.h
Vitaly Buka [Wed, 21 Jun 2023 20:04:34 +0000 (13:04 -0700)]
[NFC][sanitizer] Remove MapUnmapCallback from sanitizer_flat_map.h

It's used by test only to test "test-only" code.

16 months agoEmit DW_LLE_base_address + DW_LLE_offset_pair for DWARF v5
Shubham Sandeep Rastogi [Wed, 14 Jun 2023 23:35:38 +0000 (16:35 -0700)]
Emit DW_LLE_base_address + DW_LLE_offset_pair for DWARF v5

This patch tries to reduce the size of the debug_loclist section by
replacing the DW_LLE_start_length opcodes currently emitted by dsymutil
in favor of using DW_LLE_base_address + DW_LLE_offset_pair instead.

The DW_LLE_start_length is one AddressSize followed by a ULEB per entry,
whereas, the DW_LLE_base_address + DW_LLE_offset_pair will use one
AddressSize for the base address, and then the DW_LLE_offset_pair is a
pair of ULEBs. This will be more efficient where a loclist fragment has
many entries.

Differential Revision: https://reviews.llvm.org/D153080

16 months ago[MBP] Enable duplicating return block to remove jump to return
Guozhi Wei [Wed, 21 Jun 2023 18:54:31 +0000 (18:54 +0000)]
[MBP] Enable duplicating return block to remove jump to return

Sometimes LLVM generates branch to return instruction, like PR63227.

It is because in function MachineBlockPlacement::canTailDuplicateUnplacedPreds
we avoid duplicating a BB into another already placed BB to prevent destroying
computed layout. But if the successor BB is a return block, duplicating it will
only reduce taken branches without hurt to any other branches.

Differential Revision: https://reviews.llvm.org/D153093

16 months ago[NFC][asan] Move AsanStats update
Vitaly Buka [Wed, 21 Jun 2023 18:46:31 +0000 (11:46 -0700)]
[NFC][asan] Move AsanStats update

Deallocate is a more appropiate place to update free count.

16 months ago[gn build] Port 1ee4d880e876
LLVM GN Syncbot [Wed, 21 Jun 2023 18:41:47 +0000 (18:41 +0000)]
[gn build] Port 1ee4d880e876

16 months agoNVPTX: Lower unreachable to exit to allow ptxas to accurately reconstruct the CFG.
Tim Besard [Tue, 20 Jun 2023 17:29:16 +0000 (10:29 -0700)]
NVPTX: Lower unreachable to exit to allow ptxas to accurately reconstruct the CFG.

PTX does not have a notion of `unreachable`, which results in emitted basic
blocks having an edge to the next block:

```
block1:
  call @does_not_return();
  // unreachable
block2:
  // ptxas will create a CFG edge from block1 to block2
```

This may result in significant changes to the control flow graph, e.g., when
LLVM moves unreachable blocks to the end of the function. That's a problem
in the context of divergent control flow, as `ptxas` uses the CFG to determine
divergent regions, while some intructions may not be executed divergently.

For example, `bar.sync` is not allowed to be executed divergently on Pascal
or earlier. If we start with the following:

```
entry:
  // start of divergent region
  @%p0 bra cont;
  @%p1 bra unlikely;
  ...
  bra.uni cont;
unlikely:
  ...
  // unreachable
cont:
  // end of divergent region
  bar.sync 0;
  bra.uni exit;
exit:
  ret;
```

it is transformed by the branch-folder and block-placement passes to:

```
entry:
  // start of divergent region
  @%p0 bra cont;
  @%p1 bra unlikely;
  ...
  bra.uni cont;
cont:
  bar.sync 0;
  bra.uni exit;
unlikely:
  ...
  // unreachable
exit:
  // end of divergent region
  ret;
```

After moving the `unlikely` block to the end of the function, it has an edge
to the `exit` block, which widens the divergent region and makes the `bar.sync`
instruction happen divergently. That causes wrong computations, as we've been
running into for years with Julia code (which emits a lot of `trap` +
`unreachable` code all over the place).

To work around this, add an `exit` instruction before every `unreachable`,
as `ptxas` understands that exit terminates the CFG. Note that `trap` is not
equivalent, and only future versions of `ptxas` will model it like `exit`.
Another alternative would be to emit a branch to the block itself, but emitting
`exit` seems like a cleaner solution to represent `unreachable` to me.

Also note that this may not be sufficient, as it's possible that the block
with unreachable control flow is branched to from different divergent regions,
e.g. after block merging, in which case it may still be the case that `ptxas`
could reconstruct a CFG where divergent regions are merged (I haven't confirmed
this, but also haven't encountered this pattern in the wild yet):

```
entry:
  // start of divergent region 1
  @%p0 bra cont1;
  @%p1 bra unlikely;
  bra.uni cont1;
cont1:
  // intended end of divergent region 1
  bar.sync 0;
  // start of divergent region 2
  @%p2 bra cont2;
  @%p3 bra unlikely;
  bra.uni cont2;
cont2:
  // intended end of divergent region 2
  bra.uni exit;
unlikely:
  ...
  exit;
exit:
  // possible end of merged divergent region?
```

I originally tried to avoid the above by cloning paths towards `unreachable` and
splitting the outgoing edges, but that quickly became too complicated. I propose
we go with the simple solution first, also because modern GPUs with more flexible
hardware thread schedulers don't even suffer from this issue.

Finally, although I expect this to fix most of
https://bugs.llvm.org/show_bug.cgi?id=27738, I do still encounter
miscompilations with Julia's unreachable-heavy code when targeting these
older GPUs using an older `ptxas` version (specifically, from CUDA 11.4 or
below). This is likely due to related bugs in `ptxas` which have been fixed
since, as I have filed several reproducers with NVIDIA over the past couple of
years. I'm not inclined to look into fixing those issues over here, and will
instead be recommending our users to upgrade CUDA to 11.5+ when using these GPUs.

Also see:
- https://github.com/JuliaGPU/CUDAnative.jl/issues/4
- https://github.com/JuliaGPU/CUDA.jl/issues/1746
- https://discourse.llvm.org/t/llvm-reordering-blocks-breaks-ptxas-divergence-analysis/71126

Reviewed By: jdoerfert, tra

Differential Revision: https://reviews.llvm.org/D152789

16 months ago[lldb] Fix failure in TestStackCoreScriptedProcess on x86_64
Med Ismail Bennani [Tue, 13 Jun 2023 20:47:14 +0000 (13:47 -0700)]
[lldb] Fix failure in TestStackCoreScriptedProcess on x86_64

This patch should address the failure of TestStackCoreScriptedProcess
that is happening specifically on x86_64.

It turns out that in 1370a1cb5b97, I changed the way we extract integers
from a `StructuredData::Dictionary` and in order to get a stop info from
the scripted process, we call a method that returns a `SBStructuredData`
containing the stop reason data.

TestStackCoreScriptedProcess` was failing specifically on x86_64 because
the stop info dictionary contains the signal number, that the `Scripted
Thread` was trying to extract as a signed integer where it was actually
parsed as an unsigned integer. That caused `GetValueForKeyAsInteger` to
return the default value parameter, `LLDB_INVALID_SIGNAL_NUMBER`.

This patch address the issue by extracting the signal number with the
appropriate type and re-enables the test.

Differential Revision: https://reviews.llvm.org/D152848

Signed-off-by: Med Ismail Bennani <ismail@bennani.ma>
16 months ago[MC] Add .pushsection/.popsection support to COFFAsmParser
cynecx [Wed, 21 Jun 2023 17:39:56 +0000 (10:39 -0700)]
[MC] Add .pushsection/.popsection support to COFFAsmParser

The COFFAsmParser (to my surprise) didn't support the .pushsection and
.popsection directives. These directives aren't directly useful, however for
frontends that have inline asm support this is really useful. Rust in
particular, has support for inline asm, which can be used together with these
directives to "emulate" features like static generics. This patch adds support
for the two mentioned directives.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D152085

16 months ago[lldb][MachO] Fix section type recognition for new DWARF 5 sections
Felipe de Azevedo Piovezan [Wed, 21 Jun 2023 15:25:14 +0000 (11:25 -0400)]
[lldb][MachO] Fix section type recognition for new DWARF 5 sections

When LLDB needs to access a debug section, it generally calls
SectionList::FindSectionByType with the corresponding type (we have one type for
each DWARF section). However, the missing entries made some sections be
classified as "eSectionTypeOther", which makes all calls to `FindSectionByType`
fail.

With this patch, a check-lldb build with
`-DLLDB_TEST_USER_ARGS=--dwarf-version=5` reports a much lower number of
failures:

  Unsupported      :  327
  Passed           : 2423
  Expectedly Failed:   16
  Unresolved       :    2
  Failed           :   52

This is down from previously 400~ failures.

Differential Revision: https://reviews.llvm.org/D153433

16 months agoRevert "Define/guard MLIR_STANDALONE_BUILD LLVM_LIBRARY_OUTPUT_INTDIR var."
Stella Laurenzo [Wed, 21 Jun 2023 17:20:35 +0000 (10:20 -0700)]
Revert "Define/guard MLIR_STANDALONE_BUILD LLVM_LIBRARY_OUTPUT_INTDIR var."

This reverts commit f55fd19b6b565827af5fbf504952dcc35b8b7360.

As noted on the original thread, other uses of LLVM_LIBRARY_OUTPUT_INTDIR are optional. Will make a separate patch that makes this use optional as well.

16 months ago[lldb][NFCI] Remove ConstString from GDBRemoteCommunicationClient::ConfigureRemoteStr...
Alex Langford [Fri, 16 Jun 2023 22:49:03 +0000 (15:49 -0700)]
[lldb][NFCI] Remove ConstString from GDBRemoteCommunicationClient::ConfigureRemoteStructuredData

ConstString's benefits are not being utilized here, StringRef is
sufficient.

Differential Revision: https://reviews.llvm.org/D153177

16 months ago[flang][hlfir] fix missing conversion in transpose simplification
Tom Eccles [Tue, 20 Jun 2023 12:40:26 +0000 (12:40 +0000)]
[flang][hlfir] fix missing conversion in transpose simplification

It seems just replacing the operation was not replacing all of the uses
when the types of the expression before and after this pass differ (due
to differing shape information). Now the shape information is always
kept the same.

This fixes https://github.com/llvm/llvm-project/issues/63399

Differential Revision: https://reviews.llvm.org/D153333

16 months ago[MLIR][Linalg] Rename `tile-to-foreach-thread.mlir` (NFC)
Lorenzo Chelini [Mon, 19 Jun 2023 16:18:16 +0000 (18:18 +0200)]
[MLIR][Linalg] Rename `tile-to-foreach-thread.mlir` (NFC)

`ForeachThreadOp` was renamed to `ForallOp`, update the filename to
avoid confusion.

See: https://reviews.llvm.org/D144242

16 months agoFix a memory leak in the Python implementation of bytecode writer
Adam Paszke [Wed, 21 Jun 2023 16:40:31 +0000 (09:40 -0700)]
Fix a memory leak in the Python implementation of bytecode writer

The bytecode writer config was heap-allocated, but was never freed, causing ASAN errors.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D153440

16 months ago[libc] Rename and install the RPC server interface
Joseph Huber [Thu, 15 Jun 2023 15:57:06 +0000 (10:57 -0500)]
[libc] Rename and install the RPC server interface

This patch prepares the RPC interface to be installed. We place this in
the existing `llvm-gpu-none` directory as it will also give us access to
the generated `libc` headers for the opcodes.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D153040

16 months ago[RISCV] Custom lower fixed vector undef to scalable undef
Luke Lau [Wed, 21 Jun 2023 12:13:40 +0000 (13:13 +0100)]
[RISCV] Custom lower fixed vector undef to scalable undef

This avoids undefs from being expanded to a build vector of zeroes.
As noted by @craig.topper in D153399

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153411

16 months ago[libc][NFC] Cleanup the RPC server implementation prior to installing
Joseph Huber [Wed, 21 Jun 2023 16:10:11 +0000 (11:10 -0500)]
[libc][NFC] Cleanup the RPC server implementation prior to installing

This does some simple cleanup prior to landing the patch to install
these.

Differential Revision: https://reviews.llvm.org/D153439

16 months ago[libcxx] Include <sys/time.h> in posix_compat.h
Petr Hosek [Tue, 20 Jun 2023 21:49:22 +0000 (21:49 +0000)]
[libcxx] Include <sys/time.h> in posix_compat.h

posix_compat.h uses struct timeval which is defined in <sys/time.h>
but it doesn't include it. On most POSIX platforms like Linux or macOS,
that headers is transitively included by other headers like <sys/stat.h>,
but there are other platforms where this is not the case.

Differential Revision: https://reviews.llvm.org/D153384

16 months ago[RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vecto...
Craig Topper [Wed, 21 Jun 2023 15:57:46 +0000 (08:57 -0700)]
[RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vector lowreing.

A build_vector is the canonical representation rather than multiple
insert_vector_elts.

Unfortunately, this regresses quite a few tests now primarily due to not
having a vmv.s.x special case, but I hope we can improve this with future
patches.

Stress testing in our downstream found an infinite loop in DAG combine.
This patch breaks the infinite loop.

The insert_vector_element chain starts with a fixed vector undef.
Fixed vector undef is currently expanded to a build_vector of 0s
which gets lowered to a vmv.v.i. The insert chain overwrites all
elements so SimplifyDemandedVectorElts turns the vmv.v.i back into
undef and the cycle repeats.

We probably should custom lower fixed vector undef to scalable
vector undef. I think that would also fix the infinite loop, but
I didn't test that.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D153399

16 months ago[llvm-objdump][test] Add 2 symbols to adjust-vma.test
Fangrui Song [Wed, 21 Jun 2023 15:52:53 +0000 (08:52 -0700)]
[llvm-objdump][test] Add 2 symbols to adjust-vma.test

They will demonstrate some symbol that --adjust-vma= should not adjust.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D153401

16 months ago[RISCV] Stop isInterleaveShuffle from producing illegal extract_subvectors.
Craig Topper [Wed, 21 Jun 2023 15:52:28 +0000 (08:52 -0700)]
[RISCV] Stop isInterleaveShuffle from producing illegal extract_subvectors.

The definition for ISD::EXTRACT_SUBVECTOR says the index must be
aligned to the known minimum elements of the extracted type. We mostly
got away with this but it turns out there are places that depend on this.

For example, this code in getNode for ISD::EXTRACT_SUBVECTOR

```
    // EXTRACT_SUBVECTOR of CONCAT_VECTOR can be simplified if the pieces of
    // the concat have the same type as the extract.
    if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0 &&
        VT == N1.getOperand(0).getValueType()) {
      unsigned Factor = VT.getVectorMinNumElements();
      return N1.getOperand(N2C->getZExtValue() / Factor);
    }
```

This depends on N2C->getZExtValue() being evenly divisible by Factor.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D153380

16 months ago[tutorials] Add missing ExecutorSymbolDef header.
Lang Hames [Wed, 21 Jun 2023 15:50:14 +0000 (08:50 -0700)]
[tutorials] Add missing ExecutorSymbolDef header.

Similar to c118d05f9ed, but applied to the base Kaleidoscope series.

16 months agoRevert "[mlir][CRunnerUtils] Use explicit execution engine symbol registration."
Mehdi Amini [Wed, 21 Jun 2023 15:50:18 +0000 (17:50 +0200)]
Revert "[mlir][CRunnerUtils] Use explicit execution engine symbol registration."

This reverts commit 9119325a5666e557a19f38a05525578b556c215b.

A buildbot is broken, probably because of this change breaking the
SHARED_LIBS=ON build more.

16 months agoRevert "[LoopSink] Allow sinking to PHI-use"
Alexander Kornienko [Wed, 21 Jun 2023 14:41:05 +0000 (16:41 +0200)]
Revert "[LoopSink] Allow sinking to PHI-use"

This reverts commit 54711a6a5872d5f97da4c0a1bd7e58d0546ca701.

The commit is causing a clang crash: https://reviews.llvm.org/D152772#4437254

16 months ago[tutorials][BuildingAJIT] Add missing ExecutorSymbolDef header.
Lang Hames [Wed, 21 Jun 2023 15:31:49 +0000 (08:31 -0700)]
[tutorials][BuildingAJIT] Add missing ExecutorSymbolDef header.

16 months ago[clang-format] vim integration: Mention python3 variant of bindings
Jannik Silvanus [Tue, 20 Jun 2023 13:22:32 +0000 (15:22 +0200)]
[clang-format] vim integration: Mention python3 variant of bindings

The instructions in the documentation only mentioned how to include
bindings for clang-format into vim using python2. Add the instructions
for python3 which were already present in the source comments.

Differential Revision: https://reviews.llvm.org/D153338

Change-Id: I25fdbd36f0c7e745061908be8e26f68cb31c7dd5

16 months ago[InstCombine] Add !noundef to match behavior of violating assume
luxufan [Wed, 21 Jun 2023 15:03:56 +0000 (23:03 +0800)]
[InstCombine] Add !noundef to match behavior of violating assume

The behaviors of violating assume instruction or !nonnull metadata is
different. The former is immediate undefined behavior, but the latter is
returning poison value. This patch adds !noundef to trigger immediate
undefined behavior if !nonnull is violated.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D153400

16 months ago[IR] Add getAccessType to Instruction
Luke Lau [Mon, 15 May 2023 15:56:48 +0000 (16:56 +0100)]
[IR] Add getAccessType to Instruction

There are multiple places in the code where the type of memory being accessed from an instruction needs to be obtained, including an upcoming patch to improve GEP cost modeling. This deduplicates the logic between them. It's not strictly NFC as EarlyCSE/LoopStrengthReduce may catch more intrinsics now.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D150583

16 months agoRevert "[LLD][ELF] Cortex-M Security Extensions (CMSE) Support"
Amilendra Kodithuwakku [Wed, 21 Jun 2023 15:10:08 +0000 (16:10 +0100)]
Revert "[LLD][ELF] Cortex-M Security Extensions (CMSE) Support"

This reverts commit c4fea3905617af89d1ad87319893e250f5b72dd6.

I am reverting this for now until I figure out how to fix
the build bot errors and warnings.

Errors:
llvm-project/lld/ELF/Arch/ARM.cpp:1300:29: error: expected primary-expression before ‘>’ token
 osec->writeHeaderTo<ELFT>(++sHdrs);

Warnings:
llvm-project/lld/ELF/Arch/ARM.cpp:1306:31: warning: left operand of comma operator has no effect [-Wunused-value]

16 months ago[X86] Add test for PR63430 (NFC)
Nikita Popov [Wed, 21 Jun 2023 15:12:39 +0000 (17:12 +0200)]
[X86] Add test for PR63430 (NFC)

16 months agoRISCV: Update test
Matt Arsenault [Wed, 21 Jun 2023 15:05:03 +0000 (11:05 -0400)]
RISCV: Update test

16 months ago[RISCV] Add support for XCVmac extension in CV32E40P
Qihan Cai [Wed, 21 Jun 2023 14:59:30 +0000 (22:59 +0800)]
[RISCV] Add support for XCVmac extension in CV32E40P

Implement XCVmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].

Contributors: @CharKeaney, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[0] https://github.com/openhwgroup/corev-llvm-project

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152821

16 months ago[CVP] Don't process sext or ashr if value state including undef
luxufan [Wed, 21 Jun 2023 14:36:42 +0000 (22:36 +0800)]
[CVP] Don't process sext or ashr if value state including undef

similar to D152773

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D152774

16 months ago[libc][NFC] Move `__has_builtin` to `LIBC_HAS_BUILTIN`
Joseph Huber [Wed, 21 Jun 2023 14:50:04 +0000 (09:50 -0500)]
[libc][NFC] Move `__has_builtin` to `LIBC_HAS_BUILTIN`

Summary:
These should use the common `LIBC_HAS_BUILTIN` even if we will only
compile this with `clang`.

16 months agoX86: Fix asserts only test
Matt Arsenault [Wed, 21 Jun 2023 14:40:10 +0000 (10:40 -0400)]
X86: Fix asserts only test

This test should really check the MIR result rather than rely on the
debug output.

16 months agoRegisterCoalescer: Fix name of pass
Matt Arsenault [Wed, 21 Jun 2023 14:20:20 +0000 (10:20 -0400)]
RegisterCoalescer: Fix name of pass

I finally snapped and fixed this inconsistency.

16 months ago[LLD][ELF] Cortex-M Security Extensions (CMSE) Support
Amilendra Kodithuwakku [Wed, 21 Jun 2023 11:48:33 +0000 (12:48 +0100)]
[LLD][ELF] Cortex-M Security Extensions (CMSE) Support

This commit provides linker support for Cortex-M Security Extensions (CMSE).
The specification for this feature can be found in ARM v8-M Security Extensions:
Requirements on Development Tools.

The linker synthesizes a security gateway veneer in a special section;
`.gnu.sgstubs`, when it finds non-local symbols `__acle_se_<entry>` and `<entry>`,
defined relative to the same text section and having the same address. The
address of `<entry>` is retargeted to the starting address of the
linker-synthesized security gateway veneer in section `.gnu.sgstubs`.

In summary, the linker translates input:

```
    .text
  entry:
  __acle_se_entry:
    [entry_code]

```
into:

```
    .section .gnu.sgstubs
  entry:
    SG
    B.W __acle_se_entry

    .text
  __acle_se_entry:
    [entry_code]
```

If addresses of `__acle_se_<entry>` and `<entry>` are not equal, the linker
considers that `<entry>` already defines a secure gateway veneer so does not
synthesize one.

If `--out-implib=<out.lib>` is specified, the linker writes the list of secure
gateway veneers into a CMSE import library `<out.lib>`. The CMSE import library
will have 3 sections: `.symtab`, `.strtab`, `.shstrtab`. For every secure gateway
veneer <entry> at address `<addr>`, `.symtab` contains a `SHN_ABS` symbol `<entry>` with
value `<addr>`.

If `--in-implib=<in.lib>` is specified, the linker reads the existing CMSE import
library `<in.lib>` and preserves the entry function addresses in the resulting
executable and new import library.

Reviewed By: MaskRay, peter.smith

Differential Revision: https://reviews.llvm.org/D139092

16 months ago[libc++] Get rid of _LIBCPP_DISABLE_NEW_DELETE_DEFINITIONS
Louis Dionne [Wed, 14 Jun 2023 22:31:20 +0000 (15:31 -0700)]
[libc++] Get rid of _LIBCPP_DISABLE_NEW_DELETE_DEFINITIONS

Whether we include operator new and delete into libc++ has always
been a build time setting, and piggy-backing on a macro like
_LIBCPP_DISABLE_NEW_DELETE_DEFINITIONS is inconsistent with how
we handle similar cases for e.g. LIBCXX_ENABLE_RANDOM_DEVICE. Instead,
simply avoid including new.cpp in the sources of the library when we
do not wish to include these operators in the build.

This also makes us much closer to being able to share the definitions
between libc++ and libc++abi, since we could technically build those
definitions into a standalone static library and decide whether we link
it into libc++abi.dylib or libc++.dylib.

Differential Revision: https://reviews.llvm.org/D153272

16 months ago[AMDGPU] Add some positive tests for merging S_LOAD instructions
Jay Foad [Wed, 21 Jun 2023 12:55:43 +0000 (13:55 +0100)]
[AMDGPU] Add some positive tests for merging S_LOAD instructions

16 months ago[SystemZ] Fix regression in test macro-prefix-map-lambda.cpp
Kai Nacke [Tue, 20 Jun 2023 14:26:57 +0000 (14:26 +0000)]
[SystemZ] Fix regression in test macro-prefix-map-lambda.cpp

The failing test comes from https://reviews.llvm.org/D152570.
Root cause of the failure is that a string constant on SystemZ
has an alignment of 2, not 1. The CSKY target has a similar problem.
The solution is to replace the fixed number with a regex.

Reviewed By: uweigand, tuliom, Zibi

Differential Revision: https://reviews.llvm.org/D153352

16 months agoRevert D148717 "[libc] Improve memcmp latency and codegen"
Guillaume Chatelet [Wed, 21 Jun 2023 12:25:22 +0000 (12:25 +0000)]
Revert D148717 "[libc] Improve memcmp latency and codegen"

Once integrated in our codebase the patch triggered a bunch of failing
tests. We do not yet understand where the bug is but we revert it to
move forward with integration.
This reverts commit 5e32765c15ab8df3d2635a2bb5078c5b1d5714d5.

16 months ago[libc++] Guard terminate_successful with TEST_HAS_NO_EXCEPTIONS
Louis Dionne [Mon, 19 Jun 2023 18:44:21 +0000 (14:44 -0400)]
[libc++] Guard terminate_successful with TEST_HAS_NO_EXCEPTIONS

This one is a bit twisted. Some platforms don't have support for
exiting in a clean manner, so they don't provide std::exit(). As
a result, defining `terminate_successful()` on those platforms won't
work, and the PSTL tests that rely on `terminate_successful()` also
won't work.

However, we don't have a notion of "no clean termination" in libc++,
so we can't properly guard this. Since embedded platforms that don't
support clean termination usually also don't enable exceptions, we
don't need to be able to run those `terminate_successful` PSTL tests,
and guarding the definition of `terminate_successful` with
TEST_HAS_NO_EXCEPTIONS works pretty well.

This is kind of a hack for the lack of having a concept of "no clean
termination" in the library and in the test suite.

Differential Revision: https://reviews.llvm.org/D153302

16 months agoRevert "[Bazel][mlir] Fix ODR violation introduced in 7ab749c."
Christian Sigg [Wed, 21 Jun 2023 12:29:44 +0000 (14:29 +0200)]
Revert "[Bazel][mlir] Fix ODR violation introduced in 7ab749c."

This reverts commit e83c8c36005f0068841e628612e9e5bce7e2ac9e.

Depending only on the support header files is not sufficient.

16 months ago[AMDGPU] Preserve dom-tree analysis in atomic optimizer.
Pravin Jagtap [Wed, 21 Jun 2023 12:02:43 +0000 (08:02 -0400)]
[AMDGPU] Preserve dom-tree analysis in atomic optimizer.

AMDGPUAtomicOptimizer updates the dominator tree whenever
it modified the control flow. Therefore preserving the
analysis similar to legacy PM.

Reviewed By: arsenm, yassingh, #amdgpu

Differential Revision: https://reviews.llvm.org/D153349

16 months ago[Flang][Debug] NFC: Correct the REQUIRES line to use system-linux
Kiran Chandramohan [Wed, 21 Jun 2023 09:28:14 +0000 (10:28 +0100)]
[Flang][Debug] NFC: Correct the REQUIRES line to use system-linux

Reviewed By: kkwli0

Differential Revision: https://reviews.llvm.org/D153126

16 months ago[AMDGPU] Minor refactoring in SILoadStoreOptimizer::offsetsCanBeCombined
Jay Foad [Wed, 21 Jun 2023 11:04:29 +0000 (12:04 +0100)]
[AMDGPU] Minor refactoring in SILoadStoreOptimizer::offsetsCanBeCombined

16 months ago[ConstraintSystem] Fix mislabeling in unittests (NFC)
Antonio Frighetto [Wed, 21 Jun 2023 10:52:02 +0000 (12:52 +0200)]
[ConstraintSystem] Fix mislabeling in unittests (NFC)

Possible misleading comment has been addressed.

16 months ago[lldb] Add release note for "register info" command
David Spickett [Mon, 5 Jun 2023 17:41:32 +0000 (17:41 +0000)]
[lldb] Add release note for "register info" command

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D152919

16 months ago[lldb] Add register field tables to the "register info" command
David Spickett [Mon, 5 Jun 2023 17:02:46 +0000 (17:02 +0000)]
[lldb] Add register field tables to the "register info" command

This teaches DumpRegisterInfo to generate a table from the register
flags type. It just calls a method on RegisterFlags.

As such, the extra tests are minimal and only show that the intergration
works. Exhaustive formatting tests are done with RegisterFlags itself.

Example:
```
(lldb) register info cpsr
       Name: cpsr
       Size: 4 bytes (32 bits)
    In sets: general (index 0)

| 31 | 30 | 29 | 28 | 27-26 | 25  | 24  | 23  | 22  | 21 | 20 | 19-13 |  12  | 11-10 | 9 | 8 | 7 | 6 | 5 |  4  | 3-2 | 1 | 0  |
|----|----|----|----|-------|-----|-----|-----|-----|----|----|-------|------|-------|---|---|---|---|---|-----|-----|---|----|
| N  | Z  | C  | V  |       | TCO | DIT | UAO | PAN | SS | IL |       | SSBS |       | D | A | I | F |   | nRW | EL  |   | SP |
```

LLDB limits the max terminal width to 80 chars by default.
So to get that full width output you will need to change the "term-width"
setting to something higher.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D152918

16 months ago[RewriteStatepointsForGC] Convert tests to opaque pointers (NFC)
Nikita Popov [Wed, 21 Jun 2023 10:40:23 +0000 (12:40 +0200)]
[RewriteStatepointsForGC] Convert tests to opaque pointers (NFC)

16 months ago[AppleTables] Implement iterator over all entries in table
Felipe de Azevedo Piovezan [Thu, 15 Jun 2023 12:18:51 +0000 (08:18 -0400)]
[AppleTables] Implement iterator over all entries in table

This commit adds functionality to the Apple Accelerator table allowing iteration
over all elements in the table.

Our iterators look like streaming iterators: when we increment the iterator we
check if there is still enough data in the "stream" (in our case, the blob of
data of the accelerator table) and extract the next entry. If any failures
occur, we immediately set the iterator to be the end iterator.

Since the ultimate user of this functionality is LLDB, there are roughly two
iteration methods we want support: one that also loads the name of each entry,
and one which does not. Loading names is measurably slower (one order the
magnitude) than only loading DIEs, so we used some template metaprograming to
implement both iteration methods.

Depends on D153066

Differential Revision: https://reviews.llvm.org/D153066

16 months ago[SVE ACLE] Implement IR combines to convert intrinsics used for _m C/C++ builtins
Jolanta Jensen [Wed, 17 May 2023 09:21:40 +0000 (09:21 +0000)]
[SVE ACLE] Implement IR combines to convert intrinsics used for _m C/C++ builtins

This patch implements IR combines to convert intrinsics used for _m C/C++ builtins
which take an all active predicate to their equivalent _u intrinsic.

Differential Revision: https://reviews.llvm.org/D152005

16 months agoPowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
Kishan Parmar [Wed, 21 Jun 2023 10:16:43 +0000 (10:16 +0000)]
PowerPC/SPE:  Add phony registers for high halves of SPE SuperRegs

The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31)
as artificial regs, similar to how X86 has done it.
And emit store /reload instructions for the required halves.

PR : https://github.com/llvm/llvm-project/issues/57307

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D152437

16 months ago[DWARFLinker][DWARFv5] change emitSLEB128IntValue with emitULEB128IntValue for ranges.
Alexey Lapshin [Fri, 16 Jun 2023 21:13:47 +0000 (23:13 +0200)]
[DWARFLinker][DWARFv5] change emitSLEB128IntValue with emitULEB128IntValue for ranges.

This patch changes emitSLEB128IntValue with emitULEB128IntValue
for length part of address range of DW_RLE_start_length kind. DWARFv5
standard:

DW_RLE_start_length
This is a form of bounded range entry that has one target address operand
value and an unsigned LEB128 integer length operand value.

Differential Revision: https://reviews.llvm.org/D153334

16 months ago[Clang][Interp] Diagnose uninitialized ctor of global record arrays
Takuya Shimizu [Wed, 21 Jun 2023 10:03:01 +0000 (19:03 +0900)]
[Clang][Interp] Diagnose uninitialized ctor of global record arrays

This patch adds a check for uninitialized subobjects of global variables that are record arrays.
e.g. `constexpr Foo f[2];`

Reviewed By: tbaeder

Differential Revision: https://reviews.llvm.org/D152548

16 months ago[mlir][CRunnerUtils] Use explicit execution engine symbol registration.
Ingo Müller [Tue, 20 Jun 2023 14:36:33 +0000 (14:36 +0000)]
[mlir][CRunnerUtils] Use explicit execution engine symbol registration.

As a follow up of https://reviews.llvm.org/D153250, this path uses the
explicit symbol registration mechanism of the execution engine in the
CRunnerUtils library.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D153354

16 months ago[lldb] Correct spelling in RegisterFlags comments
David Spickett [Wed, 21 Jun 2023 09:33:35 +0000 (09:33 +0000)]
[lldb] Correct spelling in RegisterFlags comments

I missed these review comments on https://reviews.llvm.org/D152917
before landing it.

16 months ago[Inline] Convert tests to opaque pointers (NFC)
Nikita Popov [Wed, 21 Jun 2023 09:27:49 +0000 (11:27 +0200)]
[Inline] Convert tests to opaque pointers (NFC)

16 months ago[Inline] Regenerate test checks (NFC)
Nikita Popov [Wed, 21 Jun 2023 09:27:30 +0000 (11:27 +0200)]
[Inline] Regenerate test checks (NFC)

16 months ago[LLDB] Add table formatting for register fields
David Spickett [Mon, 5 Jun 2023 17:02:09 +0000 (17:02 +0000)]
[LLDB] Add table formatting for register fields

This will be used by the "register info" command to show
the layout of register contents. For example if we have
these fields coming in from XML:
```
<field name="D" start="0" end="7"/>
<field name="C" start="8" end="15"/>
<field name="B" start="16" end="23"/>
<field name="A" start="24" end="31"/>
```
We get:
```
| 31-24 | 23-16 | 15-8 | 7-0 |
|-------|-------|------|-----|
|   A   |   B   |  C   |  D  |
```
Note that this is only the layout, not the values.
For values, use "register read".

The tables' columns are center padded (left bias
if there's an odd padding) and will wrap if the terminal width
is too low.

```
| 31-24 | 23-16 |
|-------|-------|
|   A   |   B   |

| 15-8 | 7-0 |
|------|-----|
|  C   |  D  |
```

This means we match the horizontal format seen in many architecture
manuals but don't spam the user with lots of misaligned text when the
output gets very long.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D152917

16 months ago[ConstantHoisting] Convert tests to opaque pointers (NFC)
Nikita Popov [Wed, 21 Jun 2023 09:20:15 +0000 (11:20 +0200)]
[ConstantHoisting] Convert tests to opaque pointers (NFC)

16 months ago[ConstantHoisting] Regenerate test checks (NFC)
Nikita Popov [Wed, 21 Jun 2023 09:19:58 +0000 (11:19 +0200)]
[ConstantHoisting] Regenerate test checks (NFC)

16 months ago[Bazel][mlir] Fix ODR violation introduced in 7ab749c.
Christian Sigg [Wed, 21 Jun 2023 09:15:09 +0000 (11:15 +0200)]
[Bazel][mlir] Fix ODR violation introduced in 7ab749c.

16 months ago[C++20] [Modules] Use the canonical decl when getting associated constraints
Chuanqi Xu [Wed, 21 Jun 2023 08:57:27 +0000 (16:57 +0800)]
[C++20] [Modules] Use the canonical decl when getting associated constraints

Close https://github.com/llvm/llvm-project/issues/62943.

The root cause for the issue is that we think the associated constraints
from the 'same' declaration in different module units are different
incorrectly. Since the constraints doesn't know anything about decls and
modules, we should fix the problem by getting the associated constraints
from the exactly the same declarations from different modules.

16 months ago[gn build] Port ba85f206fe6f
LLVM GN Syncbot [Wed, 21 Jun 2023 08:50:28 +0000 (08:50 +0000)]
[gn build] Port ba85f206fe6f

16 months ago[lldb] Add "register info" command
David Spickett [Wed, 1 Mar 2023 11:03:01 +0000 (11:03 +0000)]
[lldb] Add "register info" command

This adds a new command that will show all the information lldb
knows about a register.
```
(lldb) register info s0
       Name: s0
       Size: 4 bytes (32 bits)
Invalidates: v0, d0
  Read from: v0
    In sets: Floating Point Registers (index 1)
```

Currently it only allows a single register, and we get the
information from the RegisterInfo structure.

For those of us who know the architecture well, this information
is all pretty obvious. For those who don't, it's nice to have it
at a glance without leaving the debugger.

I hope to have more in depth information to show here in the future,
which will be of wider use.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D152916

16 months agoRevert "[llvm-exegesis] Introduce SubprocessMemory Utility Class"
Aiden Grossman [Wed, 21 Jun 2023 08:42:36 +0000 (08:42 +0000)]
Revert "[llvm-exegesis] Introduce SubprocessMemory Utility Class"

This reverts commit 1b9b78fd481a13b54afaf4804ee4ad18fcf006fd.

There are spurious test failures on the ml-* bots and some of the ARM
builders are complaining about shm_open being missing. Pulling this
commit so that I can investigate after I sleep.

16 months ago[LoongArch] Support CodeModel::Large codegen
WANG Xuerui [Wed, 21 Jun 2023 08:04:57 +0000 (16:04 +0800)]
[LoongArch] Support CodeModel::Large codegen

This is intended to behave like GCC's `-mcmodel=extreme`.

Technically the true GCC equivalent would be `-mcmodel=large` which is
not yet implemented there, and we probably do not want to take the
"Large" name until things settle in GCC side, but:

* LLVM does not have a `CodeModel::Extreme`, and it seems too early to
  have such a variant added just for enabling LoongArch; and
* `CodeModel::Small` is already being used for GCC `-mcmodel=normal`
  which is already a case of divergent naming.

Regarding the codegen, loads/stores immediately after a PC-relative
large address load (that ends with something like `add.d $addr, $addr,
$tmp`) should get merged with the addition into corresponding `ldx/stx`
ops, but is currently not done. This is because pseudo-instructions are
expanded after instruction selection, and is best fixed with a separate
change.

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D150522

16 months agoReleaseNotes: __builtin_unpredictable is now handled by X86 Backend
Dávid Bolvanský [Wed, 21 Jun 2023 08:24:06 +0000 (10:24 +0200)]
ReleaseNotes: __builtin_unpredictable is now handled by X86 Backend

16 months ago[BOLT][RISCV] Fix implementation of getTargetSymbol
Job Noorman [Wed, 21 Jun 2023 08:20:27 +0000 (10:20 +0200)]
[BOLT][RISCV] Fix implementation of getTargetSymbol

- Correctly handle OpNum == 0 (auto select operand)
- Implement MCExpr overload

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D153343

16 months ago[BOLT][RISCV] Implement branch reversal
Job Noorman [Wed, 21 Jun 2023 08:20:14 +0000 (10:20 +0200)]
[BOLT][RISCV] Implement branch reversal

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D153344

16 months ago[BOLT][RISCV] Implement return/unconditional branch creation
Job Noorman [Wed, 21 Jun 2023 08:20:04 +0000 (10:20 +0200)]
[BOLT][RISCV] Implement return/unconditional branch creation

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D153342

16 months ago[llvm-exegesis] Introduce SubprocessMemory Utility Class
Aiden Grossman [Sat, 20 May 2023 09:50:43 +0000 (09:50 +0000)]
[llvm-exegesis] Introduce SubprocessMemory Utility Class

This patch introduces the SubprocessMemory class to llvm-exegesis. This
class contains several utilities that are needed for managing memory to
set up an execution environment for memory annotations.

Reviewed By: courbet

Differential Revision: https://reviews.llvm.org/D151022

16 months ago[mlir] #include CRunnerUtils.h instead of RunnerUtils.h in SPIRV-runner
Christian Sigg [Wed, 21 Jun 2023 08:11:46 +0000 (10:11 +0200)]
[mlir] #include CRunnerUtils.h instead of RunnerUtils.h in SPIRV-runner

This avoids bazel builds failing after commit bba2b656110209a3d9863b92c060082479b06ab1 because libmlir_test_spirv_cpu_runner_c_wrappers.so registers the same runner functions twice.

More precisely, this problem only shows up internally at Google because the bazel build does not have that target.

Either way though, it's better to IWYU.

16 months ago[llvm-exegesis] Introduce Subprocess Executor Mode
Aiden Grossman [Sat, 20 May 2023 09:23:27 +0000 (09:23 +0000)]
[llvm-exegesis] Introduce Subprocess Executor Mode

This patch introduces the subprocess executor mode. Currently, this new
mode doesn't do anything fancy, just executing the same code that the
inprocess executor would do, but within a subprocess. This sets up the
ability to add in many more memory-related features in the future.

16 months ago[gn build] Port c9e08fa60666
LLVM GN Syncbot [Wed, 21 Jun 2023 07:42:21 +0000 (07:42 +0000)]
[gn build] Port c9e08fa60666

16 months ago[RISCV] Add a pass to merge moving parameter registers instructions for Zcmp
WuXinlong [Wed, 21 Jun 2023 07:40:33 +0000 (15:40 +0800)]
[RISCV] Add a pass to merge moving parameter registers instructions for Zcmp

This patch adds a pass to generate `cm.mvsa01` & `cm.mva01s`.

RISCVMoveOptimizer.cpp which combines two mv inst into one cm.mva01s or cm.mva01s.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150415

16 months ago[mlir][linalg][NFC] Add test case for memref vectorization
Matthias Springer [Wed, 21 Jun 2023 07:17:32 +0000 (09:17 +0200)]
[mlir][linalg][NFC] Add test case for memref vectorization

Add test cases for vectorizing linalg.matmul and linalg.copy on tensors.

Differential Revision: https://reviews.llvm.org/D153357

16 months ago[mlir][linalg] TileToForallOp: Support memref ops
Matthias Springer [Wed, 21 Jun 2023 07:10:45 +0000 (09:10 +0200)]
[mlir][linalg] TileToForallOp: Support memref ops

Support tiling of ops with memref semantics.

Differential Revision: https://reviews.llvm.org/D153353

16 months ago[libc] Support for riscv32
Petr Hosek [Fri, 9 Jun 2023 07:12:58 +0000 (07:12 +0000)]
[libc] Support for riscv32

This change adds basic support for baremetal riscv32 configuration.

Differential Revision: https://reviews.llvm.org/D152563

16 months ago[RISCV] Add errors for mixing Zcmp with C/Zcd and D.
Craig Topper [Wed, 21 Jun 2023 07:10:37 +0000 (00:10 -0700)]
[RISCV] Add errors for mixing Zcmp with C/Zcd and D.

We already had an error for Zcmt though it appears to be untested
Add similar one for Zcmp along with tests for both.

Factor the code to share the strings as much as possible.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D153159

16 months ago[mlir][Interfaces] TilingInterface: Add test case for linalg.copy on memrefs
Matthias Springer [Wed, 21 Jun 2023 06:51:24 +0000 (08:51 +0200)]
[mlir][Interfaces] TilingInterface: Add test case for linalg.copy on memrefs

Differential Revision: https://reviews.llvm.org/D153347

16 months ago[mlir][tensor][NFC] TilingInterface: Use Attribute instead of Value
Matthias Springer [Wed, 21 Jun 2023 06:47:06 +0000 (08:47 +0200)]
[mlir][tensor][NFC] TilingInterface: Use Attribute instead of Value

Minor cleanup to take full advantage of OpFoldResult.

Differential Revision: https://reviews.llvm.org/D153341

16 months ago[mlir][bufferization] Allow to_memref ops in One-Shot Analysis
Matthias Springer [Tue, 20 Jun 2023 15:53:44 +0000 (17:53 +0200)]
[mlir][bufferization] Allow to_memref ops in One-Shot Analysis

bufferization.to_memref ops are allowed in One-Shot Bufferize, but they are treated conservatively: in the absence of a memref analysis, we have to assume that the result buffer is read and written.

Note: to_memref cannot introduce any future aliases that would have to be considered during One-Shot Bufferize, because only to_tensor ops with the `restrict` attribute are supported. Such tensors are guaranteed to not alias with any other buffer after bufferization.

Differential Revision: https://reviews.llvm.org/D153365

16 months ago[DAG] Unroll and expand illegal result of LDEXP and POWI instead of widen.
tianleli [Wed, 21 Jun 2023 03:05:46 +0000 (11:05 +0800)]
[DAG] Unroll and expand illegal result of LDEXP and POWI instead of widen.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D153104

16 months ago[libc++][format] Adds formattable-with concept.
Mark de Wever [Sun, 16 Apr 2023 10:21:38 +0000 (12:21 +0200)]
[libc++][format] Adds formattable-with concept.

This change has a few additional effects:
- Abstract classes are now formattable.
- Volatile objects are no longer formattable.

Implements
- LWG3631 basic_format_arg(T&&) should use remove_cvref_t<T> throughout
- LWG3925 Concept formattable's definition is incorrect

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D152092