Mike Blumenkrantz [Fri, 2 Apr 2021 21:39:30 +0000 (17:39 -0400)]
zink: add a pipe_context::evaluate_depth_buffer hook
this works by flagging the next barrier to use the current sample locations
so that everything works as expected during decompression
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 21:36:28 +0000 (17:36 -0400)]
zink: update vk sample location info during framebuffer setup
this needs to be stored as a persistent thing on the ctx so it can be
reused without needing to be recalculated
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 21:35:36 +0000 (17:35 -0400)]
zink: add a util function for populating VkSampleLocationsInfoEXT
this will be reused
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 21:34:49 +0000 (17:34 -0400)]
zink: also flag sample_locations_changed if framebuffer samples changes
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 21:32:34 +0000 (17:32 -0400)]
zink: add a pipe_context::set_sample_locations hook
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 21:31:44 +0000 (17:31 -0400)]
zink; add a pipe_screen::get_sample_pixel_grid hook
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 21:31:13 +0000 (17:31 -0400)]
zink: set VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT on zs rts
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Mike Blumenkrantz [Fri, 2 Apr 2021 19:16:17 +0000 (15:16 -0400)]
zink: populate maxSampleLocationGridSize for all available sample sizes on init
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
Timur Kristóf [Wed, 9 Jun 2021 09:00:22 +0000 (11:00 +0200)]
amd: Add extra source to the mbcnt_amd NIR intrinsic.
The v_mbcnt instructions can take an extra source that they add to
the result. This is not exposed in SPIR-V but we now expose it in NIR.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:59:21 +0000 (21:59 +0200)]
ac/nir: Refactor and optimize the repacking sequence.
According to feedback, the terminology with "exclusive scan"
and "reduction" is difficult. Change it to use "repack" instead,
which better fits what this sequence is actually used for.
The new sequence stores only 1 byte / wave to LDS, and uses packed
instructions to produce the results. This has lower latency and
fewer instructions than what we previously had.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 20:08:45 +0000 (22:08 +0200)]
aco: Keep VGPR destinations for uniform shared loads when beneficial.
When the result of these loads is only used by cross-lane instructions,
it is beneficial to use a VGPR destination. This is because this allows
to put the s_waitcnt further down, which decreases latency.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:57:43 +0000 (21:57 +0200)]
aco: Implement byte and lane permute intrinsics.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:57:19 +0000 (21:57 +0200)]
nir: Add AMD-specific byte and lane permute intrinsics.
These map directly to v_perm_b32 and v_permlane_b32.
Unfortunately there is no corresponding NIR opcode or
intrinsics, and it's too tedious to puzzle these things
together from the existing NIR instructions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:56:50 +0000 (21:56 +0200)]
aco: Add validation for v_permlane instructions.
Previously there hasn't been any validation for these instructions,
but after shooting myself in the leg with it a few times, I decided
to add the validation now.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:56:13 +0000 (21:56 +0200)]
aco: Implement nir_op_sad_u8x4.
Fix up the operand size for v_sad instructions, and implement
the new NIR horizontal add. There is no viable way to do this
in SALU, so let's always use a VGPR destination.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:53:06 +0000 (21:53 +0200)]
nir: Add nir_op_sad_u8x4 which corresponds to AMD's v_sad_u8.
NIR currently doesn't have any intrinsics for a horizontal packed add,
so this one is modeled after AMD's v_sad_u8.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Timur Kristóf [Fri, 28 May 2021 19:52:31 +0000 (21:52 +0200)]
aco: Add note about v_alignbyte in the ISA README.
We tried to use this instruction for a more optimal sequence,
but it turned out that it doesn't exactly work as it was
supposed to. This note is to help others who want to use it.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
Michel Zou [Mon, 7 Jun 2021 06:46:47 +0000 (08:46 +0200)]
llvmpipe: restrict optim bug workaround to gcc 10.x
seems fixed in 11.x, see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3906
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11209>
Ilia Mirkin [Sat, 15 May 2021 22:30:14 +0000 (18:30 -0400)]
mesa: always expose NV_image_formats and OES_shader_image_atomic
As a result of some previous changes, it is now possible to expose ES
3.1 without having the ARB_shader_image_load_store enable set. However
we still want those other extensions. When there's a driver that's
capable of exposing ES 3.1 but not these extensions, more caps can be
added.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11204>
Hoe Hao Cheng [Thu, 3 Jun 2021 18:13:33 +0000 (02:13 +0800)]
zink: remove variable length arrays in ntv
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11171>
Mike Blumenkrantz [Fri, 21 May 2021 10:20:56 +0000 (06:20 -0400)]
util/prim_restart: simplify util_draw_vbo_without_prim_restart a bit
by initilizing variables up front and using actual draw structs for the
rewrite, a multidraw can be passed to the driver
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
Mike Blumenkrantz [Fri, 21 May 2021 10:23:18 +0000 (06:23 -0400)]
util/prim_restart: update index bounds before draws in util_draw_vbo_without_prim_restart
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
Mike Blumenkrantz [Fri, 21 May 2021 10:05:53 +0000 (06:05 -0400)]
util/prim_restart: store the total index count when rewriting draws
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
Mike Blumenkrantz [Fri, 21 May 2021 10:02:18 +0000 (06:02 -0400)]
util/prim_restart: store index bounds while rewriting draws
may as well
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
Mike Blumenkrantz [Fri, 21 May 2021 09:57:17 +0000 (05:57 -0400)]
util/prim_restart: pre-trim degenerate primitives during draw rewrite
these will be eliminated by drivers anyway
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
Mike Blumenkrantz [Fri, 21 May 2021 09:49:30 +0000 (05:49 -0400)]
util/prim_restart: assert the index size at the start of the function
this lets it be removed from the macro loop
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
Rhys Perry [Tue, 1 Jun 2021 12:41:18 +0000 (13:41 +0100)]
aco: use ds_read_{u8,u16}_d16
This allows partial writes and writes to the upper half of the destination.
fossil-db (Sienna Cichlid):
Totals from 135 (0.09% of 149839) affected shaders:
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
Rhys Perry [Tue, 1 Jun 2021 12:39:56 +0000 (13:39 +0100)]
aco: don't ever widen 8/16-bit sgpr load_shared
Doesn't seem to create incorrect code, but it is suboptimal.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
Rhys Perry [Tue, 1 Jun 2021 10:20:00 +0000 (11:20 +0100)]
radv: improve LDS alignment check for load/store vectorization
Previously, this could vectorize two scalar 16-bit loads into a u8vec4
load.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
Rhys Perry [Mon, 31 May 2021 17:18:24 +0000 (18:18 +0100)]
aco: use v1b/v2b for ds_read_u8/ds_read_u16
The p_extract_vector isn't necessary.
For ds_read_u8 and ds_read_u16, we used a 32-bit regclass, but did't load
32 bits, and used dst_hint for vector loads when we shouldn't have.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4863
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
Samuel Pitoiset [Tue, 8 Jun 2021 15:02:11 +0000 (17:02 +0200)]
ci: update list of expected failures for Pitcairn/Oland (RADV)
The robustness2 failures were a mistake because they are actually
not supported (no VK_EXT_scalar_block_layout on GFX6).
The sparse related failures are no longer supported since sparse
is only enabled for Polaris10+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11243>
Samuel Pitoiset [Tue, 8 Jun 2021 16:06:46 +0000 (18:06 +0200)]
aco: fix emitting literal offsets with SMEM on GFX7
When the offset is negative, reg() isn't 255. Fix this by splitting
SGPR and literal emission. While we are at it, adjust a comment
saying that literals are also accepted on GFX6 which is wrong.
Fixes another batch of robustness tests.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11247>
Daniel Stone [Wed, 9 Jun 2021 07:15:52 +0000 (08:15 +0100)]
ci/zink: Skip flaky GLX test
!11218 definitely didn't change anything about Zink that should make it
read black back from GLX. Assuming it's a race somewhere, just add it to
skips and move on.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11256>
Samuel Pitoiset [Thu, 27 May 2021 09:12:04 +0000 (11:12 +0200)]
radv: dump SPIR-V instead of using spirv-dis when generating a hang report
Useful when spirv-dis isn't found.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11034>
Georg Lehmann [Mon, 7 Jun 2021 11:27:52 +0000 (13:27 +0200)]
radv: Implement VK_EXT_global_priority_query.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11215>
Georg Lehmann [Mon, 7 Jun 2021 10:46:48 +0000 (12:46 +0200)]
vulkan: Update the XML and headers to 1.2.180
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11215>
Paulo Zanoni [Wed, 7 Apr 2021 00:15:21 +0000 (17:15 -0700)]
iris: finish converting from drmIoctl to intel_ioctl
Only 3 remaining users. The implementations are exactly the same.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11194>
Caio Marcelo de Oliveira Filho [Thu, 29 Apr 2021 22:12:24 +0000 (15:12 -0700)]
nir/gather_info: Rename per_vertex to is_arrayed
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
Caio Marcelo de Oliveira Filho [Thu, 29 Apr 2021 21:50:06 +0000 (14:50 -0700)]
nir/lower_io: Rename vertex_index to array_index in helpers
The helpers will be reused for per-primitive variables that are also
arrayed, so use a more general name.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
Samuel Pitoiset [Mon, 7 Jun 2021 13:19:59 +0000 (15:19 +0200)]
aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7
GFX6-7 are affected by a hw bug that prevents address clamping to work
correctly when the SGPR offset is used. Use the VGPR offset to fix it.
Fixes various hangs with dEQP-VK.robustness.robustness2.* on Bonaire.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11238>
Tomeu Vizoso [Wed, 9 Jun 2021 05:33:26 +0000 (07:33 +0200)]
ci: Disable windows builds due to runner not being available
Warning from Gitlab:
This job is stuck because you don't have any active runners online or
available with any of these tags assigned to them: windows shell 1809
mesa
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
Alyssa Rosenzweig [Mon, 7 Jun 2021 17:59:26 +0000 (13:59 -0400)]
nir/lower_fragcolor: Avoid redundant load_output
At best, this is an extra instruction for NIR to optimize out. At worst,
depending on pass ordering nir_load_output could sneak into the final
NIR, even on drivers that don't support fbfetch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
Alyssa Rosenzweig [Tue, 8 Jun 2021 23:46:12 +0000 (19:46 -0400)]
ci: Disable the iris APL jobs
Someone's cat is chewing on the Ethernet adaptor.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
Rob Clark [Sun, 18 Apr 2021 16:10:07 +0000 (09:10 -0700)]
freedreno/ir3: Fix use after free
If the tex/sfu ssa src is from a different block than the one currently
being scheduled, we do not have a valid sched-node. So fallback to
previous behavior rather than dereference an invalid ptr.
Fixes:
7821e5a3f8d ("ir3/sched: Don't penalize uses of already-waited tex/SFU")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10306>
Jason Ekstrand [Tue, 8 Jun 2021 14:22:44 +0000 (09:22 -0500)]
anv/blorp: Optimize addresses/relocations when ANV_ALWAYS_SOFTPIN
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 14:25:57 +0000 (09:25 -0500)]
anv: Optimize anv_address_physical when ANV_ALWAYS_SOFTPIN
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 14:15:09 +0000 (09:15 -0500)]
anv: Fast-path surface relocs when we have softpin
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 01:16:07 +0000 (20:16 -0500)]
anv: Make anv_batch_emit_reloc inline and optimize SKL+
This should drop the CPU overhead of processing buffers on SKL+ by
dropping some of the logic contained in anv_reloc_list_add() whenever we
have enough compile-time information to know we have softpin.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Fri, 7 Aug 2020 03:46:12 +0000 (22:46 -0500)]
anv: Add a helper to add a BO to the batch list without a reloc
The relocation list currently serves two purposes. One is for
relocations on older non-softpin platforms. The second is to keep track
of driver-managed BOs which are used by the given command buffer. We
going to need a mechanism to add BOs to the command buffer without doing
a relocation into the batch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 01:02:22 +0000 (20:02 -0500)]
anv: Handle OOM in the pinned path in anv_reloc_list_add
Fixes:
b3c0b1b21880 "anv: Use a bitset for tracking residency"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Tue, 8 Jun 2021 00:53:42 +0000 (19:53 -0500)]
anv: Make use_softpin compile-time in genX code
Whenever we have the GFX_VERx10 macro available, we can make use_softpin
a compile-time thing for everything but Broadwell and Cherryview. This
should save us some CPU cycles especially on SKL+.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Jason Ekstrand [Fri, 3 Apr 2020 13:17:43 +0000 (08:17 -0500)]
anv: Require softpin on Gen8+
Softpin was added to i915 in
commit
506a8e87d8d2746b9e9d2433503fe237c54e4750
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Dec 8 11:55:07 2015 +0000
drm/i915: Add soft-pinning API for execbuffer
which was included in Linux 4.5. It's been over 5 years so it's
probably reasonable to make it a hard requirement.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
Caio Marcelo de Oliveira Filho [Mon, 7 Jun 2021 21:17:12 +0000 (14:17 -0700)]
anv: Support workgroup memory in other shaders
Mesh and Task shaders can use workgroup memory, so generalize its
handling in anv by moving it from anv_pipeline_compile_cs() to
anv_pipeline_lower_nir().
Update Pipeline Statistics accordingly.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11230>
Caio Marcelo de Oliveira Filho [Wed, 5 May 2021 19:24:44 +0000 (12:24 -0700)]
nir: Move workgroup_size and workgroup_variable_size into common shader_info
Move it out the "cs" sub-struct, since these will be used for other
shader stages in the future.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
Caio Marcelo de Oliveira Filho [Wed, 5 May 2021 16:34:46 +0000 (09:34 -0700)]
nir: Move zero_initialize_shared_memory into common shader_info
Move it out the "cs" sub-struct, since the bit will be used for other
shader stages in the future.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
Mike Blumenkrantz [Tue, 8 Jun 2021 15:23:43 +0000 (11:23 -0400)]
zink: more accurately handle shader layer/viewport caps
the spirv extension is required for spirv < 1.5, but the core cap should
be used for spirv >= 1.5
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11244>
Tony Wasserka [Thu, 27 May 2021 11:16:01 +0000 (13:16 +0200)]
aco/ra: Split print_regs by lines of 64 registers
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10517>
Tony Wasserka [Thu, 29 Apr 2021 10:18:24 +0000 (12:18 +0200)]
aco/ra: Clean up print_regs output and support byte-allocated variables
Example output:
00 03 06 09 12 15 18 21 24 27 30 33 36 39 42
sgprs: ·▉█▉███▉▉█··████···········▉████············
00 03 06 09 12 15 18 21 24 27 30 33 36 39 42
vgprs: ▉▉··▉▉▉▉▘▀▉▉▉···▉▘▘▉▉▉▉···▉▉▉▀▀▉············
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10517>
Tony Wasserka [Thu, 29 Apr 2021 16:06:53 +0000 (18:06 +0200)]
aco/ra: Fix off-by-one-error in print_regs
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
3675aefa84e ("aco/ra: Fix build with print_regs enabled")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10517>
Boyuan Zhang [Tue, 8 Jun 2021 00:33:43 +0000 (20:33 -0400)]
frontends/omx: use pipe buffer map instead of texture map
Fixes:
eb74f9776 ("gallium: split transfer_(un)map into buffer_(un)map and texture_(un)map")
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11233>
Leo Liu [Sat, 5 Jun 2021 23:34:40 +0000 (19:34 -0400)]
frontends/va: use the entrypoint from context instead of the hard-coded one
It could fail the case where this is only encode available.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 23:31:34 +0000 (19:31 -0400)]
frontends/va: include the profile queries for encoder as well
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 23:29:08 +0000 (19:29 -0400)]
frontends/va: use the correct entrypoint to get config attributes
PIPE_VIDEO_ENTRYPOINT_ENCODE should be used in this case.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 22:46:58 +0000 (18:46 -0400)]
radeonsi: separate video hw info based on HW engine individually
This removes previous "has_hw_decode" and "uvd_enc_supported" and
makes information more accuate for cases where HW decode, HW encode,
and HW JPEG decode might partially available.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Leo Liu [Sat, 5 Jun 2021 21:03:32 +0000 (17:03 -0400)]
radeonsi: add PIPE_FORMAT_P010 for HEVC Main10 profile to encode param
The format can be queried through the encode entrypoint
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
Bas Nieuwenhuizen [Mon, 7 Jun 2021 00:50:09 +0000 (02:50 +0200)]
nir/lower_returns: Deal with single-arg phis after if.
if we have
if ... {
return;
} else {
// block X
}
// block Y
phi(X: ...)
then nir_lower_returns tries to move block Y into the else body,
except nir_cf_extract doesn't move the phi. As the return is removed
in the then-body the phi suddenly has the wrong number of arguments
(and the phi doesn't dominate its uses anymore).
In this case we know that the phi has to be single arg, so we can just
rewrite the users of the phis and drop them.
Hit this in my RT adventures, not sure if this is actually reachable
right now, as single arg phis tend to be kind of exceptional outside
of CSSA and we typically call nir_lower_returns pretty early.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11207>
Hubert Jasudowicz [Tue, 8 Jun 2021 09:09:03 +0000 (11:09 +0200)]
docs/egl: Add missing backticks
Signed-off-by: Hubert Jasudowicz <hubert.jasudowicz@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11240>
Juan A. Suarez Romero [Mon, 7 Jun 2021 12:19:33 +0000 (14:19 +0200)]
broadcom/ci: Report flakes on IRC
Report flakes in #videocore-ci channel.
v2 (Emma):
- Add glx@glx_arb_sync_control@timing.* as flakes.
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11220>
Juan A. Suarez Romero [Mon, 7 Jun 2021 09:11:42 +0000 (11:11 +0200)]
ci/v3dv: test v3dv in arm64 environment
As most of the development is done in arm64, execute the v3dv related
tests in this environment.
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11220>
Juan A. Suarez Romero [Fri, 4 Jun 2021 17:04:59 +0000 (19:04 +0200)]
ci/broadcom: unset manual jobs
Make some of the jobs for vc4 and v3d to run automatically, in order to
identify more regressions.
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11220>
Samuel Pitoiset [Mon, 7 Jun 2021 05:56:19 +0000 (07:56 +0200)]
ac/debug: fix color printing PKT3 when count in header is too low
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11211>
Rhys Perry [Mon, 3 Feb 2020 15:22:11 +0000 (15:22 +0000)]
aco/tests: add SDWA tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Fri, 14 Aug 2020 15:12:55 +0000 (16:12 +0100)]
aco/tests: add tests for p_extract/p_insert lowering
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Fri, 23 Apr 2021 10:56:18 +0000 (11:56 +0100)]
aco: disallow literals with some instruction formats
Because isVOPn() is true for many VOP3, SDWA and DPP instructions, this
would often not complain.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 7 Oct 2020 13:35:21 +0000 (14:35 +0100)]
aco: make validate_ir() output usable in tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:23:56 +0000 (14:23 +0100)]
aco: optimize 32-bit extracts and inserts using SDWA
Still need to use dst_u=preserve field to optimize packs
fossil-db (Sienna Cichlid):
Totals from 15974 (10.66% of 149839) affected shaders:
VGPRs: 1009064 -> 1008968 (-0.01%); split: -0.03%, +0.02%
SpillSGPRs: 7959 -> 7964 (+0.06%)
CodeSize:
101716436 ->
101159568 (-0.55%); split: -0.55%, +0.01%
MaxWaves: 284464 -> 284490 (+0.01%); split: +0.02%, -0.01%
Instrs:
19334216 ->
19224241 (-0.57%); split: -0.57%, +0.00%
Latency:
375465295 ->
375230478 (-0.06%); split: -0.14%, +0.08%
InvThroughput:
79006105 ->
78860705 (-0.18%); split: -0.25%, +0.07%
fossil-db (Polaris):
Totals from 11369 (7.51% of 151365) affected shaders:
SGPRs: 787920 -> 787680 (-0.03%); split: -0.04%, +0.01%
VGPRs: 681056 -> 681040 (-0.00%); split: -0.01%, +0.00%
CodeSize:
68127288 ->
67664120 (-0.68%); split: -0.69%, +0.01%
MaxWaves: 54370 -> 54371 (+0.00%)
Instrs:
13294638 ->
13214109 (-0.61%); split: -0.62%, +0.01%
Latency:
373515759 ->
373214571 (-0.08%); split: -0.11%, +0.03%
InvThroughput:
166529524 ->
166275291 (-0.15%); split: -0.20%, +0.05%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 28 Oct 2020 13:32:55 +0000 (13:32 +0000)]
radv: use byte/word extract/insert instructions
ACO doesn't yet combine extract/insert into instructions, but it seems to
already generate less instructions because NIR optimizes shift+and to
these instructions. Code size is worse in some cases though because we
have to always use a literal when masking.
fossil-db (Sienna Cichlid):
Totals from 14361 (9.58% of 149839) affected shaders:
VGPRs: 850152 -> 850304 (+0.02%); split: -0.02%, +0.04%
SpillSGPRs: 7979 -> 7989 (+0.13%); split: -0.03%, +0.15%
CodeSize:
88031216 ->
88162520 (+0.15%); split: -0.01%, +0.16%
MaxWaves: 269414 -> 269426 (+0.00%)
Instrs:
16695182 ->
16662852 (-0.19%); split: -0.21%, +0.01%
Latency:
375592693 ->
375544364 (-0.01%); split: -0.04%, +0.03%
InvThroughput:
75627700 ->
75607720 (-0.03%); split: -0.07%, +0.04%
fossil-db (Polaris):
Totals from 13816 (9.13% of 151365) affected shaders:
SGPRs: 984896 -> 982512 (-0.24%); split: -0.29%, +0.05%
VGPRs: 809220 -> 809112 (-0.01%); split: -0.02%, +0.01%
SpillSGPRs: 9181 -> 9185 (+0.04%); split: -0.04%, +0.09%
CodeSize:
82017952 ->
82123484 (+0.13%); split: -0.01%, +0.14%
MaxWaves: 65721 -> 65723 (+0.00%)
Instrs:
16008744 ->
15988007 (-0.13%); split: -0.18%, +0.05%
Latency:
439911623 ->
439869622 (-0.01%); split: -0.04%, +0.03%
InvThroughput:
185898770 ->
185841742 (-0.03%); split: -0.08%, +0.05%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 28 Oct 2020 13:32:25 +0000 (13:32 +0000)]
ac/llvm: implement byte/word extract/insert instructions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:35:15 +0000 (14:35 +0100)]
aco: use byte/word extract pseudo-instructions
fossil-db (Sienna Cichild):
Totals from 1890 (1.26% of 149839) affected shaders:
CodeSize: 5104196 -> 5104300 (+0.00%); split: -0.00%, +0.01%
Latency:
11572943 ->
11572880 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 4876941 -> 4876982 (+0.00%); split: -0.00%, +0.00%
SClause: 26774 -> 26775 (+0.00%)
Copies: 125778 -> 125813 (+0.03%)
PreSGPRs: 56452 -> 56451 (-0.00%)
fossil-db (Polaris):
Totals from 1884 (1.24% of 151365) affected shaders:
CodeSize: 3849340 -> 3849312 (-0.00%); split: -0.00%, +0.00%
Instrs: 741391 -> 741382 (-0.00%)
Latency:
13533815 ->
13533439 (-0.00%)
InvThroughput:
12058777 ->
12058500 (-0.00%)
Copies: 120890 -> 120891 (+0.00%)
PreSGPRs: 48940 -> 48939 (-0.00%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:35:15 +0000 (14:35 +0100)]
aco: implement nir_op_extract/nir_op_insert
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 12 Aug 2020 13:35:15 +0000 (14:35 +0100)]
aco: add p_extract/p_insert
These will let us make the SDWA optimizer much simpler than if we were to
recognize combinations of shift/and/bfe.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Mon, 7 Jun 2021 15:56:45 +0000 (16:56 +0100)]
aco: disallow SDWA for instructions with 64-bit definitions/operands
For example, v_cvt_f64_i32. LLVM doesn't seem to allow this either and it
doesn't seem to work correctly.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Wed, 25 Mar 2020 15:38:06 +0000 (15:38 +0000)]
nir, nir/algebraic: add byte/word insertion instructions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Rhys Perry [Fri, 3 Apr 2020 13:41:38 +0000 (14:41 +0100)]
nir/algebraic: optimize extract of extract
Found in some sottr shaders (originally iand(ishr(a, 16), 0xffff))
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
Samuel Pitoiset [Mon, 7 Jun 2021 05:40:54 +0000 (07:40 +0200)]
radv: emit PA_SC_CONSERVATIVE_RASTERIZATION_CNTL only on GFX9+
This context register doesn't exist on older generations.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11210>
Dave Airlie [Tue, 4 May 2021 04:05:10 +0000 (14:05 +1000)]
intel/isl: add blend enable flag to gen4/5
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
Dave Airlie [Sun, 6 Jun 2021 19:28:07 +0000 (05:28 +1000)]
intel/isl: add levels and minimum array element to null fill
gen4/5 needs these to avoid gpu hangs around matching depth/null
surfaces
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
Dave Airlie [Sun, 6 Jun 2021 19:26:05 +0000 (05:26 +1000)]
intel/isl: convert null surface fill to a struct.
Suggested by Jason, pre-convert this to a struct so it can
be expanded for gen4/5 crocus support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
Dave Airlie [Tue, 8 Jun 2021 00:00:20 +0000 (10:00 +1000)]
intel/isl: decrease isl_format_layouts size by 36k
This drops
-
0000000000011e90 R isl_format_layouts
+
0000000000008f48 R isl_format_layouts
I think that's about 36k.
Thanks to Jason for suggesting PACKED
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11232>
Yiwei Zhang [Thu, 3 Jun 2021 20:46:08 +0000 (20:46 +0000)]
venus: forward the host renderer hardware info
Some game engines rely on the real hardware info to adjust default
graphics quality and other attributes.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11175>
Caio Marcelo de Oliveira Filho [Fri, 4 Jun 2021 19:04:15 +0000 (12:04 -0700)]
nir: Rename WORK_GROUP (and similar) to WORKGROUP
Be consistent with other usages in Vulkan and SPIR-V, and the recently
added workgroup_size field.
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Caio Marcelo de Oliveira Filho [Thu, 27 May 2021 21:44:54 +0000 (14:44 -0700)]
nir: Rename nir_intrinsic_load_local_group_size to nir_intrinsic_load_workgroup_size
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Caio Marcelo de Oliveira Filho [Thu, 27 May 2021 21:39:03 +0000 (14:39 -0700)]
compiler: Rename SYSTEM_VALUE_LOCAL_GROUP_SIZE to SYSTEM_VALUE_WORKGROUP_SIZE
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Caio Marcelo de Oliveira Filho [Thu, 27 May 2021 06:53:32 +0000 (23:53 -0700)]
compiler: Rename local_size to workgroup_size
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
Emma Anholt [Mon, 7 Jun 2021 18:51:21 +0000 (11:51 -0700)]
i915g: Make sure we don't try to texture from the const file.
It's an invalid value for the texture coordinate source, and this becomes
more common if we enable nir-to-tgsi.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11227>
Emma Anholt [Mon, 7 Jun 2021 19:44:50 +0000 (12:44 -0700)]
ci/i915g: Fix incorrect expectation.
I think this was an edit failure on my part when fixing up the
expectations for merge.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11227>
Timur Kristóf [Mon, 31 May 2021 15:46:19 +0000 (17:46 +0200)]
radv: Assert that there is no GS copy shader when the pipeline has NGG.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11092>
Timur Kristóf [Mon, 31 May 2021 15:43:23 +0000 (17:43 +0200)]
radv: Don't generate GS copy shader when the pipeline has NGG.
Previously the code used radv_pipeline_has_ngg but that always
returned false because the pipeline->shaders was all NULL at the
time when the GS copy shader was created.
Fixes:
ca783612e721bc66af545075d76dc578ddbf7666
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11092>
Timur Kristóf [Mon, 31 May 2021 15:42:46 +0000 (17:42 +0200)]
radv: Remove duplicate code for getting GS info.
This was my mistake for forgetting to delete this code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11092>
Alejandro Piñeiro [Fri, 23 Apr 2021 10:21:29 +0000 (12:21 +0200)]
v3d/simulator: get rid of has_gca wrapper
We can assume that it is always present on 3.3 and below. In fact,
recent updates of the simulator will remove it, so this change would
be needed soon.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11040>
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