Gert Wollny [Thu, 12 May 2022 11:28:15 +0000 (13:28 +0200)]
r600/sb: Fall back to un-optimized shader if scheduling fails
Sometimes the optimizer created codes that can't be scheduled,
instead of failing completely, simply bail out and use the
un-optimized code.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16499>
Gert Wollny [Tue, 10 May 2022 18:04:09 +0000 (20:04 +0200)]
r600/sb: Don't create three source ops with all kcache values
There is a good chance that the created instruction can't be
scheduled, so avoid this case.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16499>
Jason Ekstrand [Fri, 25 Mar 2022 21:14:19 +0000 (16:14 -0500)]
radv: Use vk_image_view as the base for radv_image_view
I've left the extent field because, even though it looks like it should
be roughly equivalent, it's weirdly different on different hardware and
I didn't want to mess with it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Fri, 25 Mar 2022 19:58:39 +0000 (14:58 -0500)]
radv: Use vk_image as the base for radv_image
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Fri, 25 Mar 2022 23:56:38 +0000 (18:56 -0500)]
radv: Only use PLANE_0 in meta when actually needed
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Fri, 25 Mar 2022 22:36:35 +0000 (17:36 -0500)]
vulkan,v3dv: Add a driver_internal flag to vk_image_view_init/create
We already had a little workaround for v3dv where, for some if its meta
ops, it had to bind a depth/stenicil image as color. Instead of
special-casing binding depth/stencil as color, let's flip on the
drier_internal flag and get rid of most of the checks in that case.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Sat, 26 Mar 2022 00:38:27 +0000 (19:38 -0500)]
v3dv: Drop the region temporary from blit_shader
We're no longer stomping aspects, so there's no need.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Sat, 26 Mar 2022 00:35:17 +0000 (19:35 -0500)]
v3dv: Don't use color aspects for depth/stencil images
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Sat, 26 Mar 2022 00:44:17 +0000 (19:44 -0500)]
vulkan: Only be clever about vk_image_view::view_format for normal views
For color view of depth views, just set whatever format they asked for.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Jason Ekstrand [Fri, 25 Mar 2022 22:57:37 +0000 (17:57 -0500)]
v3dv: Add a create_image_view helper for internal views
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
Samuel Pitoiset [Fri, 13 May 2022 09:19:21 +0000 (11:19 +0200)]
aco: use ac_is_llvm_processor_supported() for checking LLVM asm support
It seems more universal but it's needed to create a temporary TM.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16494>
Samuel Pitoiset [Mon, 16 May 2022 14:42:22 +0000 (16:42 +0200)]
radv: do not lower loading TESS/ESGS rings using the ABI for LLVM
LLVM uses an implicit argument for the ring offsets and this lowering
was just broken.
This fixes tessellation and geometry on all generations with LLVM.
Fixes:
896a55f47d9 ("radv: Lower ABI in NIR for tess/ESGS/NGG shader arguments.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16530>
Alyssa Rosenzweig [Sun, 15 May 2022 16:57:31 +0000 (12:57 -0400)]
asahi: Fix hangs waiting on the notification queue
Dequeue and WaitForAvailableData can race. Restructure the loop to avoid
this. Fixes all timeouts in dEQP.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16518>
Emma Anholt [Tue, 17 May 2022 14:07:35 +0000 (07:07 -0700)]
i915g/ci: Add depth-clear-precision-check xfails like everyone else.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
Emma Anholt [Thu, 12 May 2022 20:22:17 +0000 (13:22 -0700)]
ci/crocus: Merge the piglit runs with the deqp runs.
Fewer manual buttons to click.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
Emma Anholt [Sun, 8 May 2022 16:54:53 +0000 (09:54 -0700)]
ci/crocus: Manual CI updates after CI was down for a bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
Konstantin Seurer [Sun, 15 May 2022 10:52:58 +0000 (12:52 +0200)]
Revert "radv: Make fill_buffer_shader non-static"
We do not need this any longer since
radv_acceleration_structure.c uses
radv_fill_buffer now instead.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
Konstantin Seurer [Sun, 15 May 2022 10:46:11 +0000 (12:46 +0200)]
radv: Use radv_fill_buffer for accel struct builds
It turns out, that the fuchsia sort may actually
perform clears with size < 16 which hits an assert
in radv_fill_buffer_shader. This fixes random
crashes in Control.
Fixes: be57b08 ("radv: Build accaleration structures using LBVH")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
Konstantin Seurer [Sun, 15 May 2022 10:43:35 +0000 (12:43 +0200)]
radv: Allow radv_fill_buffer to work with VAs only
Makes the bo parameter optional which is useful
for the clears performed by acceleration structure
build commands.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
Marek Olšák [Mon, 16 May 2022 12:16:23 +0000 (08:16 -0400)]
Revert "mesa: consider the sample count when choosing a texture format"
This reverts commit
89c94502b6650fed222abd3588e9c927811580aa.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16524>
Marek Olšák [Mon, 16 May 2022 12:16:02 +0000 (08:16 -0400)]
Revert "frontend/dri: allow swapped BGR->RGB channel order for MSAA color buffers"
This reverts commit
cfec9a55ea6a1cd535ea60aeff7f7bd85dd64bb5.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16524>
Marek Olšák [Fri, 13 May 2022 08:09:37 +0000 (04:09 -0400)]
radeonsi: fix resource_copy_region with ETC formats (e.g. for Stoney)
Only Stoney, Vega10, Raven, and Raven2 support ETC.
Fixed tests:
dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16i.texture2d_to_texture2d
dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16ui.texture2d_to_texture2d
dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16i.texture2d_to_texture2d
dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16ui.texture2d_to_texture2d
Fixes:
cf1e562fdd7 - radeonsi: remove compressed and subsampled gfx copy from resource_copy_region
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6431
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16491>
Dave Airlie [Tue, 3 May 2022 00:33:02 +0000 (10:33 +1000)]
llvmpipe: align scratch size to 64-bit size.
This fixes a crash with luxmark where it uses a 12-byte scratch space,
but when llvmpipe allocates it for 8 lanes, it isn't properly aligned
for 64-bit.
Karol found this debugging rusticl.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16288>
Marek Olšák [Sun, 15 May 2022 01:16:31 +0000 (21:16 -0400)]
winsys/amdgpu: initialize IB_PREAMBLE in advance
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sun, 15 May 2022 00:51:47 +0000 (20:51 -0400)]
radeonsi: move CS preamble emission into the winsys
The preamble will be skipped by the kernel if there is no context switch.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 14:23:05 +0000 (10:23 -0400)]
radeonsi: merge all preamble states into one
Tess registers are appended. GS registers are appended or overwritten
if they are already set. There are separate TMZ and non-TMZ preambles.
The preamble will be passed to the kernel as an IB to execute on a context
switch only.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 11:23:13 +0000 (07:23 -0400)]
radeonsi/gfx11: optimize attribute stores
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 09:55:29 +0000 (05:55 -0400)]
radeonsi/gfx11: fix VM faults due to the attribute ring
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 07:55:34 +0000 (03:55 -0400)]
Revert "radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order"
This reverts commit
54d85700a12aa33d185e147c2d5c794ba54b7a11.
It's an LLVM bug. If you disable AMDGPUImageIntrinsicOptimizer in LLVM,
MSAA is fixed. There is no LLVM command line option to disable it from Mesa.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 06:33:30 +0000 (02:33 -0400)]
radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 06:19:56 +0000 (02:19 -0400)]
radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU
GS_PIPELINE_STATS_EMU is always false, so the branches were never entered.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 02:34:17 +0000 (22:34 -0400)]
radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export
We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 02:04:05 +0000 (22:04 -0400)]
ac/gfx11: fix the scratch buffer
We didn't use the value that we computed.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Wed, 11 May 2022 07:50:03 +0000 (03:50 -0400)]
radeonsi: remove GFX9_MERGED_NUM_USER_SGPR definition
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Marek Olšák [Sat, 14 May 2022 06:21:30 +0000 (02:21 -0400)]
ac/gpu_info: silence a valgrind warning due to amdgpu_query_hw_ip_info
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Samuel Pitoiset [Thu, 5 May 2022 13:15:17 +0000 (15:15 +0200)]
radv: more register changes on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 12:18:51 +0000 (14:18 +0200)]
radv: limit CP DMA to max 32KB sizes on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 12:06:43 +0000 (14:06 +0200)]
radv: apply a workaround for CB perf counters on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Wed, 4 May 2022 23:40:34 +0000 (01:40 +0200)]
radv: update the initialization of SGPR0/1 registers for HS and GS on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 11:23:06 +0000 (13:23 +0200)]
radv: update VRS registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 11:11:56 +0000 (13:11 +0200)]
radv: update TF_RING_size to a per-SE size on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 10:10:13 +0000 (12:10 +0200)]
radv: do not emit FLUSH_AND_INV_DB_META on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 10:04:26 +0000 (12:04 +0200)]
radv: do not emit non-existent CP_COHER_START_DELAY on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 10:01:36 +0000 (12:01 +0200)]
radv: configure DB_RENDER_CONTROL on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 09:45:56 +0000 (11:45 +0200)]
radv: use PIXEL_PIPE_STATE_DUMP event instead of ZPASS_DONE on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 09:28:52 +0000 (11:28 +0200)]
radv: update image descriptor registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 09:28:40 +0000 (11:28 +0200)]
radv: update buffer descriptor registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Thu, 5 May 2022 09:22:32 +0000 (11:22 +0200)]
radv: update sampler registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Thu, 5 May 2022 00:55:58 +0000 (02:55 +0200)]
radv: Disable transform feedback for gfx11.
Until we implement it.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Thu, 5 May 2022 00:37:57 +0000 (02:37 +0200)]
radv: Add gfx11 DCC fast clear support.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Wed, 4 May 2022 23:38:11 +0000 (01:38 +0200)]
radv: Adjust for new SWIZZLE_ENABLE.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Thu, 5 May 2022 11:21:16 +0000 (13:21 +0200)]
radv: gfx11 register changes.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Wed, 4 May 2022 19:48:12 +0000 (21:48 +0200)]
radv: Mark all formats as DCC compatible with each other on gfx11.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Bas Nieuwenhuizen [Wed, 4 May 2022 19:44:18 +0000 (21:44 +0200)]
radv: always enable NGG on GFX11
The legacy path is removed.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Wed, 4 May 2022 15:55:09 +0000 (17:55 +0200)]
radv: update scratch buffer registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Wed, 4 May 2022 15:52:20 +0000 (17:52 +0200)]
radv: use the new format table on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Samuel Pitoiset [Fri, 6 May 2022 09:16:49 +0000 (11:16 +0200)]
radv: do not align VGPRS to 8 or 16 on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
Tomeu Vizoso [Tue, 17 May 2022 08:30:50 +0000 (10:30 +0200)]
panvk/ci: Disable CI for a while
We have been hitting OOM conditions quite often and this is making ti
hard to get stuff merged.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
Tomeu Vizoso [Tue, 17 May 2022 08:28:16 +0000 (10:28 +0200)]
lima/ci: Disable lima-mali450-piglit-gpu:arm64
Due to a kernel regression, these jobs fail most of the time with the
backtrace below.
Disable while we get a fix in our kernel.
2022-05-17 08:00:15.428691: [ 374.755841] ------------[ cut here ]------------
2022-05-17 08:00:15.428778: [ 374.755883] kernel BUG at kernel/irq_work.c:235!
2022-05-17 08:00:15.429011: [ 374.759409] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
2022-05-17 08:00:15.429077: [ 374.764842] Modules linked in: ipv6
2022-05-17 08:00:15.429233: [ 374.768294] CPU: 3 PID: 18210 Comm: vp-bad-program Not tainted 5.16.12linux-v5.16-for-mesa-ci-
991fec6622591.tar.bz2 #1
2022-05-17 08:00:15.429386: [ 374.778900] Hardware name: Libre Computer AML-S805X-AC (DT)
2022-05-17 08:00:15.429536: [ 374.784421] pstate:
60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
2022-05-17 08:00:15.429714: [ 374.791320] pc : irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.429780: [ 374.795546] lr : irq_work_run+0x38/0x50
2022-05-17 08:00:15.429927: [ 374.799342] sp :
ffff80000801bf30
2022-05-17 08:00:15.430097: [ 374.802618] x29:
ffff80000801bf30 x28:
ffff000003398e00 x27:
ffff00000ed3e400
2022-05-17 08:00:15.430158: [ 374.809691] x26:
ffff800009678750 x25:
ffff0000030d8900 x24:
ffff800008846fa0
2022-05-17 08:00:15.430316: [ 374.816763] x23:
ffff800009909f80 x22:
0000000000000006 x21:
ffff00000101e780
2022-05-17 08:00:15.430411: [ 374.823836] x20:
ffff800009d7c408 x19:
ffff8000099089c8 x18:
0000000000000000
2022-05-17 08:00:15.430547: [ 374.830908] x17:
ffff8000252e9000 x16:
ffff80000801c000 x15:
0000000000004000
2022-05-17 08:00:15.430735: [ 374.837981] x14:
0000000000000000 x13:
0000000000000000 x12:
0000000000000001
2022-05-17 08:00:15.430797: [ 374.845054] x11:
0000000000000001 x10:
ffff8000252e9000 x9 :
ffff00002ebf90e0
2022-05-17 08:00:15.430962: [ 374.852126] x8 :
fffffc00000eda08 x7 :
ffff000003398e00 x6 :
0000000000001000
2022-05-17 08:00:15.431029: [ 374.859199] x5 :
0000000000000000 x4 :
ffff00002ebfc910 x3 :
ffff00000ed3e430
2022-05-17 08:00:15.431194: [ 374.866271] x2 :
0000000000000000 x1 :
0000000000000000 x0 :
ffff00002ebf19c8
2022-05-17 08:00:15.431261: [ 374.873345] Call trace:
2022-05-17 08:00:15.431409: [ 374.875761] irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.431557: [ 374.879641] ipi_handler+0x98/0x15c
2022-05-17 08:00:15.431726: [ 374.883091] handle_percpu_devid_irq+0x88/0x140
2022-05-17 08:00:15.431795: [ 374.887576] generic_handle_domain_irq+0x40/0x60
2022-05-17 08:00:15.431958: [ 374.892147] gic_handle_irq+0x48/0xd0
2022-05-17 08:00:15.432025: [ 374.895769] call_on_irq_stack+0x2c/0x60
2022-05-17 08:00:15.432211: [ 374.899651] do_interrupt_handler+0x80/0x84
2022-05-17 08:00:15.432364: [ 374.903791] el1_interrupt+0x34/0x84
2022-05-17 08:00:15.432432: [ 374.907327] el1h_64_irq_handler+0x1c/0x30
2022-05-17 08:00:15.432616: [ 374.911380] el1h_64_irq+0x78/0x7c
2022-05-17 08:00:15.432764: [ 374.914744] irq_work_queue+0x70/0x80
2022-05-17 08:00:15.432832: [ 374.918367] drm_sched_entity_fini+0x290/0x320
2022-05-17 08:00:15.433043: [ 374.922766] lima_sched_context_fini+0x18/0x24
2022-05-17 08:00:15.433161: [ 374.927164] lima_ctx_free+0x7c/0x114
2022-05-17 08:00:15.433228: [ 374.930787] lima_ioctl_ctx_free+0x28/0x40
2022-05-17 08:00:15.433362: [ 374.934840] drm_ioctl_kernel+0xc4/0x170
2022-05-17 08:00:15.433522: [ 374.938721] drm_ioctl+0x21c/0x440
2022-05-17 08:00:15.433587: [ 374.942085] __arm64_sys_ioctl+0xac/0xf0
2022-05-17 08:00:15.433748: [ 374.945966] invoke_syscall+0x48/0x114
2022-05-17 08:00:15.433814: [ 374.949675] el0_svc_common.constprop.0+0x44/0xec
2022-05-17 08:00:15.433977: [ 374.954332] do_el0_svc+0x28/0x90
2022-05-17 08:00:15.434041: [ 374.957609] el0_svc+0x20/0x60
2022-05-17 08:00:15.434204: [ 374.960629] el0t_64_sync_handler+0x1a8/0x1b0
2022-05-17 08:00:15.434269: [ 374.964941] el0t_64_sync+0x1a0/0x1a4
2022-05-17 08:00:15.434492: [ 374.968568] Code:
a8c27bfd d50323bf d65f03c0 d65f03c0 (
d4210000)
2022-05-17 08:00:15.434612: [ 374.974607] ---[ end trace
74ef9d6ff9457a3f ]---
2022-05-17 08:00:15.434676: [ 374.979174] Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt
2022-05-17 08:00:15.434888: [ 374.986505] SMP: stopping secondary CPUs
2022-05-17 08:00:15.435011: [ 374.990391] Kernel Offset: 0x80000 from 0xffff800008000000
2022-05-17 08:00:15.435079: [ 374.995818] PHYS_OFFSET: 0x0
2022-05-17 08:00:15.435243: [ 374.998665] CPU features: 0x00,
00004802,
00000846
2022-05-17 08:00:15.435313: [ 375.003236] Memory Limit: none
2022-05-17 08:00:15.435488: [ 375.006258] ---[ end Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt ]---
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
Kenneth Graunke [Fri, 13 May 2022 20:04:21 +0000 (13:04 -0700)]
intel/decoder: Fix binding table pointer decoding with large offsets
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX. Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.
Thanks to Felix DeGrood for catching this!
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538>
Pierre-Eric Pelloux-Prayer [Fri, 13 May 2022 12:31:53 +0000 (14:31 +0200)]
glx: set max values for pbuffer width / height
Without this change the values are always 0. This breaks
Maya which uses this value to create a pbuffer (and then
fails).
This commit is based on
b91e1e38e87 which does the same
for EGL.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16496>
David Heidelberg [Mon, 9 May 2022 17:58:58 +0000 (19:58 +0200)]
ci/iris: skqp: remove flaking atlastext for TGL
Example:
- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
22380389#L4349
- https://mesa.pages.freedesktop.org/-/mesa/-/jobs/
22380389/artifacts///results/gles/report.html
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6460
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
David Heidelberg [Mon, 9 May 2022 17:57:35 +0000 (19:57 +0200)]
ci/iris: skqp: add default GLES rendertests for TGL
Import the intact whole rendertest file from skqp (branch
android-cts-12.1_r1) to be able remove the offending test line in the
following commit.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
Dave Airlie [Mon, 16 May 2022 04:54:05 +0000 (14:54 +1000)]
aco/radv: drop radv_nir_compiler_options from aco.
Add a new aco input and options structs, then convert from radv
pieces on submit.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
Dave Airlie [Mon, 16 May 2022 04:35:07 +0000 (14:35 +1000)]
ac/radv: drop info pointer from the ac and radv shader structs
This was being used for one bool, just pass the bool.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
Mike Blumenkrantz [Tue, 17 May 2022 04:02:08 +0000 (00:02 -0400)]
zink: add tu baseline for a630
oof
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16549>
Mike Blumenkrantz [Mon, 16 May 2022 13:02:07 +0000 (09:02 -0400)]
zink: move get_timestamp to screen
this doesn't need to use a particular context
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
Mike Blumenkrantz [Mon, 16 May 2022 12:58:37 +0000 (08:58 -0400)]
zink: use copy context to eliminate dependency on EXT_calibrated_timestamps
this is unsupported by a surprising number of drivers
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
Mike Blumenkrantz [Mon, 16 May 2022 17:02:11 +0000 (13:02 -0400)]
zink: fix init with MESA_SHADER_CACHE_DISABLE enabled
Fixes:
ba2f5cb20aa ("zink: check for error when initializing util_queue")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16533>
Mike Blumenkrantz [Wed, 11 May 2022 20:04:14 +0000 (16:04 -0400)]
zink: manually validate shaders in debug builds
VVL is great, but there's actually cases where it doesn't catch critical
spirv errors, so add in our own validation pass to make sure things are
okay
this is especially useful for running on nvidia, as their compiler will
either crash on or silently drop illegal instructions
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
Mike Blumenkrantz [Wed, 11 May 2022 20:01:48 +0000 (16:01 -0400)]
spirv: fix barrier scope assert
glslang generates barriers with QueueFamily, so this is totally legal
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
Mike Blumenkrantz [Wed, 11 May 2022 17:06:11 +0000 (13:06 -0400)]
lavapipe: fix pipeline handling for dynamic render zs state with pipeline library
this is slightly more nuanced: if this is ONLY a fragment state,
pDepthStencilState must exist, but if it's BOTH fragment and output,
then pDepthStencilState must only exist if zs attachment is used
Fixes:
d4d5a7abba7 ("lavapipe: implement EXT_graphics_pipeline_library")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
Mike Blumenkrantz [Thu, 12 May 2022 15:43:51 +0000 (11:43 -0400)]
lavapipe: ignore depth/stencil states if attachment is not present
depth and stencil states should only be set if the corresponding attachment
is present, otherwise they should be ignored. this is different from
ignoring the entire VkPipelineDepthStencilStateCreateInfo struct, as
it's possible that only depth or only stencil may be present
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
Timothy Arceri [Mon, 16 May 2022 06:41:48 +0000 (16:41 +1000)]
vc4: disable GLSL IR loop unrolling
NIR loop unrolling is already enabled so just let it do its job.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 02:04:05 +0000 (12:04 +1000)]
r600: switch to NIR loop unrolling
Note the NIR unrolling code was already enabled but we bump the
iteration unroll count to match the GLSL IR limit as per the
comment about loop bugs.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 01:56:11 +0000 (11:56 +1000)]
r300: disable GLSL IR loop unrolling
NIR loop unrolling is already enabled so just let it do its job.
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 01:40:57 +0000 (11:40 +1000)]
i915g: switch to NIR loop unrolling
Shader-db stats:
total instructions in shared programs: 406749 -> 406890 (0.03%)
instructions in affected programs: 216 -> 357 (65.28%)
total tex_indirect in shared programs: 12666 -> 12671 (0.04%)
tex_indirect in affected programs: 29 -> 34 (17.24%)
total temps in shared programs: 23447 -> 23451 (0.02%)
temps in affected programs: 296 -> 300 (1.35%)
total const in shared programs: 59400 -> 59455 (0.09%)
const in affected programs: 50 -> 105 (110.00%)
LOST: 0
GAINED: 17
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 01:32:24 +0000 (11:32 +1000)]
etnaviv: switch to NIR loop unrolling
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 01:30:30 +0000 (11:30 +1000)]
d3d12: switch to NIR loop unrolling
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 01:26:25 +0000 (11:26 +1000)]
asahi: switch to NIR loop unrolling
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Fri, 6 May 2022 01:23:06 +0000 (11:23 +1000)]
softpipe: switch to NIR loop unrolling
shader-db results:
total instructions in shared programs: 2788746 -> 2788886 (<.01%)
instructions in affected programs: 2126 -> 2266 (6.59%)
total loops in shared programs: 1357 -> 892 (-34.27%)
loops in affected programs: 468 -> 3 (-99.36%)
total temps in shared programs: 288754 -> 288725 (-0.01%)
temps in affected programs: 1623 -> 1594 (-1.79%)
total const in shared programs: 1954525 -> 1954621 (<.01%)
const in affected programs: 207 -> 303 (46.38%)
total imm in shared programs: 101023 -> 100891 (-0.13%)
imm in affected programs: 198 -> 66 (-66.67%)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Mon, 9 May 2022 04:40:52 +0000 (14:40 +1000)]
i915g: use a valid setting for force_indirect_unrolling
Otherwise we can hit asserts for example nir_deref_mode_must_be()
asserts on !(modes & ~nir_var_all)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Wed, 11 May 2022 12:53:46 +0000 (22:53 +1000)]
glsl: move validation of sampler indirects to the nir linker
This will allow us to disable the GLSL IR loop unroller in a
following patch and rely on the NIR loop unroller instead.
This allows the piglit test spec@!opengl 2.0@max-samplers border
to pass on the v3d rpi4 driver.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Wed, 11 May 2022 12:44:44 +0000 (22:44 +1000)]
gallium/drivers: set force_indirect_unrolling_sampler for all required drivers
This is set to true for all drivers that have a GLSL level
of support lower than 4.00. This matches the rule for setting the
GLSL IR option EmitNoIndirectSampler.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Timothy Arceri [Wed, 11 May 2022 10:12:56 +0000 (20:12 +1000)]
nir: add support for forced sampler indirect loop unrolling
Some drivers don't support these indirects and therefore require
loop unrolling if a shader uses a loop induction variable to
access a sampler array.
Here we add a new nir shader compiler option that drivers can set,
this will be the equivalent of the EmitNoIndirectSampler setting
used in the GLSL IR unrolling pass.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
Chia-I Wu [Mon, 16 May 2022 20:19:29 +0000 (13:19 -0700)]
ir3: fix mem_ctx for ir3_disasm_info::nir
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6494
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16535>
Jason Ekstrand [Thu, 12 May 2022 14:53:08 +0000 (09:53 -0500)]
panvk: Lower blending after lower_var_copies
nir_lower_blend needs store_deref as does
io_arrays_to_elements_no_indirects.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16483>
Jason Ekstrand [Thu, 12 May 2022 14:05:34 +0000 (09:05 -0500)]
panvk: So more nir_lower_tex before descriptor lowering
Some texture lowering generates more txs which means it needs to happen
before we lower descriptors because descriptor lowering is where txs is
actually handled in panvk.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16483>
Jason Ekstrand [Tue, 15 Mar 2022 21:22:27 +0000 (16:22 -0500)]
bifrost: Run nir_lower_global_vars_to_local before nir_lower_vars_to_scratch
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16483>
Chia-I Wu [Fri, 13 May 2022 17:41:30 +0000 (10:41 -0700)]
turnip: emit VPC_SO_DISABLE in xfb begin/end
SO was always enabled before this change. That meant, after a call to
tu_CmdBindTransformFeedbackBuffersEXT to emit VPC_SO_BUFFER_SIZE, any
draw call (from the same render pass, in a different render pass, or in
a different cmdbuf) could potentially cause writes to the SO buffers
regardless of whether the draw is inside xfb begin/end or not.
I choose to emit VPC_SO_DISABLE instead of using stateobjs like
freedreno does only because it is simpler. It is not clear to me which
is more efficient to HW.
This also fixes double SO writes for gmem rendering. While
tu6_tile_render_begin was careful to disable SO for the draw pass,
tu6_emit_tile_select re-enabled it.
dEQP-VK.transform_feedback.* still passes. It fixes
dEQP-GLES3.functional.transform_feedback.* on angle.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16502>
Chia-I Wu [Fri, 13 May 2022 00:32:42 +0000 (17:32 -0700)]
turnip: fix sampledImageIntegerSampleCounts
It seems fine to advertise msaa in sampledImageIntegerSampleCounts.
dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.*
goes from NotSupported to Pass for more test cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16487>
Yonggang Luo [Tue, 10 May 2022 21:19:33 +0000 (05:19 +0800)]
radv: Add macros for win32 that accessed
Fixes:
3e85a0c90b5 ("ac/surface: define gfx11 modifiers")
../../src/amd/common/ac_surface.c: In function 'ac_get_supported_modifiers':
../../src/amd/common/ac_surface.c:421:47: error: 'AMD_FMT_MOD_TILE_GFX11_256K_R_X' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_GFX9_64K_R_X'?
421 | unsigned swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| AMD_FMT_MOD_TILE_GFX9_64K_R_X
../../src/amd/common/ac_surface.c:421:47: note: each undeclared identifier is reported only once for each function it appears in
In file included from ../../src/amd/common/ac_surface.c:31:
../../src/amd/common/ac_surface.c:424:61: error: 'AMD_FMT_MOD_TILE_VER_GFX11' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_VER_GFX10'?
424 | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/amd/common/ac_drm_fourcc.h:75:21: note: in definition of macro 'AMD_FMT_MOD_SET'
75 | ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
| ^~~~~
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Yonggang Luo [Tue, 10 May 2022 21:04:33 +0000 (05:04 +0800)]
radv: Add losing member hw_ip_version_major and hw_ip_version_minor for win32
Fixes:
b261ac1ab5d ("ac/gpu_info: print all IP versions reported by the kernel")
```
../../src/amd/common/ac_gpu_info.c
../../src/amd/common/ac_gpu_info.c: In function 'ac_query_gpu_info':
../../src/amd/common/ac_gpu_info.c:545:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_major'
545 | info->ip[ip_type].ver_major = ip_info.hw_ip_version_major;
| ^
../../src/amd/common/ac_gpu_info.c:546:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_minor'
546 | info->ip[ip_type].ver_minor = ip_info.hw_ip_version_minor;
| ^
```
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Yonggang Luo [Fri, 6 May 2022 13:46:17 +0000 (21:46 +0800)]
radv: Fixes compiling error with msvc
Fixes:
11c28d9798c ("ac: add ac_nir_optimize_outputs, a NIR version of ac_optimize_vs_outputs")
```
FAILED: src/amd/common/libamd_common.a.p/ac_nir_opt_outputs.c.obj
"cl" "-Isrc\amd\common\libamd_common.a.p" "-Isrc\amd\common" "-I..\mesa\src\amd\common" "-Iinclude" "-I..\mesa\include" "-Isrc" "-I..\mesa\src" "-Isrc\mapi" "-I..\mesa\src\mapi" "-Isrc\mesa" "-I..\mesa\src\mesa" "-I..\mesa\src\gallium\include" "-Isrc\gallium\auxiliary" "-I..\mesa\src\gallium\auxiliary" "-Isrc\compiler" "-I..\mesa\src\compiler" "-Isrc\amd" "-I..\mesa\src\amd" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\contrib\elftoolchain\common" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\contrib\elftoolchain\libelf" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\sys" "-Isrc\util" "-I..\mesa\src\util" "-Isubprojects\zlib-1.2.11" "-I..\mesa\subprojects\zlib-1.2.11" "-Isrc\compiler\nir" "-I..\mesa\src\compiler\nir" "/MT" "/nologo" "/showIncludes" "/utf-8" "/W3" "/WX" "/std:c11" "/O2" "/Gw" "-D__STDC_CONSTANT_MACROS" "-D__STDC_FORMAT_MACROS" "-D__STDC_LIMIT_MACROS" "-DPACKAGE_VERSION=\"22.2.0-devel\"" "-DPACKAGE_BUGREPORT=\"https://gitlab.freedesktop.org/mesa/mesa/-/issues\"" "-DHAVE_SWRAST" "-DHAVE_D3D12" "-DHAVE_ZINK" "-DVIDEO_CODEC_VC1DEC=0" "-DVIDEO_CODEC_H264DEC=0" "-DVIDEO_CODEC_H264ENC=0" "-DVIDEO_CODEC_H265DEC=0" "-DVIDEO_CODEC_H265ENC=0" "-DHAVE_WINDOWS_PLATFORM" "-DHAVE_SURFACELESS_PLATFORM" "-DUSE_ELF_TLS" "-DUSE_TLS_BEHIND_FUNCTIONS" "-DENABLE_ST_OMX_BELLAGIO=0" "-DENABLE_ST_OMX_TIZONIA=0" "-DEGL_NO_X11" "-D_WINDOWS" "-D_WIN32_WINNT=0x0A00" "-DWINVER=0x0A00" "-DPIPE_SUBSYSTEM_WINDOWS_USER" "-D_USE_MATH_DEFINES" "-DVC_EXTRALEAN" "-D_CRT_SECURE_NO_WARNINGS" "-D_CRT_SECURE_NO_DEPRECATE" "-D_SCL_SECURE_NO_WARNINGS" "-D_SCL_SECURE_NO_DEPRECATE" "-D_ALLOW_KEYWORD_MACROS" "-D_HAS_EXCEPTIONS=0" "-DNOMINMAX" "-DMISSING_64BIT_ATOMICS" "-DHAVE_STRTOF" "-DHAVE_TIMESPEC_GET" "-DHAVE_QSORT_S" "-DHAVE_STRUCT_TIMESPEC" "-DHAVE_ZLIB" "-DHAVE_COMPRESSION" "-DLLVM_AVAILABLE" "-DMESA_LLVM_VERSION_STRING=\"12.0.1\"" "-DLLVM_IS_SHARED=0" "-DDRAW_LLVM_AVAILABLE" "-DMESA_EXECMEM" "-DVK_USE_PLATFORM_WIN32_KHR" "/wd4018" "/wd4056" "/wd4244" "/wd4267" "/wd4305" "/wd4351" "/wd4756" "/wd4800" "/wd4996" "/wd4291" "/wd4146" "/wd4200" "/wd4624" "/wd4309" "/wd4838" "/wd5105" "/we4020" "/we4024" "/Zc:__cplusplus" "-DADDR_FASTCALL=" "/Fdsrc\amd\common\libamd_common.a.p\ac_nir_opt_outputs.c.pdb" /Fosrc/amd/common/libamd_common.a.p/ac_nir_opt_outputs.c.obj "/c" ../mesa/src/amd/common/ac_nir_opt_outputs.c
../mesa/src/amd/common/ac_nir_opt_outputs.c(256): error C2059: syntax error: '}'
[23/987] Compiling C object src/compiler/nir/libnir.a.p/nir_opt_preamble.c.obj
```
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Yonggang Luo [Fri, 6 May 2022 13:37:54 +0000 (21:37 +0800)]
radv: fixes msvc compiling error
Fixes:
5d9ef0efb57 ("radv: Add the fuchsia radix sort")
../mesa/src/amd/vulkan/radix_sort/radv_radix_sort.c(148): error C2220: the following warning is treated as an error
../mesa/src/amd/vulkan/radix_sort/radv_radix_sort.c(148): warning C4098: 'vkDestroyPipeline': 'void' function returning a value
[82/1129] Compiling C++ object src/amd/compiler/libaco.a.p/aco_instruction_selection.cpp.obj
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Yonggang Luo [Tue, 10 May 2022 23:33:41 +0000 (07:33 +0800)]
llvmpipe: Do not use _Atomic keyword that doesn't support by MSVC
Fixes:
3269d34b29a ("llvmpipe/fence: make the fence id counter atomic")
Fixes:
```
../mesa/src/gallium/drivers/llvmpipe/lp_fence.c
../mesa/src/gallium/drivers/llvmpipe/lp_fence.c(47): error C2143: syntax error: missing ';' before 'type'
```
fence_id initialized to 0
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Erik Faye-Lund [Mon, 16 May 2022 07:50:26 +0000 (09:50 +0200)]
vulkan/wsi: unbreak win32-support
There's no unistd.h on Windows, let's not include it unconditionally.
But we also don't want to deal with DRM modifiers or DMABUFs on Windows,
so let's also ifdef out the rest of that stuff.
Fixes:
a8b009aed6b ("vulkan/wsi: fix missing unistd include")
Fixes:
c72ff19a9ef ("vulkan/wsi: Close file descriptors in wsi_destroy_image")
Reviewed-By: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Ian Romanick [Tue, 10 May 2022 18:56:35 +0000 (11:56 -0700)]
glsl: Delete lower_extracts code
The single caller of this function (in st_glsl_to_ir.cpp) always passes
false, so this is dead code.
v2: Delete convert_vec_index_to_cond_assign method because all the
callers are deleted too.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>
Ian Romanick [Fri, 14 Jan 2022 21:44:31 +0000 (13:44 -0800)]
nir: Use nir_vector_extract to generate code for ir_binop_vector_extract
Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total cycles in shared programs:
861153442 ->
861153533 (<.01%)
cycles in affected programs: 14748 -> 14839 (0.62%)
helped: 5
HURT: 10
helped stats (abs) min: 1 max: 2 x̄: 1.80 x̃: 2
helped stats (rel) min: 0.09% max: 0.18% x̄: 0.16% x̃: 0.17%
HURT stats (abs) min: 2 max: 18 x̄: 10.00 x̃: 10
HURT stats (rel) min: 0.17% max: 1.54% x̄: 1.06% x̃: 1.24%
95% mean confidence interval for cycles value: 1.15 10.99
95% mean confidence interval for cycles %-change: 0.25% 1.07%
Cycles are HURT.
Skylake and Broadwell had similar results. (Skylake shown)
total cycles in shared programs:
844405063 ->
844405073 (<.01%)
cycles in affected programs: 1710 -> 1720 (0.58%)
helped: 0
HURT: 4
HURT stats (abs) min: 2 max: 4 x̄: 2.50 x̃: 2
HURT stats (rel) min: 0.35% max: 1.16% x̄: 0.88% x̃: 1.00%
95% mean confidence interval for cycles value: 0.91 4.09
95% mean confidence interval for cycles %-change: 0.30% 1.45%
Cycles are HURT.
Haswell and all earlier Intel GPUs had similar results. (Haswell shown)
total instructions in shared programs:
16710016 ->
16709769 (<.01%)
instructions in affected programs: 5842 -> 5595 (-4.23%)
helped: 64
HURT: 0
helped stats (abs) min: 3 max: 4 x̄: 3.86 x̃: 4
helped stats (rel) min: 3.36% max: 7.69% x̄: 4.52% x̃: 4.17%
95% mean confidence interval for instructions value: -3.95 -3.77
95% mean confidence interval for instructions %-change: -4.83% -4.22%
Instructions are helped.
total cycles in shared programs:
881088472 ->
881086722 (<.01%)
cycles in affected programs: 68696 -> 66946 (-2.55%)
helped: 58
HURT: 6
helped stats (abs) min: 10 max: 202 x̄: 36.41 x̃: 18
helped stats (rel) min: 0.81% max: 16.42% x̄: 4.15% x̃: 1.51%
HURT stats (abs) min: 2 max: 88 x̄: 60.33 x̃: 68
HURT stats (rel) min: 0.17% max: 7.06% x̄: 4.94% x̃: 5.60%
95% mean confidence interval for cycles value: -42.14 -12.54
95% mean confidence interval for cycles %-change: -4.66% -1.94%
Cycles are helped.
No fossil-db changes on any Intel platform.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>
Ian Romanick [Fri, 14 Jan 2022 21:39:06 +0000 (13:39 -0800)]
glsl: Add flag to disable part of do_vec_index_to_cond_assign
As of
ca63a5ed3e9 ("glsl: fix interpolateAtXxx(some_vec[idx], ...) with
dynamic idx"), this lowering pass does two things. It converts
ir_binop_vector_extract to an if-ladder to select the dynamically
indexed component, and it extracts a ir_binop_vector_extract from the
source of an interpolateAt function and applies to the result instead.
This change adds a flag to disable the former behavior. The latter is
still useful, but NIR has better (and soon even better) ways of doing
the former.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>