Yifan Zha [Wed, 17 Aug 2022 09:25:15 +0000 (17:25 +0800)]
drm/amdgpu: Use RLCG to program GRBM_GFX_CNTL during full access time
[Why]
KIQ register init requires GRBM_GFX_CNTL to select KIQ.
[How]
As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it.
Use RLCG indirect accessing register method to select grbm instead of mmio directly access.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Wed, 17 Aug 2022 10:44:14 +0000 (18:44 +0800)]
drm/amdgpu: Skip program SDMA0_SEM_WAIT_FAIL_TIMER_CNTL under SRIOV VF
[Why]
As SDMA0_SEM_WAIT_FAIL_TIMER_CNTL is a PF-only register,
L1 would block this register for VF access.
[How]
VF do not program it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Wed, 27 Jul 2022 06:43:32 +0000 (14:43 +0800)]
drm/amdgpu: Skip the VRAM base offset on SRIOV
[Why]
As VF cannot read MMMC_VM_FB_OFFSET with L1 Policy(read 0xffffffff).
It leads to driver get the incorrect vram base offset.
[How]
Since SR-IOV is dGPU only, skip reading this register and set the
fb_offest to 0.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Mon, 1 Aug 2022 03:11:20 +0000 (11:11 +0800)]
drm/amdgpu: skip "Issue additional private vm invalidation to MMHUB" on SRIOV
[Why]
vm_l2_bank_select_reserved_cid2 is a PF_only register
that cannot be programmed by VF. This feature is only
support HDP using GPUVM page tables to access FB memory
which should be disabled on SRIOV.
[How]
Disable the feature on VF.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Wed, 27 Jul 2022 05:43:50 +0000 (13:43 +0800)]
drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV on MMHUB v3_0_0
[Why]
VF should not program these registers, the value were defined in the host.
[How]
Skip writing them in SRIOV environment and program them on host side.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Wed, 27 Jul 2022 02:50:55 +0000 (10:50 +0800)]
drm/amdgpu: Use PSP program IH_RB_CNTL registers under SRIOV
[Why]
With L1 Policy applied, IH_RB_CNTL/RING cannot be accessed by VF.
[How]
Use PSP program IH_RB_CNTL in VF.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Fri, 29 Jul 2022 05:44:43 +0000 (13:44 +0800)]
drm/amdgpu: Support PSP 13.0.10 on SR-IOV
Add support for PSP 13.0.10 for SR-IOV VF
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Thu, 21 Jul 2022 08:25:17 +0000 (16:25 +0800)]
drm/amdgpu: sriov remove vcn_4_0 and jpeg_4_0
SRIOV needs to initialize mmsch instead of multimedia engines
directly. So currently remove them for SR-IOV until the code and
firmwares are ready.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Thu, 21 Jul 2022 06:42:30 +0000 (14:42 +0800)]
drm/amdgpu: refine virtualization psp fw skip check
SR-IOV may need to load different firmwares for different ASIC inside
VF.
So create a new function in amdgpu_virt to check whether FW load needs
to be skipped.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Thu, 21 Jul 2022 04:18:18 +0000 (12:18 +0800)]
drm/amdgpu: enable WPTR_POLL_ENABLE for sriov on sdma_v6_0
[Why]
Under SR-IOV, if VF is switched out then its doorbell will be disabled,
SDMA rely on WPTR_POLL to get doorbells which was sent during VF
switched-out time.
[How]
For SR-IOV, set SDMA WPTR_POLL_ENABLE to 1.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Thu, 21 Jul 2022 04:11:33 +0000 (12:11 +0800)]
drm/amdgpu: add a compute pipe reset for RS64
[Why]
Under SR-IOV, we are not sure whether pipe status is
good or not when doing initialization. The compute engine
maybe fail to bringup if pipe status is bad.
[How]
Do an RS64 pipe reset for MEC before we do initialization.
Also apply to bare-metal.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Thu, 21 Jul 2022 03:57:44 +0000 (11:57 +0800)]
drm/amdgpu: add sriov nbio callback structure
[Why]
under SR-IOV, the nbio doorbell range will be defined by PF. So VF
nbio doorbell range registers will be blocked. It will cause violation
if VF access those registers directly.
[How]
create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to
skip the setting for the doorbell range registers.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Horace Chen [Thu, 21 Jul 2022 08:56:21 +0000 (16:56 +0800)]
drm/amdgpu: add CHIP_IP_DISCOVERY support for virtualization
For further chips we will use CHIP_IP_DISCOVERY, so add this
support for virtualization
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Tue, 30 Aug 2022 15:18:47 +0000 (23:18 +0800)]
drm/amdgpu/mes: zero the sdma_hqd_mask of 2nd SDMA engine for SDMA 6.0.1
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be
zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd
engine exists and map/unmap SDMA queues to the non-existent engine.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 30 Aug 2022 21:57:52 +0000 (17:57 -0400)]
drm/amd/display: fix documentation for amdgpu_dm_update_freesync_caps()
Document missing parameter.
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Fixes:
8889a13f99e5 ("drm/amd/display: Add some extra kernel doc to amdgpu_dm")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 11 Aug 2022 15:48:19 +0000 (11:48 -0400)]
Documentation/gpu: Add Multiplane Overlay doc
Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some discussion in the public upstream [1][2].
[1]. https://lore.kernel.org/amd-gfx/3qY-QeukF_Q_MJeIXAuBjO4szbS4jRtqkTifXnbnN3bp88SxVodFQRpah3mIIVJq24DUkF6g0rOGdCmSqTvVxx9LCGEItmzLw8uWU44jtXE=@emersion.fr/
[2]. https://lore.kernel.org/amd-gfx/
864e45d0-c14b-3b12-0f5b-
9d26a9cb41bd@amd.com/
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 11 Aug 2022 15:48:18 +0000 (11:48 -0400)]
Documentation/gpu: Add an explanation about the DCN pipeline
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.
Changes since V1:
- Rewrite the first paragraph that describes AMD hardware pipeline.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 11 Aug 2022 15:48:17 +0000 (11:48 -0400)]
Documentation/gpu: Add info table for ASICs
Amdgpu driver is used in an extensive range of devices, and each ASIC
has some specific configuration. As a result of this variety, sometimes
it is hard to identify the correct block that might cause the issue.
This commit expands the amdgpu kernel-doc to alleviate this issue by
introducing one ASIC table that describes dGPU and another one that
shares the APU info.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Cc: Kent Russell <Kent.Russell@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 30 Aug 2022 08:33:01 +0000 (16:33 +0800)]
drm/amd/amdgpu: skip ucode loading if ucode_size == 0
Restrict the ucode loading check to avoid frontdoor loading error.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ye xingchen [Tue, 30 Aug 2022 08:32:43 +0000 (08:32 +0000)]
drm/amdgpu: Remove the unneeded result variable 'r'
Return the value sdma_v4_0_start() directly instead of storing it in
another redundant variable.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:04:22 +0000 (17:04 -0400)]
drm/amdgpu: add new ip block for MES 11.0.3
Add ip block support for mes v11_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:02:47 +0000 (17:02 -0400)]
drm/amdgpu: add new ip block for GFX 11.0
Add ip block support for gfx v11_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:05:24 +0000 (17:05 -0400)]
drm/amdgpu: Set GC family for GC 11.0.3
Set AMDGPU_FAMILY_GC_11_0_0.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 2 Jul 2022 02:20:03 +0000 (10:20 +0800)]
drm/amdgpu: enable imu_rlc_ram programming for v11_0_3
All gc v11_0_3 registers in gcvml2 range have different
register offset from the ones in gc v11_0_0. v11_0_3
imu_rlc_ram programming has to be separated from v11_0_0
implementation
v2: fix checkpatch errors (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Belanger [Tue, 26 Jul 2022 13:54:51 +0000 (09:54 -0400)]
drm/amdkfd: Added GFX 11.0.3 Support
Added missing cases for GFX 11.0.3 code in a few switch statements.
Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 27 Jun 2022 16:33:14 +0000 (00:33 +0800)]
drm/amdgpu: init gfx config for gfx v11_0_3
initialize some gfx config for gfx v11_0_3
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 20:57:57 +0000 (16:57 -0400)]
drm/amdgpu: declare firmware for new MES 11.0.3
To support new mes ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 20:56:52 +0000 (16:56 -0400)]
drm/amdgpu: declare firmware for new GC 11.0.3
To support new gfx ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:01:52 +0000 (17:01 -0400)]
drm/amdgpu: add new ip block for GMC 11.0
Add ip block support for gmc v11_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 27 Jun 2022 16:35:07 +0000 (00:35 +0800)]
drm/amdgpu: initialize gmc sw config for v11_0_3
initialize gmc sw config for v11_0_3
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Fri, 1 Jul 2022 09:19:27 +0000 (17:19 +0800)]
drm/amdgpu: add gfxhub_v3_0_3 support
add gfxhub_v3_0_3 support
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 27 Jun 2022 03:05:43 +0000 (11:05 +0800)]
drm/amdgpu: add gc v11_0_3 ip headers
Add gc v11_0_3 register offset and shift masks
header files
v2: update registers (Alex)
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 30 Aug 2022 07:47:47 +0000 (15:47 +0800)]
drm/amdgpu: only init tap_delay ucode when it's included in ucode binary
Not all the gfx10 variants need to integrate
global tap_delay and per se tap_delay firmwares
Only init tap_delay ucode when it does include in
rlc ucode binary so driver doesn't send a null buffer
to psp for firmware loading
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Li [Mon, 29 Aug 2022 08:36:27 +0000 (16:36 +0800)]
drm/amd/display: clean up some inconsistent indentings
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Li [Mon, 29 Aug 2022 08:36:26 +0000 (16:36 +0800)]
drm/amd/display: clean up some inconsistent indentings
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Li [Mon, 29 Aug 2022 08:36:25 +0000 (16:36 +0800)]
drm/amd/display: clean up some inconsistent indentings
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Li [Mon, 29 Aug 2022 08:36:24 +0000 (16:36 +0800)]
drm/amd/display: clean up one inconsistent indenting
1. The indentation of statements in the same curly bracket should be
consistent.
2. Variable declarations in the same function should be aligned.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1889
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:06:21 +0000 (17:06 -0400)]
drm/amdgpu: add new ip block for LSDMA 6.0
Add ip block support for lsdma v6_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:03:29 +0000 (17:03 -0400)]
drm/amdgpu: add new ip block for sdma 6.0
Add ip block support for sdma v6_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 20:58:27 +0000 (16:58 -0400)]
drm/amdgpu: declare firmware for new SDMA 6.0.3
To support new sdma ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 11 May 2022 07:24:11 +0000 (15:24 +0800)]
drm/amdgpu: enable smu block for smu 13.0.10
Force to enable smu block for SMU v13.0.10
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Mon, 25 Jul 2022 02:02:05 +0000 (10:02 +0800)]
drm/amdgpu: added supported smu 13.0.10 sw pptable
added sw pptable id 6666 for smu 13.0.10
v2: fix checkpatch error (Alex)
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Fri, 18 Mar 2022 12:05:32 +0000 (20:05 +0800)]
drm/amd/pm: add smu_v13_0_10 driver if version
add smu_v13_0_10 driver if version
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Thu, 25 Aug 2022 21:13:05 +0000 (17:13 -0400)]
drm/amd/pm: add smu_v13_0_10 support
add smu_v13_0_10 support.
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Thu, 25 Aug 2022 21:10:00 +0000 (17:10 -0400)]
drm/amdgpu: add new ip block for PSP 13.0
Add ip block support for psp v13_0_10.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 13 Jul 2022 14:10:16 +0000 (22:10 +0800)]
drm/amdgpu: added firmware module for psp 13.0.10
added missing firmware module
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Thu, 25 Aug 2022 21:09:08 +0000 (17:09 -0400)]
drm/amdgpu: support psp v13_0_10 ip block
Add psp v13_0_10 ip block, initialize firmware and
psp functions
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:00:13 +0000 (17:00 -0400)]
drm/amdgpu: add new ip block for SOC21
Add ip block support for soc21_common.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sonny Jiang [Thu, 4 Aug 2022 20:56:58 +0000 (16:56 -0400)]
drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCN
This enable VCN PG, CG, DPG and JPEG PG, CG
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 27 Jun 2022 16:41:52 +0000 (00:41 +0800)]
drm/amdgpu: initialize common sw config for v11_0_3
init cp/pg_flags and extenal_rev_id
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 19 Jul 2022 06:39:57 +0000 (14:39 +0800)]
drm/amdgpu: drop gc 11_0_0 golden settings
driver doesn't need to program any gc 11_0_0 golden
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jinpeng Cui [Mon, 29 Aug 2022 12:29:14 +0000 (12:29 +0000)]
drm/amdkfd: remove redundant variables err and ret
Return value from kfd_wait_on_events() and io_remap_pfn_range() directly
instead of taking this in another redundant variable.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Jinpeng Cui <cui.jinpeng2@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jinpeng Cui [Mon, 29 Aug 2022 12:13:20 +0000 (12:13 +0000)]
drm/amd/display: remove redundant vertical_line_start variable
Return value from expression directly instead of
taking this in another redundant variable.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Jinpeng Cui <cui.jinpeng2@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Tsai [Thu, 18 Aug 2022 08:01:24 +0000 (16:01 +0800)]
drm/amd/display: Correct cursor position on horizontal mirror
[Why]
Incorrect cursor position will induce system hang on pipe split.
[How]
1.Handle horizontal mirror on rotation,
2.Correct cursor set on piep split.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vladimir Stempen [Fri, 19 Aug 2022 22:32:01 +0000 (18:32 -0400)]
drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass
[Why]
On secondary display hotplug we switch primary
stream from ODM2to1 to ODMBypass mode. Current
logic will trigger disabling front end for this
stream.
[How]
We need to check if prev_odm_pipe is equal to NULL
in order to disable dangling planes in this scenario.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ethan Wellenreiter [Fri, 19 Aug 2022 22:30:44 +0000 (18:30 -0400)]
drm/amd/display: Fix check for stream and plane
[WHY]
Function wasn't returning false when it had a no stream
[HOW]
Made it return false when it had no stream.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ethan Wellenreiter [Mon, 22 Aug 2022 18:33:23 +0000 (14:33 -0400)]
drm/amd/display: Re-initialize viewport after pipe merge
[Why]
Pipes get merged in preparation for SubVP but if they don't get used, and
are in ODM or some other multi pipe config, it would calculate the
voltage level with a viewport of just one pipe from when they were split
resulting in too low of a voltage level.
[How]
Made it so that the viewport and other timing settings get rebuilt and re-
initialized after the pipe merge, before calculating the voltage level so it
would calculate it correctly.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Fri, 19 Aug 2022 19:11:19 +0000 (15:11 -0400)]
drm/amd/display: Use correct plane for CAB cursor size allocation
[Why&How]
plane and stream variables used for cursor size allocation calculation
were stale from previous iteration. Redo the iteration to find the
correct cursor plane for the calculation.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Thu, 25 Aug 2022 20:42:08 +0000 (15:42 -0500)]
drm/amdgpu: ensure no PCIe peer access for CPU XGMI iolinks
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 22 Aug 2022 04:47:03 +0000 (00:47 -0400)]
drm/amd/display: 3.2.201
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Aug 2022 09:37:26 +0000 (17:37 +0800)]
drm/amd/pm: bump SMU 13.0.0 driver_if header version
To suppress the warning about version mismatch with
the latest 78.54.0 PMFW.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Aug 2022 08:07:18 +0000 (16:07 +0800)]
drm/amd/pm: use vbios carried pptable for all SMU13.0.7 SKUs
For those SMU13.0.7 unsecure SKUs, the vbios carried pptable is ready to go.
Use that one instead of hardcoded softpptable.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Aug 2022 07:45:36 +0000 (15:45 +0800)]
drm/amd/pm: use vbios carried pptable for those supported SKUs
For some SMU13.0.0 SKUs, the vbios carried pptable is ready to go.
Use that one instead of hardcoded softpptable.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Hanghong) Ma [Tue, 16 Aug 2022 20:51:33 +0000 (16:51 -0400)]
drm/amd/display: Add visual confirm color support for SubVP
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this display;
3. Set visual confirm color to blue: SubVP is enable on
other display and DRR is off on this display;
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 20 Aug 2022 13:04:06 +0000 (09:04 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.132.0
- Fix comment to indicate correct visual confirm option
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Tue, 16 Aug 2022 07:47:02 +0000 (15:47 +0800)]
drm/amd/display: Add comments.
Reviewed-by: Dennis Chan <dennis.chan@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Fri, 19 Aug 2022 17:11:30 +0000 (13:11 -0400)]
drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32"
[Why & How]
This reverts commit
e6cf22ef5fae493a99e162c3f2e7233448d2b970 since it
causes a SubVP related regression: "Switching between windowed video and
fullscreen can intermittently cause black screen"
Fixes:
e6cf22ef5fae49 ("drm/amd/display: program k1/k2 divider for virtual signal for DCN32")
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Iswara Nagulendran [Fri, 19 Aug 2022 18:10:08 +0000 (14:10 -0400)]
drm/amd/display: Fix primary EDP link detection
[HOW&WHY]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.
* SWDEV-342936 - dc: DSC bringup for SAG 1.5
[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.
[HOW]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic to ensure the CRC checker provides valid
values for non-black frames
allowing the system to come out of forced PSR on
d2i.
Added additional logic to both generate a black
frame through setVisibility calls and keep track
of the CRCs values for this black frame when
coming out of forced PSR.
Updating logic for DalRegKey_DisableDSC to disable
DSC on EDP and all ports for systems.
[CLEANED]
dc: Moved DSC programming to before stream enablement
[HOW&WHY]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic.
Co-authored-by: sregolui <sregolui@amd.com>
Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com>
Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: sregolui <sregolui@amd.com>
Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Fri, 19 Aug 2022 00:24:26 +0000 (20:24 -0400)]
drm/amd/display: fix wrong register access
[why]
fw version check was for release branch.
for staging, it has a chance to enter wrong code path.
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 18 Aug 2022 21:55:01 +0000 (17:55 -0400)]
drm/amd/display: use actual cursor size instead of max for CAB allocation
[Why&How]
When calculating allocation for cursor size, get the real cursor through
the HUBP instead of using the maximum cursor size for more optimal
allocation
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 18 Aug 2022 16:34:06 +0000 (12:34 -0400)]
drm/amd/display: disable display fresh from MALL on an edge case for DCN321
[Why&How]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.
Prevent entering SS if we are on the edge case and cursor caching is not
possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the
cursor size calculation out of if condition since cursor address may not
be set on all platforms
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 18 Aug 2022 21:25:05 +0000 (17:25 -0400)]
drm/amd/display: Fix CAB cursor size allocation for DCN32/321
For calculating cursor size allocation, surface size was used, resulting
in over allocation
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Chen [Thu, 18 Aug 2022 17:21:37 +0000 (13:21 -0400)]
drm/amd/display: Missing HPO instance added
[Why & How]
Number of encoder is set to 4 but only 3 instances are created.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Thu, 4 Aug 2022 07:44:27 +0000 (15:44 +0800)]
drm/amd/display: Refactor edp dsc codes.
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh <mike.hsieh@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 15 Aug 2022 17:12:42 +0000 (13:12 -0400)]
drm/amd/display: SubVP missing scaling case
[Description]
For SubVP scaling case we have to combine
the plane scaling and stream scaling.
Use UCLK dummy p-state WM for FCLK WM set C
[Description]
For DCN32/321 program dummy UCLK P-state watermark into FCLK
watermark set C register.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Hanghong) Ma [Fri, 29 Jul 2022 15:46:13 +0000 (11:46 -0400)]
drm/amd/display: Add support for visual confirm color
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Thu, 18 Aug 2022 15:18:33 +0000 (11:18 -0400)]
drm/amd/display: Allow PHY state update between same states
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON, such as
when using MST or during resolution change. This is expected, so allow HW
programming to continue.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gabe Teeger [Thu, 18 Aug 2022 02:25:01 +0000 (22:25 -0400)]
drm/amd/display: Cleanup PSR flag
[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.
[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the case of dcn31 and above.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gabe Teeger [Tue, 16 Aug 2022 02:52:46 +0000 (22:52 -0400)]
drm/amd/display: Cursor lag with PSR1 eDP
[Why]
On edp with psr1, we do not provide updates
of the cursor position regularly to firmware
like with PSR2. To send updates regularly,
the flag enable_sw_cntl_psr has to equal 1,
but cursor update should be provided
regularly to FW regardless of that flag.
[How]
Ensure that we always send cursor updates to
firmware when PSR version equals 1.
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Wed, 17 Aug 2022 14:57:10 +0000 (10:57 -0400)]
drm/amd/display: Add DC debug option to force LTTPR mode
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Chen [Wed, 17 Aug 2022 15:15:48 +0000 (11:15 -0400)]
drm/amd/display: add a override flag as wa for some specific dongle
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen <sancchen@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo Chen <SanChuan.Chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Wed, 17 Aug 2022 14:47:59 +0000 (10:47 -0400)]
drm/amd/display: Only commit SubVP state after pipe programming
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Tue, 16 Aug 2022 21:10:50 +0000 (17:10 -0400)]
drm/amd/display: Remove assert from PHY state update
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wang Fudong [Wed, 17 Aug 2022 09:47:50 +0000 (17:47 +0800)]
drm/amd/display: set dig fifo read start level to 7 before dig fifo reset
[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.
[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR = 1.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Wang Fudong <Fudong.Wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YuBiao Wang [Wed, 24 Aug 2022 07:56:04 +0000 (15:56 +0800)]
drm/amdgpu: Fix use-after-free in amdgpu_cs_ioctl
[Why]
In amdgpu_cs_ioctl, amdgpu_job_free could be performed ealier if there
is -ERESTARTSYS error. In this case, job->hw_fence could be not
initialized yet. Putting hw_fence during amdgpu_job_free could lead to a
use-after-free warning.
[How]
Check if drm_sched_job_init is performed before job_free by checking
s_fence.
v2: Check hw_fence.ops instead since it could be NULL if fence is not
initialized. Reverse the condition since !=NULL check is discouraged in
kernel.
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Duncan Ma [Mon, 15 Aug 2022 21:37:32 +0000 (17:37 -0400)]
drm/amd/display: Fix OTG H timing reset for dcn314
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lewis Huang [Mon, 8 Aug 2022 05:20:16 +0000 (13:20 +0800)]
drm/amd/display: Refine aux transaction before retrieve caps
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
George Shen [Thu, 11 Aug 2022 02:06:17 +0000 (22:06 -0400)]
drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming
[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.
Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-to-1 with
HPO stream encoder instance. This is not always
guaranteed and can result in blackscreen.
[How]
Program the correct dpstreamclk instance with
the correct dtbclk_p source.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 15 Aug 2022 18:58:53 +0000 (14:58 -0400)]
drm/amd/display: Don't choose SubVP display if ActiveMargin > 0
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Fri, 12 Aug 2022 20:59:48 +0000 (16:59 -0400)]
drm/amd/display: Set ODM policy based on number of DSC slices
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 15 Aug 2022 04:18:45 +0000 (00:18 -0400)]
drm/amd/display: 3.2.200
This version brings along following fixes:
- Modify pipe split policy
- Fix odm 2:1 policy in 4k144 mode
- Correct HDMI ODM combine policy
- Change AUX NACK behavior
- Change runtime initialization for DCN32/321
- Fix cursor flicker in PSRSU
- Fix k1/k2 divider for virtual signal for DCN32
- Free phantom plane after removing the context
- Add interface to track PHY state
- Add SubVP scaling case
- Add log clock table for SMU
- Fix atomic_check check
- Fix SMU 13.0.0 driver_if header
- Fix doorbells allocation
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Yingliang [Fri, 26 Aug 2022 08:57:54 +0000 (16:57 +0800)]
drm/amdgpu: add missing pci_disable_device() in amdgpu_pmops_runtime_resume()
Add missing pci_disable_device() if amdgpu_device_resume() fails.
Fixes:
8e4d5d43cc6c ("drm/amdgpu: Handling of amdgpu_device_resume return value for graceful teardown")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
sunliming [Fri, 26 Aug 2022 08:41:21 +0000 (16:41 +0800)]
drm/amd/display: Fix variable dereferenced before check
Fixes the following smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311 dc_dmub_srv_p_state_delegate()
warn: variable dereferenced before check 'dc' (see line 309)
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: sunliming <sunliming@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ye xingchen [Fri, 26 Aug 2022 07:23:57 +0000 (07:23 +0000)]
drm/amdgpu: Remove the unneeded result variable
Return the value sdma_v5_2_start() directly instead of storing it in
another redundant variable.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Graham Sider [Mon, 15 Aug 2022 17:28:19 +0000 (13:28 -0400)]
drm/amdgpu: Update mes_v11_api_def.h
New GFX11 MES FW adds the trap_en bit. For now hardcode to 1 (traps
enabled).
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Wed, 24 Aug 2022 15:00:02 +0000 (23:00 +0800)]
drm/amdgpu: disable FRU access on special SIENNA CICHLID card
Below driver load error will be printed, not friendly to end user.
amdgpu: ATOM BIOS: 113-D603GLXE-077
[drm] FRU: Failed to get size field
[drm:amdgpu_fru_get_product_info [amdgpu]] *ERROR* Failed to read FRU Manufacturer, ret:-5
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bernard Zhao [Tue, 23 Aug 2022 06:41:31 +0000 (23:41 -0700)]
drm/amd: remove possible condition with no effect (if == else)
This patch fix cocci warning:
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c:1816:6-8:
WARNING: possible condition with no effect (if == else).
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bernard Zhao [Tue, 23 Aug 2022 07:00:44 +0000 (00:00 -0700)]
drm/amd: remove possible condition with no effect (if == else)
This patch fix cocci warning:
drivers/gpu/drm/amd/display/dc/core/dc.c:3335:2-4: WARNING:
possible condition with no effect (if == else).
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bernard Zhao [Tue, 23 Aug 2022 06:35:24 +0000 (23:35 -0700)]
drm/amd: fix potential memory leak
This patch fix potential memory leak (clk_src) when function run
into last return NULL.
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bernard Zhao [Tue, 23 Aug 2022 06:49:56 +0000 (23:49 -0700)]
drm/amd: fix potential memory leak
This patch fix potential memory leak (clk_src) when function run
into last return NULL.
s/free/kfree/ - Alex
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / platform / kernel / linux-starfive.git / log