Ian Romanick [Thu, 1 Sep 2016 01:42:34 +0000 (18:42 -0700)]
glsl: Remove ir_function_signature::_is_intrinsic field
text data bss dec hex filename
6036491 283160 28608 6348259 60dde3 lib64/i965_dri.so before
6036395 283160 28608 6348163 60dd83 lib64/i965_dri.so after
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Thu, 1 Sep 2016 01:38:57 +0000 (18:38 -0700)]
glsl: Add ir_function_signature::is_intrinsic() method
This necessetated renaming the is_intrinsic field to _is_intrinsic. The
next commit will remove the field.
text data bss dec hex filename
6036507 283160 28608 6348275 60ddf3 lib64/i965_dri.so before
6036491 283160 28608 6348259 60dde3 lib64/i965_dri.so after
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Thu, 1 Sep 2016 01:09:27 +0000 (18:09 -0700)]
glsl: Use the ir_intrinsic_* enums instead of the __intrinsic_* name strings
text data bss dec hex filename
6038043 283160 28608 6349811 60e3f3 lib64/i965_dri.so before
6036507 283160 28608 6348275 60ddf3 lib64/i965_dri.so after
v2: s/ir_intrinsic_atomic_sub/ir_intrinsic_atomic_counter_sub/. Noticed
by Ilia.
v3: Silence unhandled enum in switch warnings in st_glsl_to_tgsi.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Wed, 31 Aug 2016 00:49:24 +0000 (17:49 -0700)]
glsl: Track a unique intrinsic ID with each intrinsic function
text data bss dec hex filename
6037483 283160 28608 6349251 60e1c3 lib64/i965_dri.so before
6038043 283160 28608 6349811 60e3f3 lib64/i965_dri.so after
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ian Romanick [Mon, 3 Oct 2016 22:47:29 +0000 (15:47 -0700)]
glsl: Don't emit ir_binop_carry during ir_binop_imul_high lowering
st_glsl_to_tgsi only calls lower_instructions once (instead of in a
loop), so the ir_binop_carry generated would not get lowered. Fixes
assertion failure
state_tracker/st_glsl_to_tgsi.cpp:2265: void glsl_to_tgsi_visitor::visit_expression(ir_expression*, st_src_reg*): Assertion `!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()"' failed.
on softpipe in 16 piglit tests:
mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended-only-msb-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended-only-msb.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended-only-msb-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended-only-msb.shader_test
mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended-only-msb-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended-only-msb.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended-only-msb-nonuniform.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended-only-msb.shader_test
mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended.shader_test
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Tue, 4 Oct 2016 00:15:08 +0000 (11:15 +1100)]
i965: fix unused variable warning in brw_emit_gpgpu_walker()
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Tue, 4 Oct 2016 00:15:07 +0000 (11:15 +1100)]
i965: add MAYBE_UNUSED to assert param
Fixes unused variable warning in release build.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Tue, 4 Oct 2016 00:15:06 +0000 (11:15 +1100)]
i965: wrap unused function in #ifndef NDEBUG
This function is only ever used by an assert() this fixes an
unused function warning in release builds.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Tue, 4 Oct 2016 00:15:05 +0000 (11:15 +1100)]
i965: fix unused variable warning in gen7_block_read_scratch()
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Tue, 4 Oct 2016 00:15:04 +0000 (11:15 +1100)]
i965: add MAYBE_UNUSED to assert param
This fixes an unused variable warning on release builds.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jose Fonseca [Fri, 1 Apr 2016 23:20:00 +0000 (00:20 +0100)]
gallivm: Use AVX2 gather instrinsics.
v2: Use AVX2 gather for non aligned loads too.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Roland Scheidegger [Thu, 21 Nov 2013 09:14:47 +0000 (09:14 +0000)]
gallivm: Use 8 wide AoS sampling on AVX2.
v2: Make sure that with num_lods > 1 and min_filter != mag_filter we
still enter the splitting path. So this case would still use 4-wide aos
path (as a side note, the 4-wide aos sampling path could actually be
improved quite a bit if we have avx2, by just doing the filtering with
256bit vectors).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
José Fonseca [Wed, 20 Nov 2013 08:32:52 +0000 (08:32 +0000)]
gallivm: Basic AVX2 support.
v2: pblendb -> pblendvb
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Chad Versace [Tue, 27 Sep 2016 20:27:19 +0000 (13:27 -0700)]
egl: Drop duplicate check on EGLSync type
_eglInitSync checked that the display supported the sync type (such as
EGL_SYNC_FENCE), and did it wrong. When the check failed it emitted
EGL_BAD_ATTRIBUTE, but sometimes EGL_BAD_PARAMETER is needed.
_eglCreateSync already does the error checking, and it does it right.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chad Versace [Tue, 27 Sep 2016 20:27:18 +0000 (13:27 -0700)]
egl: Cleanup control flow in _eglParseSyncAttribList
When the function encountered an error, it effectively returned
immediately. However, it did so indirectly by breaking out of a loop.
Replace the loop breakout with a explicit 'return'.
Do the same for _eglParseSyncAttribList64 too.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chad Versace [Tue, 27 Sep 2016 20:27:17 +0000 (13:27 -0700)]
egl: Add _eglConvertIntsToAttribs()
This function converts an attribute list from EGLint[] to EGLAttrib[].
Will be used in following patches to cleanup EGLSync attribute parsing.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chad Versace [Tue, 27 Sep 2016 20:27:12 +0000 (13:27 -0700)]
egl: Fix an error path in eglCreateSync*
When the user called eglCreateSync64KHR on a display without
EGL_KHR_cl_event2 (the only extension that exposes it), we returned
EGL_NO_SYNC but did not update the error code.
We also did the same for eglCreateSync on a display without EGL 1.5.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chad Versace [Tue, 27 Sep 2016 20:27:09 +0000 (13:27 -0700)]
egl: Fix truncation error in _eglParseSyncAttribList64
The function stores EGLAttrib values in EGLint variables. On 64-bit
systems, this truncated the values.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chad Versace [Wed, 28 Sep 2016 06:06:37 +0000 (23:06 -0700)]
egl: Fix missing unlock in eglGetSyncAttribKHR
On the error path, eglGetSyncAttribKHR neglected to unlock the
EGLDisplay before returning.
Fixes deadlock in dEQP-EGL.functional.fence_sync.invalid.get_invalid_value.
Cc: mesa-stable@lists.freedesktop.org
Cc: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Anuj Phogat [Mon, 3 Oct 2016 17:40:34 +0000 (10:40 -0700)]
anv/gen7_pipeline: Fix typo in semicolon
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 18:40:00 +0000 (11:40 -0700)]
anv/gen7_pipeline: Set sample mask field in 3DSTATE_PS
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 18:32:55 +0000 (11:32 -0700)]
anv/gen7_pipeline: Move ksp{1,2} state setting next to ksp0
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 18:10:56 +0000 (11:10 -0700)]
anv/gen7: Make use of local variable prog_data
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 18:08:33 +0000 (11:08 -0700)]
anv/gen8_pipeline: Add an assert to ensure use_alt_mode is not set in prog_data
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Anuj Phogat [Mon, 26 Sep 2016 18:07:38 +0000 (11:07 -0700)]
anv/gen8_pipeline: Fix typo in semicolon
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 18:04:50 +0000 (11:04 -0700)]
intel/genxml: Keep the value name 'Alternate' uniform across gen75.xml
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 18:01:40 +0000 (11:01 -0700)]
intel/genxml: Fix typo in gen75.xml
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Tue, 27 Sep 2016 19:28:39 +0000 (12:28 -0700)]
i965/gen8+: Enable GL_OES_viewport_array
This patch causes 2 regressions in khronos' gles cts tests
on various intel platforms.
Failing tests:
ES3-CTS.functional.state_query.integers.viewport_getinteger
ES3-CTS.functional.state_query.integers.viewport_getfloat
Here is an explanation of what's causing the failures:
CTS tests are not clamping the x, y location of the viewport's
bottom-left corner as recommended by ARB_viewport_array and
OES_viewport_array:
"The location of the viewport's bottom-left corner, given by (x,y), are
clamped to be within the implementation-dependent viewport bounds range.
The viewport bounds range [min, max] tuple may be determined by
calling GetFloatv with the symbolic constant VIEWPORT_BOUNDS_RANGE_OES"
Khronos CTS merge request to fix the test case:
https://gitlab.khronos.org/opengl/cts/merge_requests/399
V2: Initialize the relevant variables for GL_OES_viewport_array on gen8+
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Anuj Phogat [Wed, 28 Sep 2016 18:40:37 +0000 (11:40 -0700)]
mesa: Add a check for OES_viewport_array
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Anuj Phogat [Wed, 28 Sep 2016 18:39:39 +0000 (11:39 -0700)]
mesa: Enable enums for OES_viewport_array
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Anuj Phogat [Tue, 27 Sep 2016 19:24:56 +0000 (12:24 -0700)]
anv/gen7_pipeline: Use MSDISPMODE_PERSAMPLE for non-multisampled fbo
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Mon, 26 Sep 2016 17:17:49 +0000 (10:17 -0700)]
anv/blorp: Handle zero width/height blits in blorp_copy()
V2: Move the check from copy_buffer_to_image() to blorp_copy(). (Nanley)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Tue, 20 Sep 2016 18:59:01 +0000 (11:59 -0700)]
intel/isl: Add an assert to check zero width/height surface
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Leo Liu [Thu, 29 Sep 2016 20:55:59 +0000 (16:55 -0400)]
st/omx/dec/h265: add scaling list data
Specified by subclause 7.3.4
v2: get the loop optimized
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Fri, 23 Sep 2016 16:05:16 +0000 (12:05 -0400)]
st/omx/dec/h265: fix the skip for before and after list
For reference picture sets, there are cases that rps will not always
be used. Once detect the unused flag from encoded bitstream, we should
not add this rps to any list, otherwise pass the incorrect reference
and skip the correct rps.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Leo Liu [Fri, 23 Sep 2016 15:42:16 +0000 (11:42 -0400)]
st/omx/dec/h265: set the default reference picture set for reference
It will fix the corruption for frame, that only has one stort term ref
picture set, we set NULL rps for this case previously, causing taking
incorrect reference. Instead we should take that only short term set
as reference
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Leo Liu [Fri, 23 Sep 2016 15:33:31 +0000 (11:33 -0400)]
st/omx/dec/h265: decoder size should follow from sps
The video size from format container is not always compatible with
the size from codec bitstream, the HW decoder should take the size
information from bitstream, otherwise the corruption appears with clip
that has different size info between bitstream and format container
So we are passing width(height)_in_samples from sequence parameter
set to video decoder.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Leo Liu [Fri, 23 Sep 2016 15:11:53 +0000 (11:11 -0400)]
st/omx/dec/h265: increase dpb max size to 32
For clip with frame delta poc over 16
Signed-off-by: Leo Liu <leo.liu@amd.com>
Eric Engestrom [Sun, 2 Oct 2016 11:15:53 +0000 (12:15 +0100)]
nir/spirv: Remove a duplicate spirv2nir from .gitignore
This reverts commit
fc03ecfeaf5a10a8b84d366f24f02e74ab03b145.
Chad had already pushed the same change between me posting the patch and Jason
pushing it:
44bcf1ffcced04fd7f2b (".gitignore: Ignore src/compiler/spirv2nir")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nicolai Hähnle [Wed, 28 Sep 2016 19:44:55 +0000 (21:44 +0200)]
radeonsi: optionally run the LLVM IR verifier pass
This is enabled automatically if shader printing is enabled, or separately
by R600_DEBUG=checkir. Catch mal-formed IR before it crashes in a later
pass.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 29 Sep 2016 12:55:51 +0000 (14:55 +0200)]
gallium/radeon: fix argument type of llvm.{cttz,ctlz}.i32 intrinsics
Caught by R600_DEBUG=checkir (next commit).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 28 Sep 2016 19:27:16 +0000 (21:27 +0200)]
gallium/radeon: unify the creation of basic blocks
This changes the order of basic blocks to be equal to the order of code in the
original TGSI, which is nice for making sense of shader dumps.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 28 Sep 2016 19:17:56 +0000 (21:17 +0200)]
gallium/radeon: merge branch and loop flow control stacks
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 28 Sep 2016 16:59:42 +0000 (18:59 +0200)]
gallium/radeon: simplify if/else/endif blocks
In particular, we no longer emit an else block when there is no ELSE
instruction.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 28 Sep 2016 16:30:09 +0000 (18:30 +0200)]
gallium/radeon: label basic blocks by the corresponding TGSI pc
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 28 Sep 2016 16:20:32 +0000 (18:20 +0200)]
gallium/radeon: cleanup and fix branch emits
Some of the existing code is needlessly complicated. The basic principle
should be: control-flow opcodes emit branches to properly terminate the
current block, _unless_ the current block already has a terminator (which
happens if and only if there was a BRK or CONT).
This also fixes a bug where multiple terminators were created in a block.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97887
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 4 Oct 2016 08:50:55 +0000 (10:50 +0200)]
winsys/radeon: add buffer_get_reloc_offset
Really fix the bug that was supposed to be fixed by commits
3e7cced4b and
a48bf02d: even when virtual addresses are used, the legacy relocation-based
method with offsets relative to the kernel's buffer object are used for
video submissions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sun, 2 Oct 2016 20:01:38 +0000 (22:01 +0200)]
radeonsi: don't declare LDS in PS when ds_bpermute is used
I guess this is not needed because dead code elimination removes
the declaration.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 19:56:00 +0000 (21:56 +0200)]
radeonsi: use DDX/DDY directly in si_llvm_emit_ddxy_interp
We can finally do this, because the opcodes are scalar now.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 19:37:13 +0000 (21:37 +0200)]
radeonsi: simplify si_llvm_emit_ddxy
si_llvm_emit_ddxy is called once per element, so we don't have to generate
code for 4 elements at once.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 19:23:26 +0000 (21:23 +0200)]
radeonsi: don't call build_gep0 in si_llvm_emit_ddxy on VI
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 18:54:30 +0000 (20:54 +0200)]
radeonsi: use a helper function for BuildGEP(0, x)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 18:21:19 +0000 (20:21 +0200)]
radeonsi: remove obsolete shader definitions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 15:52:46 +0000 (17:52 +0200)]
radeonsi: remove unnecessary #includes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 15:40:49 +0000 (17:40 +0200)]
radeonsi: clean up lucky #include dependencies
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sat, 11 Jun 2016 19:07:14 +0000 (21:07 +0200)]
radeonsi: don't re-create shader PM4 states after scratch buffer update
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 14:12:47 +0000 (16:12 +0200)]
gallium/radeon: move r600_common_context::texture_buffers to r600g
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 14:05:51 +0000 (16:05 +0200)]
radeonsi: don't set sampler buffer offsets in create_sampler_view
do it at bind time, so that pipe_sampler_view is immutable with regard to
buffer reallocations and we don't have to remember all existing buffer
views.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 13:50:15 +0000 (15:50 +0200)]
radeonsi: optimize si_invalidate_buffer based on bind_history
Just enclose each section with: if (rbuffer->bind_history & PIPE_BIND_...)
Bioshock Infinite: +1% performance
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 13:45:15 +0000 (15:45 +0200)]
radeonsi: track buffer bind history
similar to gl_buffer_object::UsageHistory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 13:40:10 +0000 (15:40 +0200)]
radeonsi: drop support for NULL sampler views
not used anymore. It was used when the polygon stipple texture was constant.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Fri, 30 Sep 2016 20:47:20 +0000 (22:47 +0200)]
radeonsi: separate IA_MULTI_VGT_PARAM and VGT_PRIMITIVE_TYPE emission
We want to emit IA_MULTI_VGT_PARAM less often because it's a context reg.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Fri, 30 Sep 2016 20:37:14 +0000 (22:37 +0200)]
radeonsi: move VGT_LS_HS_CONFIG to derived tess_state
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Fri, 30 Sep 2016 22:46:39 +0000 (00:46 +0200)]
radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER
Caches are always flushed at IB boundary.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Fri, 30 Sep 2016 18:20:32 +0000 (20:20 +0200)]
radeonsi: parse SURFACE_SYNC correctly on CIK-VI
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Sun, 2 Oct 2016 13:36:19 +0000 (15:36 +0200)]
gallium/radeon: inline r600_context_add_resource_size
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
James Legg [Tue, 4 Oct 2016 13:30:11 +0000 (14:30 +0100)]
radeonsi: Fix primitive restart when index changes
If primitive restart is enabled for two consecutive draws which use
different primitive restart indices, then the first draw's primitive
restart index was incorrectly used for the second draw.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98025
Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 4 Oct 2016 00:25:25 +0000 (11:25 +1100)]
spirv: replace assert() with unreachable()
This fixes an uninitialized warning for is_vertex_input.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Tue, 4 Oct 2016 01:03:14 +0000 (12:03 +1100)]
intel: use the correct format specifier for printing uint64_t
Fixes a bunch of warnings in 32-bit builds.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Whitlock [Sun, 2 Oct 2016 03:49:45 +0000 (23:49 -0400)]
gallium/winsys: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Without this fix, duplicated file descriptors leak into child processes.
See commit
aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Matt Whitlock [Sun, 2 Oct 2016 03:49:44 +0000 (23:49 -0400)]
st/xa: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Without this fix, duplicated file descriptors leak into child processes.
See commit
aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Matt Whitlock [Sun, 2 Oct 2016 03:49:43 +0000 (23:49 -0400)]
st/dri: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Without this fix, duplicated file descriptors leak into child processes.
See commit
aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Matt Whitlock [Sun, 2 Oct 2016 03:49:42 +0000 (23:49 -0400)]
gallium/auxiliary: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Without this fix, duplicated file descriptors leak into child processes.
See commit
aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Matt Whitlock [Sun, 2 Oct 2016 03:49:41 +0000 (23:49 -0400)]
egl/android: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Without this fix, duplicated file descriptors leak into child processes.
See commit
aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tapani Pälli [Mon, 3 Oct 2016 06:32:54 +0000 (09:32 +0300)]
intel: fix compilation warning on gen_get_device_info
(warning: 'const' type qualifier on return type has no effect)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Mon, 26 Sep 2016 17:30:30 +0000 (10:30 -0700)]
i965: Only emit 1 viewport when possible.
In core profile, we support up to 16 viewports. However, in the
majority of cases, only 1 of them is actually used - we only need
the others if the last shader stage prior to the rasterizer writes
gl_ViewportIndex.
Processing all 16 viewports adds additional CPU overhead, which hurts
CPU-intensive workloads such as Glamor. This meant that switching to
core profile actually penalized Glamor to an extent, which is
unfortunate.
This patch tracks the number of relevant viewports, switching between
1 and ctx->Const.MaxViewports if gl_ViewportIndex is written. A new
BRW_NEW_VIEWPORT_COUNT flag tracks this. This could mean re-emitting
viewport state when switching, but hopefully this is offset by doing
1/16th of the work in the common case. The new flag is also lighter
weight than BRW_NEW_VUE_MAP_GEOM_OUT, which we were using in one case.
According to Eric Anholt, x11perf -copypixwin10 performance improves by
11.5094% +/- 3.10841% (n=10) on his Skylake.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Dave Airlie [Mon, 29 Aug 2016 00:18:15 +0000 (10:18 +1000)]
spirv: translate cull distance semantic.
This just translates to the correct cull distance slot.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 29 Aug 2016 00:17:16 +0000 (10:17 +1000)]
compiler: add printable values for cull distance varyings.
We need these for spir-v/nir shaders.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Fri, 16 Sep 2016 04:12:34 +0000 (21:12 -0700)]
nir/spirv/cfg: Use a nop intrinsic for tagging the ends of blocks
Previously, we were saving off the last nir_block in a vtn_block before
moving on so that we could find the nir_block again when it came time to
handle phi sources. Unfortunately, NIR's control flow modification code is
inconsistent when it comes to how it splits blocks so the block pointer we
saved off may point to a block somewhere else in the shader by the time we
get around to handling phi sources. In order to get around this, we insert
a nop instruction and use that as the logical end of our block. Since the
control flow manipulation code respects instructions, the nop will keeps
its place like any other instruction and we can easily find the end of our
block when we need it.
This fixes a bug triggered by a couple of vkQuake shaders.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97233
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 16 Sep 2016 04:02:37 +0000 (21:02 -0700)]
nir: Add a nop intrinsic
This intrinsic has no destination, no sources, no variables, and can be
eliminated. In other words, it does nothing and will always get deleted by
dead code elimination. However, it does provide a quick-and-easy way to
temporarily tag a particular location in a NIR shader.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 13 Sep 2016 00:56:38 +0000 (17:56 -0700)]
intel/isl: Allow non-2D HiZ surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 22:45:18 +0000 (15:45 -0700)]
intel/isl: Add a detailed comment about multisampling with HiZ
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 05:25:50 +0000 (22:25 -0700)]
intel/isl: Remove tiling checks from choose_msaa_layout
We already do those checks in filter_tiling. There's no good reason to
repeat them in choose_msaa_layout. If anything they should have been
asserts and not "return false" checks. Also, this check was causing us to
outright reject multisampled HiZ surfaces which wasn't intended.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 05:01:47 +0000 (22:01 -0700)]
intel/isl: Handle HiZ and CCS tiling more directly
The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces
respectively. There's no reason why we should go through filter_tiling and
it's much easier to always get HiZ and CCS right if we just handle them
directly.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 01:57:18 +0000 (18:57 -0700)]
intel/isl: Allow multisampling with ISL_FORMAT_HiZ
HiZ buffers can be multisampled and, on Broadwell and earlier, simply using
interleaved multisampling with a compression block size of 8x4 samples
yields the correct HiZ surface size calculations. Unfortunately,
choose_msaa_layout was rejecting multisampled HiZ buffers because of format
checks. Now that we have a simple helper for determining if a format
supports multisampling, that's an easy enough issue to fix.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 13 Sep 2016 00:43:28 +0000 (17:43 -0700)]
intel/isl: Allow creation of 1-D compressed textures
Compressed 1-D textures are not well-defined thing in either GL or Vulkan.
However, auxiliary surfaces are treated as compressed textures in ISL and
we can do HiZ and CCS with 1-D so we need to be able to create them. In
order to prevent actually using them (the docs say no), we assert in the
state setup code.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 02:52:38 +0000 (19:52 -0700)]
intel/isl: Fix up asserts in calc_phys_level0_extent_sa
The assertion that a format is uncompressed in the multisample layouts
isn't quite right. What we really want to assert is that the format
supports multisampling which is a bit more complicated query. We also want
to assert that it has a block size of 1x1 since we do nothing with the
block size in the phys_level0_sa assignment.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 2 Sep 2016 01:57:01 +0000 (18:57 -0700)]
intel/isl: Add a format_supports_multisampling helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Nayan Deshmukh [Sat, 1 Oct 2016 05:22:52 +0000 (10:52 +0530)]
vl/dri3: fix warning about incompatible pointer type
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Bruce Cherniak [Tue, 27 Sep 2016 18:27:08 +0000 (13:27 -0500)]
swr: Removed stalling SwrWaitForIdle from queries.
Previous fundamental change in stats gathering added a temporary
SwrWaitForIdle to begin_query and end_query. Code has been reworked to
remove stall.
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Tim Rowley [Fri, 30 Sep 2016 21:05:19 +0000 (16:05 -0500)]
swr: [rasterizer core] refactor thread creation
Create worker pool now computes number of worker threads based on
things like topologies, etc. and creates the pool but doesn't actually
launch the threads. Instead there is a separate start thread pool
function. This allows thread resources to be constructed first before
threads start.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Fri, 30 Sep 2016 20:18:13 +0000 (15:18 -0500)]
swr: [rasterizer jitter] canonicalize blend compile state
Canonicalize to prevent unnecessary JIT compiles.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 22 Sep 2016 23:00:47 +0000 (18:00 -0500)]
swr: [rasterizer core] archrast fixes
- Immediately sleep threads until thread data is initialized
- Fix some compile bugs with AR enabled
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Tue, 20 Sep 2016 22:14:54 +0000 (17:14 -0500)]
swr: [rasterizer jitter] fixes for icc in vs2015 compat mode
- Move most jitter functionality into SwrJit namespace
- Avoid global "using namespace llvm" in headers
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 21 Sep 2016 18:39:44 +0000 (13:39 -0500)]
swr: [rasterizer core] generalize compute dispatch mechanism
Generalize compute dispatch mechanism to support other types of dispatches.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 21 Sep 2016 04:55:24 +0000 (23:55 -0500)]
swr: [rasterizer common] os.h portability header changes
- Fix conflict between windows MemoryFence and llvm::sys::MemoryFence
- Declare gettid()
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Ville Syrjälä [Fri, 30 Sep 2016 20:00:22 +0000 (23:00 +0300)]
anv/formats: Fix build on gcc-4 and earlier
gcc-4 and earlier don't allow compound literals where a constant
is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
when populating the anv_formats[] array. There are a few ways around
it: First one would be -std=c89/gnu89, but the rest of the code
depends on c99 so it's not really an option. The second option
would be to upgrade to gcc-5+ where the compiler behaviour was relaxed
a bit [1]. And the third option is just to avoid using compound
literals. I chose the last option since it keeps gcc-4 and earlier
working.
[1] https://gcc.gnu.org/gcc-5/porting_to.html
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes:
7ddb21708c80 ("intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tapani Pälli [Mon, 26 Sep 2016 07:03:32 +0000 (10:03 +0300)]
egl: stop claiming support for pbuffer + msaa
This fixes a crash in egl-create-msaa-pbuffer-surface Piglit test
and same crash in many dEQP EGL tests.
I also found that some Qt example did a workaround because of this
crash: https://bugreports.qt.io/browse/QTBUG-47509
v2: Ian pointed out that v1 removed support for all multisample
configs, including window ones. This one removes pbuffer bit
when adding configs, now only pbuffer+msaa gets rejected and
window+msaa continues to work. Fixed also comment (Emil)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Sun, 2 Oct 2016 23:39:29 +0000 (10:39 +1100)]
i965: rename max_ds_* variable to max_tes_*
Using consistent naming allows us to create macros more easily.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 2 Oct 2016 23:39:28 +0000 (10:39 +1100)]
i965: rename max_hs_* variables to max_tcs_*
Using consistent naming allows us to create macros more easily.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>